No part of this manual may be reproduced by any means without written
permission from SBE, Inc., except that the purchaser may copy necessary
portions for internal use only.
While every effort has been made to ensure the accuracy of this manual, SBE
cannot be held responsible for damage resulting from information herein. All
specifications are subject to change without notice.
SBE, Inc. and the SBE logo are trademarks of SBE, Inc.
All other trademarks and copyrights are owned by their respective companies.
About SBE, Inc. SBE designs and provides IP-based networking solutions for
an extensive range of applied computing applications. SBE delivers a portfolio
of scalable, standards-based hardware and software products, including iSCSI
and VoIP, designed to enable optimal performance and rapid deployment
across a wide range of next generation communications and storage systems.
SBE is based in San Ramon, California, and can be reached at 925-355-2000
or online at http://www.sbei.com.
October 10, 2006 Copyright 2006, SBE, Inc. Page ii
HighWire HW400c/2 User Reference Guide Rev 1.0
Revision History
RevisionDateChanges
1.0 October 10, 2006 Initial Release
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THIS PAGE IS INTENTIONALLY LEFT BLANK
October 10, 2006 Copyright 2006, SBE, Inc. Page iv
Table 7. J8 and J9 pin out ..........................................................................................................................15
Table 58. EEPROM Data Registers (EDRn) Offset Address 0x2A-0x2B ................................................63
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HighWire HW400c/2 User Reference Guide Rev 1.0
Conventions
The following conventions are used in this document:
A # following a signal name, e.g., INTA#, represents an active low signal.
A / preceding a signal name, e.g., /INTA represents an active low signal.
0x preceding a number represents a Hexadecimal value.
A number in “ ” preceded by H represents a Hexadecimal value.
A number in “ ” preceded by B represents a Binary value.
A register or bit name that ends with _EN indicates an enable function
A register or bit name that ends with _N indicates an asserted low function
Typeface courier is used to designate code and/or terminal input.
Draws attention to important information related to the nearby text.
Refers to information about potential hazards to equipment or personnel.
!
October 10, 2006 Copyright 2006, SBE, Inc. Page xii
HighWire HW400c/2 User Reference Guide Rev 1.0
1 ABOUT THIS MANUAL
This manual is technical reference for the HighWire HW400c/2 Gigabit Switched
PTMC Processing Platform for CompactPCI. This manual is intended for those who
are installing the HW400c/2 into a system.
The HighWire HW400c/2 User Reference Manual includes the following:
• Introduction and background on the HighWire HW400c/2
• Hardware reference material
• Hardware installation instructions
• Programming information
• Physical characteristics and specifications
• Operating System Software environment and installation
October 10, 2006 Copyright 2006, SBE, Inc. Page 1
HighWire HW400c/2 User Reference Guide Rev 1.0
2 INTRODUCTION
The HW400c/2 is a flexible high-performance core processing platform for building
powerful processor enabled CompactPCI (CPCI) telephony and data communications
I/O solutions. Advanced features on the HW400c/2 include two PCI Telecom
Mezzanine Card (PTMC) sites for CT Bus enabled I/O interfaces that are
interconnected through a high-speed Layer 2 Gigabit Ethernet switch to the dual node
CompactPCI Packet Switched Backplane (cPSB). The HighWire core architecture
utilizes the Freescale MPC7447A PowerPC processor and Marvell Discovery™ III
system controller to provide a powerful computing environment for addressing a
wide range of communications applications.
The HW400c/2 is optimized for packet-based switch fabric system architectures and
is fully compliant with the PICMG 2.16 cPSB specification. The cPSB standard
provides a switched fabric backplane interconnection using Ethernet technology
overlaid on the standard CPCI J3 connector. Dual Gigabit Ethernet interfaces are
provided on the HW400c/2 cPSB interface to support both the high availability dual
node and reduced cost single node configurations.
Full CPCI compliance and interoperability are maintained including Hot Swap,
H.110 CT Bus and rear I/O support.
2.1 Product Description
The HW400c/2 is built on SBE’s advanced HighWire core architecture, and features
the MPC7447A PowerPC processor, Marvell Discovery III system controller, up to
1GB DDR SDRAM and Disk-on-Chip flash file system storage to meet the
demanding needs of today’s telecom and datacom applications. Additional developer
features including a serial console port and a COP emulator port help speed code
development. The HW400c/2 also fully supports the Intelligent Platform
Management Interface (IPMI) standard (PICMG 2.9) for system management.
The two expansion sites accept both CT Bus enabled PTMC modules and standard
PMC modules. PT2MC modules have access to the on-board local CT Bus and
timeslot interchange fabric allowing flexible routing of TDM timeslots both between
the PTMC sites and the H.110 backplane CT Bus. PT5MC modules also include
Gigabit Ethernet connectivity to platform resources. The HW400c/2 automatically
detects each module type to provide full mix and match support for using PT2MC,
PT5MC or PMC modules in either site.
The 32-bit 33-133 MHz PCI/PCI-X interface supports 3.3V signaling modules with
full support for both front and rear I/O access per PICMG 2.3 mapping.
In addition, a 10/100/1000 Ethernet port for system management and application
flexibility is included through a front panel RJ45 connector on the board.
Figure 1 shows the block diagram of the HW400c/2.
October 10, 2006 Copyright 2006, SBE, Inc. Page 2
HighWire HW400c/2 User Reference Guide Rev 1.0
r
L
r
Temp
Temp
Sensors
Sensors
SDRAM
SDRAM
Console
RJ45
CPLD
Boot
ROM
SRAM
Disk on
Chip
Ene t
RJ45
Flash
Flash
Memor
Memory
IPMI
Controller
Microwire
Ser ia l
EEPROM
10/100/
1000
Phy
Processo
Motorola
MPC7447A
System Controlle
Discovery III
Enet
MAC
I2C
Config.
ROM
Layer 2
Ethernet
PTMC Site A
Config #2 or #5
GigE o r
TDMPCI-X
Rear I /O
PhyPhy
PTMC Site B
Config #2 or #5
GigE or
TDMPCI-X
Rear I/O
Switch
H.110
Controller
Hot S wap
J1
PCI
J2
PCI-64
Controller
J3
PSB
J4
H.110
J5
Rear I/ O
Figure 1. HW400c/2 Block Diagram
2.2 Unpacking Instructions
• If the carton is damaged when you receive it, request that the carrier's agent be
present when you unpack and inspect the equipment.
• After unpacking, verify that all items listed in the packing list are present.
• Inspect the equipment for shipping damage.
• Save all packing material for storage or return shipment of the equipment.
• For repairs or replacement of equipment damaged during shipment, contact SBE,
Inc. to obtain a Return Materials Authorization (RMA) number and further
shipping instructions.
October 10, 2006 Copyright 2006, SBE, Inc. Page 3
HighWire HW400c/2 User Reference Guide Rev 1.0
2.3 Handling Procedures
The HW400c/2 board uses CMOS components that can be easily damaged by static
electrical discharge. To avoid damage, familiarize yourself with electrostatic
discharge (ESD) procedures, which include the following precautions:
• The board should be handled only by trained service personnel at an approved
ESD workstation.
• Refer to ANSI/IPC-A-610 developed by the Institute for Interconnecting and
Packaging Electronic Circuits (IPC).
• Keep the board in a sealed conductive plastic bag while in transit.
• When installing the board in the field, ground yourself to the system chassis
before removing the board from the sealed conductive plastic bag (the power
plug must be installed on the system for this to be effective).
• Any equipment used to work on the board must be grounded. Any person
handling the board must be grounded.
• Check alignment and polarization of cables and connectors before applying
power.
• Do not apply external voltages to any devices on the board with power removed
from the board.
• Do not attempt to straighten any part soldered to the board, as pin breakage or
internal damage could occur.
2.4 Hardware Installation of the HW400c/2
The HW400c/2 is designed for use in a 6U CompactPCI enclosure.
Be sure to follow safe ESD procedures when handling electronic hardware.
!
• Remove the HW400c/2 from the protective bag.
• Slide the HW400c/2 into an available peripheral board slot in the CompactPCI
chassis. Check that the board is aligned properly on the card guides.
• Completely insert the board until the top and bottom board ejectors lock into
place. If chassis power is on the blue hot swap LED will blink and turn off.
• Tighten top and bottom screws to secure the HW400c/2 in place.
October 10, 2006 Copyright 2006, SBE, Inc. Page 4
HighWire HW400c/2 User Reference Guide Rev 1.0
2.5 Returns/Service
Before returning any equipment for service, you must obtain a Return Material
Authorization (RMA) number from SBE:
TEL: 800-925-2666 (Toll free, USA)
TEL: +925-355-2000 (Outside of USA)
FAX: +925-355-2020
Ship all returns to SBE’s USA service center:
SBE, Inc.
4000 Executive Parkway, Suite 200
San Ramon, CA 94583
SBE’s Technical Support Department can be reached at 800-444-0990.
2.6 Operating Environment
The HW400c/2 is designed to function within the environment shown in Table 1.
Table 1. HW400c/2 Operating Environment
Storage temperature
Operating temperature:
Operating humidity: 10% to 90% non-condensing
Storage humidity: 5% to 95% non-condensing
Power requirements: 36.5 Watts max. (estimated, basic configuration)
Voltages:
Bring the HW400c/2 board to operating temperature in a non-condensing
!
environment. The rate of change in board temperature should not exceed
2 °C (35.6 °F) per minute.
-40 to +85 C (-40 to +185 °F)
0 to 55 °C (32 to 131 °F) ambient temperature with a minimum
of 200 LFM airflow (basic configuration)
5V +5%/-3%, 3.3V +5%/-3%, 12V ±5% (all required)
October 10, 2006 Copyright 2006, SBE, Inc. Page 5
HighWire HW400c/2 User Reference Guide Rev 1.0
2.7 Mean Time Between Failures (MTBF)
The Mean Time Between Failure (MTBF) of SBE, Inc’s HW400c/2 was
calculated per Telcordia Technical Reference TR-332 Issue 6, December
Controlled, fixed, ground (mult. factor = 1.0)
Quality level II parts (level I on Rs, Cs and LEDs)
50 C
>150,000 hours (not including installed PMC or PTMC modules)
October 10, 2006 Copyright 2006, SBE, Inc. Page 6
HighWire HW400c/2 User Reference Guide Rev 1.0
2.8 Regulatory Agency Certifications
The HW400c/2 complies with the requirements listed below.
2.8.1 Safety
• IEC60950 International product safety pending
• IEC60950 pending
• UL60950 pending
• Certified Body (CB) Report pending
2.8.2 US and Canadian Emissions
• FCC Part 15 Class B pending
• Industry Canada CS-003 pending
2.8.3 European Emissions and Immunity
• EN 50082-1 pending
• EN 300386-2 (supercedes EN55022)
to include EN61000-4-6: 10kHz-80MHz, 80%AM 1kHz
pending
CE Mark approval is included.
2.9 Agency Compliance
The HW400c/2 is designed to comply with the following agency requirements.
• NEBS
• VCC
October 10, 2006 Copyright 2006, SBE, Inc. Page 7
HighWire HW400c/2 User Reference Guide Rev 1.0
2.10 Physical Properties
The Highwire 400c/2 is compliant with the mechanical specifications of PCMIG 2.0.
Table 2 lists the physical dimensions of the HW400c/2 product. Figure 2 shows the
physical profile of the HW400c/2 board.
Table 2. HW400c/2 Physical Dimensions
Length:9.2 inches (233.68 mm)
Width:6.3 inches (160.02 mm)
Maximum component height (front):0.540 inches (13.72 mm)
Maximum component height (back):0.079 inches (2 mm)
Board thickness:0.062 inches (1.57 mm)
Figure 2. The HW400c/2 PTMC Processing Platform
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HighWire HW400c/2 User Reference Guide Rev 1.0
2.10.1 HW400c/2 Front Panel
The HW400c/2 CompactPCI front panel has custom cut outs with the appropriate
thickness to accommodate two PTMC bezels (with EMC gaskets), two RJ-45
connectors, blue Hot Swap LED, green power LED, and status LEDs. Figure 3
below shows an illustration of the front panel.
Figure 3. HW400c/2 Front Panel
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HighWire HW400c/2 User Reference Guide Rev 1.0
2.10.2 Part number and serial number
oards are marked with the manufacturing part number and assembly revision.
All b
This is marked on a label and affixed to the top of the board.
All boards are serialized physically with a bar code serial number label and affixe
e secondary side of the board.
th
.10.3 Bus Keying
2
d to
Keying on the HW400c/2 is used to prevent damage to the card and/or the backplane.
There are two keying systems used on the HW400c/2, CompactPCI and P
2.10.3.1 Compact PC
2.10.3.2 PTMC Site
!
The host PCI bus (CompactPCI) and local PCI bus (PTMC Sites) are independent of one another, and
I
As defined in PICMG 2.10, the HW400c/2 has a Strawberry Red key, RAL # 3018,
installed in J4 signifying the existence of the H.110 Computer Telephony bus on J4.
There is no key installed in J1, signifying universal PCI signaling levels.
The PTMC Sites are capable of 3.3v signaling only. Therefore cards with 5v only IO
signals will be prevented from installation by the presence o
e HW400c/2. The key posts are located at each PTMC site, with the location
th
efined in IEEE 1386.
d
The key posts must not be removed, or damage could result from
incompatible PMC or PTMC card with 5v only IO signals.
may operate at different speeds and bus widths (see Sections 3.2.3 and 3.2.4).
f key posts installed on
installation of an
TMC.
October 10, 2006 Copyright 2006, SBE, Inc. Page 10
HighWire HW400c/2 User Reference Guide Rev 1.0
2.10.4 Power Requirements
The power requirements of the HW400c/2 are defined for two environments:
• CompactPCI VIO of 5.0v (see Table 3)
• CompactPCI VIO set 3.3v (see Table 4).
1. All voltages are required.
2. The CompactPCI VIO has no effect on the local PCI bus VIO (PTMC sites), which is fixed at 3.3v.
Table 3. HW400c/2 power requirements VIO = 5.0V
HW400c/2 alone
PTMC site A capacity
PTMC site B capacity
HW400c/2 with PTMC A&B
3.3V
Current (A)
2.266.1350.05 38.73
4.542.80.92 40.02
4.542.80.92 40.02
11.3411.7351.89 118.78
5.0V
Current (A)
12V
Current (A)
Total
Power (W)
Table 4. HW400c/2 power requirements VIO = 3.3V
HW400c/2 alone
PTMC site A capacity
PTMC site B capacity
HW400c/2 with PTMC A&B
3.3V
Current (A)
5.044.30.05 38.73
4.542.80.92 40.02
4.542.80.92 40.02
14.129.91.89 118.78
5.0V
Current (A)
12V
Current (A)
Total
Power (W)
October 10, 2006 Copyright 2006, SBE, Inc. Page 11
HighWire HW400c/2 User Reference Guide Rev 1.0
2.10.5 Switches
The HW400c/2 contains single switch that is necessary for normal operation. The
switch is an integral part of the lower ejector handle inside the front panel, and is
used along with the blue LED (see Figure 3) and the Linear Systems LTC1644, for
hot swap. The switch is connected to the PC board at J10 near the lower ejector
handle.
For debugging purposes an optional reset/NMI toggle switch and cable is available
(see Section 3.1.3). Please contact SBE Technical Support for details.
2.10.6 Product Configurations
The HW400c/2 can be manufactured with several configuration options. Specific
options include processor type and speed, memory amount, and CompactPCI
connector configuration. See Table 6, Table 16, and Section 3.2.3 for related
information.
Table 5. HW400c/2 Order time options
CPU Speed 1.0 GHz 1.4 Ghz, 1.7Ghz
DDR RAM 256MB 512MB, 1GB
H.110 CT bus Installed Uninstalled (see Section 3.3.3)
CompactPCI bus Installed Uninstalled (See Section 3.2.3)
Options or modifications are available upon request. Please call SBE Sales for option
availability, and/or modification requests.
Build options have significant impact on power consumption.
Standard Configuration Options
(see Section 3.1)
(see Section 3.2.2)
October 10, 2006 Copyright 2006, SBE, Inc. Page 12
HighWire HW400c/2 User Reference Guide Rev 1.0
3 FUNCTIONAL BLOCKS
The HW400c/2 has six major functional blocks – the PowerPC processor, system
controller, CT Bus interface, Ethernet switch, PTMC expansion sites, and the IPMI
controller. The following sections describe these functional blocks in greater detail.
Additional features such as the connector pin outs and JTAG development support
are also described.
3.1 PowerPC Processor
The standard configuration for the HW400c/2 includes the Freescale MPC7447A
PowerPC Processor running at 1000 MHz (1 GHz) with a corresponding system bus
speed of 166 MHz. There are two additional processor variants available for the
board, which utilize the Freescale MPC7448 PowerPC Processor with a 200 MHz
system bus speed.
The operating frequency and power consumption for each processor variant is shown
in Table 6.
Table 6. HW400c/2 Processor Options
Operating
Frequency
Processor Type
MPC7447A
MPC7448
MPC7448
(Maximum)
1.0 GHz
1.4 GHz
1.7 GHz
3.1.1 MPC744X Development/Debug Support
The HW400c/2 provides external access to the MPC744X processor COP port, reset
and interrupt signals at headers J6, Jx6, J7, J8, and J9 (See Figure 2). A console port
is also provided on the front panel of the board though an RJ45 modular connector
(see Figure 4, and Section 3.1.2).
System Bus
Frequency
(Maximum)
166 MHz 8.0 / 11.5 W
200 MHz 8.0 / 15.9 W
200 MHz 21 / 29.8 W
Core Power
Consumption
(Typical/Maximum)
October 10, 2006 Copyright 2006, SBE, Inc. Page 13
HighWire HW400c/2 User Reference Guide Rev 1.0
(-)
3.1.2 Console port
The front panel console port is connected through the MV64462 via a Linear Systems
LTC1386 EIA-562 (low voltage EIA-232) transceiver. The console port is an RJ45
modular connector mounted on the front panel using three wire (Tx, Rx, GND) EIA232 at 9600 baud, 8N1 (8 bits, No parity, 1 stop bit). Figure 4 shows the console port
pin out.
Tx
Rx
1
2
3
4
5
6
7
Shield
CONSOLE
Pin 1
Figure 4. Console port pin out
3.1.3 Pushbutton Reset / Interrupt
An optional external pushbutton reset is provided as a 6-pin header (part of J8, J9, see
Figure 2, Figure 5, and Table 7) on the board that accepts the standard SBE
developer’s debug cable with toggle switch. Contact SBE Technical Support for
additional details on obtaining a developer’s debug cable.
The same toggle switch is also used to generate a non-maskable interrupt (NMI), by
pushing it in the opposite direction. The pushbutton interrupt signal is connected to a
GPIO port of the Marvell Discovery III System Controller, which can be configured
to route it to the MPC744X if desired. See Table 11 for the GPIO port number.
J9J8
RSTOO
NMI
I2C2 I2C2
SDA SCL
Indicates location of Pin 1
This row (even numbered pins)
reserved for factory use
Figure 5. J8, J9 Reset/NMI header
October 10, 2006 Copyright 2006, SBE, Inc. Page 14
HighWire HW400c/2 User Reference Guide Rev 1.0
Table 7 describes the pin out of J8 and J9. Some of the pins listed are for Factory use
only.
Table 7. J8 and J9 pin out
Header Pin Label Usage
J8
1 O N/C. The “o” indicates pin one
2 SCL TWSI IPMB SCL, for Factory use only
3 none N/C. Just below the “J8” header title.
4 SDA TWSI IPMB SDA, for Factory use only
5 NMI Ground. Used in conjunction with J9, 1, holds
microprocessor Non Maskable Interrupt (NMI) active.
When used with optional reset/NMI cable toggles NMI.
6 (-) Ground. Used with TWSI cable, for Factory use only
J9
1 O Non Maskable Interrupt (NMI). The “o” indicates pin
one. Used in conjunction with J8, 5, holds
microprocessor Non Maskable Interrupt (NMI) active.
2 none N/C
3 none Reset to the microprocessor. Used in conjunction with
J9, 5, holds microprocessor in reset. When used with
optional reset/NMI cable toggles reset line.
4 I2C2 Select I2C2, Used with J9-6 to select I2C3 mode. For
Factory use only.
5 RST Ground. In conjunction with J9-3 to hold microprocessor
in reset.
6 I2C2 Ground. Used with J9-4 to select I2C3 mode. For
Factory use only.
Bottom row of J8 and J9 reserved for Factory use only.
Figure 6. J8 and J9 with optional Reset/NMI cable
October 10, 2006 Copyright 2006, SBE, Inc. Page 15
HighWire HW400c/2 User Reference Guide Rev 1.0
Figure 7. Optional Reset/NMI switch
3.1.4 COP/JTAG Port
A 16-pin header (J6, see Figure 2, and Figure 8) and a 6-pin header (JX6) are
provided on the HW400c/2 board for connecting to the processor’s COP (Common
On-chip Processor) port for factory development purpose
e used to access the JTAG chain for the entire board.
b
The COP/JTAG port uses 3.3V signaling.
s. The J6 header can also
3.1.5 Special Pu
Figure 8. COP/JTAG Pinout
rpose Jumper Block
Jumper block J7, located along the top of the board, is used for diagnostic and other
special purposes. Under normal operating circumstances these jumpers will remain
uninstalled. The IGNP jumper is necessary when in standalone test mode (no PCI
bus is present, or no PCI Slot One Master installed). See Figure 9 and Table 8, below.
Pin 1
Figure 9. J7 Special purpose jumper block
October 10, 2006 Copyright 2006, SBE, Inc. Page 16
HighWire HW400c/2 User Reference Guide Rev 1.0
Table functions
.1 Jumper
3.1.5
Pins
1-2 PWR Forces board “late power” to switch “ON” at power-up
3-4 IGNP Forces board to operate as if no Host PCI bus is
5-6 FAC a) Sets “FACT” bit in BSR register for use by so
7-8 LPCI Limits Local PCI bus (PTMC sites) to 100MHz
9-10 IRST Holds IPMI Controller (U92) in reset state. (Required
11-12 IWE Enables writes to the I2C Configuration ROM (U30)
13-14 ZJT Connects only IPMI Controller (U92) to JTAG/COP
15-16 TRST Forces JTAG Reset signal inactive (Required when
Label Usage
8. J7 pin
present
b) Enables writes to Microwire EEPROM lower
addresses
maximum frequency
hen programming IPMI EEPROMs on-board via the
w
System Controller TWSI interface, see Table 7).
header (J6/JX6)
using Altera ByteBlaster)
ftware
3.2 MV64462 Sy
3.2.1 System Bu
3.2.2 Dual Data
stem Controller
The HW400c/2 uses the Marvell Discovery III (MV64462) PowerPC System
ontroller, which acts as the C
evice busses (see Figure 1). This section outlines the devices and functions
d
rfaced to the MV64462.
inte
interface between the processor, memory, PCI and
s
he system bus interface between the Freescale MPC744X processor aT
V64462 system controller is a 64-bit bus, operating at a speed of 166 MHz or 200
M
MHz depending on the pro
cessor system bus frequency (see Table 6).
nd Marvell
Rate (DDR) SDRAM
One 200-pin SODIMM module is used for the DDR SDRAM. The module is located
under one of the PTMC mezzanine cards using a low-profile SODIMM socket.
The HW400c/2 supports DDR SDRAM densities of 256 MB, 512 MB, and 1 GB as
order time options. Memory speeds of up to 200 MHz are supported for MPC7448
rocessors. Thp
e memory speed for the standard MPC7447A (1 GHz) configuration is 166 MHz
th
(see Table 6).
e memory speed is the same as the processor bus speed, and therefore
October 10, 2006 Copyright 2006, SBE, Inc. Page 17
HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.3 Host PCI B
3.2.3.1 Operation
us
The Marvell Discovery III (MV64462) host PCI bus (PCI bus 0) provides an
interface between the process
ites and the CompactPCI host. The MV64462 device acts as a PCI-to-PCI bridge
s
between the two PCI buses.
he HW400c/2 supports a 64-bit-wide bus operating at 33 or 66 MHz. PCI-X
T
operation at 66 MHz is supporte
Without CompactPCI Bus
The HW400c/2 supports the PICMG 2.16 R1.0 specification’s requirement that a
PICMG 2.16 compliant node card must have the ability to operate without the
presence of the CPCI bus. CPCI connectors J1 and J2 are present as they provide
power and geographic addressing information; however pin B6 of J1 is redefined a
signal PCI_PRSNT# in PICMG 2.16. When the PCI bus is prese
is pin is defined as GND. If the PCI bus is not present on the backplane, then it
th
must leave this pin floating (there is a 10K pull-up on the node).
The state of the PCI_PRSNT# signal is sensed at power-up (or hot-swap) and, if
inactive, the backplane PCI signals are ignored, enabling the board to boot up
normally. The primary PCI signals from the MV64462 are tri-stated in this case
the precharge voltage is switched from 1.0V to VIO (3.3V or 5V) to prevent floating
signals. The PCI Status Register (PSR) provides the status o
ection 4.2.10). The software must read this register to determine whether the PCI
S
bus is present or not and configure the board appropriately.
The HW400c/2 can also boot up without the slot 1 card in a CompactPCI chassis. A
jumper enables this feature, regardless of the state of the PCI_PRSNT# pin on
his jumper is labeled IGNP (part of J7, see Section 3.1.5), and when installed, the
T
CI reset and clock signals for MV64462 PCI bus 0 are generated internally.
P
If a Slot 1 card is present and the IGNP jumper is installed, the HW400c/2 will not be
able to communicate with the Slot 1 card.
or and CompactPCI host, as well as between the PTMC
d; however 100/133 MHz operation is not supported.
s
nt on the backplane,
, and
f the PCI bus (see
J1.
3.2.4 Local PCI
October 10, 2006 Copyright 2006, SBE, Inc. Page 18
Bus
The Marvell Discovery III (MV64462) local PCI bus (PCI bus 1) provides an
terface between the processor and the two PTMC sites. The local PCI bus is 32-
in
bits wide and operates in PCI mode at 33-66 MHz, or PCI-X mode at 66-133 MHz.
The PCI-X 133 MHz speed is allowed when only one PTMC module is installed,
it must be in
apable module is installed at Site A, the bus frequency is automatically forced to
c
100 MHz.
stalled at Site B. If two PCI-X capable modules are installed, or a PCI-X
a!
nd
HighWire HW400c/2 User Reference Guide Rev 1.0
If a PCI-X 133 card is installed in Site B, it may be forced to 100 MHz, by installing the LPCI jumper at
(see Section 3.1.5).
J7
Module presence is detected by the state of the BUSMODE1 pin. Interrupts from
either of the two sites are fed through the MV64462 GPIO pins, and can be routed t
either the on-board processor or through the host PCI bus to the CompactPCI host
processor. The local PCI bus is independent of the ho
uses can operate at different speeds and bus widths.
b
st PCI bus, that is, the two
The local PCI Bus I/O voltage is connected to 3.3 volts only. Therefore, PTMC modules with 5-volt only I/O signals cannot be used on the HW400c/2, and are
!
prevented
.10.3).
2
from being installed by a voltage key residing at each site (see Section
3.2.5 Serial EEPROM
o
The HW400c/2 includes a 4 K-bit non-volatile EEPROM for storing small items s
uch
as IP addresses and board serial numbers. This device is the Atmel AT93C66A,
which is organized in a 256 x 16-bit format. The EEPROM is accessed through
CPLD registers, which control a read/write state machine within
ections 4.2.25 to 4.2.28 for details on accessing the EEPROM.
S
the CPLD. See
Table 9 and Table 10 summarize the contents of the EEPROM. The first 16
addresses (0x00-0x0F) are written by SBE when the boards are manufactured, and
must not be modified. Space is reserved in the next 32 addresses (0x10-0x2F) for a
total of 16 IP Addresses, beginning with the board IP address and the Gateway I
ddress. U-boot use the remaining addresses (0x30-0xFF) for boot parameters.
a
P
Boot software must read the MAC address from the serial EEPROM and subsequently assign the value
to the MV64462 Ethernet Por
number 00:A0:D6:12:34:56.
t 0 registers. In Table 9, the MAC address is represented by the sample
October 10, 2006 Copyright 2006, SBE, Inc. Page 19
HighWire HW400c/2 User Reference Guide Rev 1.0
Table 9. Microwire EEPROM Contents, Factory Area
Word
Address
0x00 Payload Length (words) 0x20 Format 0x03
0x01 CRC32 Byte 2 0xCC CRC32 for address 0x00
0x02 CRC32 Byte 4 0xCC CRC32 Byte 3 0xCC
0x03 Subsystem Vendor ID 0x76 Subsystem Vendor ID 0x11
0x04 Subsystem ID 0x01 Subsystem ID 0x0D
0x05 SBE MAC Address
0x06 Board Serial Number
0x07 Board Serial Number
0x08 Reserved 0x01 Reserved 0x43
0x09 Reserved 0x40 Reserved 0xD5
0x0A Reserved 0x00 Reserved 0x00
0x0B Reserved 0x00 Reserved 0x00
0x0C Reserved 0x00 Reserved 0x00
0x0D Reserved 0x00 Reserved 0x00
0x0E Reserved 0x00 Reserved 0x00
0x0F Reserved 0x00 Reserved 0x00
Bits 15-8 (MSB)
Header Byte 2
(BCD) Byte 1
(BCD) Byte 3
Typical
Value
0xA0 SBE MAC Address
0x12 SBE MAC Address
0x56 Board Serial Number
Bits 7-0 (LSB)
and 0x02-0x0F
Header Byte 1
Header Byte 3
(BCD) Byte 2
Typical
Value
0xCC
0x00
0xD6
0x34
Shaded areas indicate addresses reserved for programming by SBE at the time the boards are
manufactured.
October 10, 2006 Copyright 2006, SBE, Inc. Page 20
HighWire HW400c/2 User Reference Guide Rev 1.0
Table 10. Microwire EEPROM Contents, Uboot Area
Word
Address
0x10 Board IP Address byte 1 0xA8 Board IP Address byte 0 0xC0
0x11 Board IP Address byte 3 0x0A Board IP Address byte 2 0x01
0x12 Gateway IP Address byte 1 0xA8 Gateway IP Address byte 0 0xC0
0x13 Gateway IP Address byte 3 0x0A Gateway IP Address byte 2 0x01
0x14 Server IP Address byte 1 0xA8 Server IP Address byte 0 0xC0
0x15 Server IP Address byte 3 0x0A Server IP Address byte 2 0x01
Addresses are typically modified by the user through the U-boot software.
Typical
Value
0xFF
0xFF
0xFF
0xFF
0xFF
0x35
October 10, 2006 Copyright 2006, SBE, Inc. Page 21
HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.6 MV64462 Ethernet Interface
The MV64462 contains an Ethernet MAC, which provides a MAC-to-MAC
connection to port 7 of the on-board Broadcom BMC5388 layer 2 Ethernet switch
(see Table 14). The connection is made via the RGMII ports on each device. The
operating speed of the RGMII port is 125 MHz.
3.2.7 MV64462 Device Interface
The Discovery III Device Interface connects the following functional elements:
• SRAM Device
• Boot PROM
• Disk-on-Chip
• CT Bus Controller
• CPLD
The device bus is a 32-bit interface with a default operating frequency of 100 MHz.
The following sections provide additional detail for each of the functional elements.
3.2.7.1 SRAM Device
The HW400c/2 includes a 512 KB SRAM device with a 32-bit wide data bus
necessary for the processor to boot. The device supports burst reads and writes.
3.2.7.2 Boot PROM
A 4 Mbit (512 KB) Boot PROM device is supported in a PLCC socket (XU4) that is
located underneath PTMC site B. The device allows for easy upgrade of boot and/or
diagnostic code. The socket also accepts most EPROM emulator cables. Burst
reads/writes to the boot ROM are not supported.
3.2.7.3 Disk-on-Chip
A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data
storage. DoC is a high-density flash device manufactured by M-Systems
Incorporated, with a data bus width of 16 bits. The 128 MB device is standard on the
HW400c/2, with the option of populating other devices for OEM configurations.
Burst reads/writes to the DoC are not possible due to the maximum input clock
frequency of the device (33 MHz) being slower than the 100 MHz device bus clock.
October 10, 2006 Copyright 2006, SBE, Inc. Page 22
HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.7.4 CT Bus Controller
The Agere T8110L CT bus controller on the HW400c/2 board is accessed and
programmed via the device bus. It also has a data bus width of 16 bits. Burst
reads/writes are not supported by the T8110L. See Section 3.3 for details about the
CT Bus Controller functions.
3.2.7.5 CPLD
The Complex Programmable Logic Device (CPLD) registers are also accessed via
the device bus, using an 8-bit data bus width. Miscellaneous signals such as resets
and mezzanine card selection logic are monitored and controlled by the CPLD
registers. The CPLD supports burst reads and writes. See Section 4.2 for details
about CPLD register functions.
3.2.8 Watchdog Timer
3.2.9 Reset
The Marvell MV64462 Discovery III system controller contains an internal 32-bit
Watchdog Timer that can be configured as a source of interrupt to either the
MPC744X processor or to the CompactPCI host through the PCI interrupt output.
The IPMI controller can also detect a Watchdog timeout by checking the appropriate
GPIO bit (see Table 22 in Section 3.6).
The following types of reset are available:
• Power–on reset. Resets the entire board during hot-swap or power-up.
• Optional external pushbutton reset. See Section 3.2.9 for details.
• Host PCI reset. This reset is routed through the Early Power CPLD, allowing
the host on the CompactPCI bus to reset all devices on the HW400c/2 board.
• Individual device reset. The PTMC sites, the T8110L, the Ethernet Switch
and PHYs and the Disk on Chip can all be individually reset via the CPLD
register bits (see Section 4.2.16)
• Software reset (warm reset). Initiated by writing to the CPLD’s Warm Reset
Register (WRR, see Section 4.2.18), resets the CPU, System Controller, and
all on board devices. Host PCI reset signal is not affected by warm reset.
October 10, 2006 Copyright 2006, SBE, Inc. Page 23
HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.10 Multi-Purpose Port (MPP) Usage
The MV64462 Discovery III includes a 32-bit Multi-Purpose Port (MPP) that can be
used for a variety of possible functions. The HW400c/2 board uses the MPP for the
serial Console Port signals (front-panel RJ-45), REQ and GNT signals for the local
PCI bus, I2C EEPROM activity indicator (used during boot*), and as a detector for
the various on-board interrupt sources.
Interrupts from the PTMC sites, the T8110L, the Ethernet PHYs, the Disk-on-Chip,
and the optional external pushbutton are connected individually to GPIO ports of the
Discovery III, which can then be configured to route them either to the MPC744X, or
to the host through the PCI interrupt output.
Table 11 lists the MV64462 MPP pin connections on the HW400c/2 board.
Table 11. MV64462 Multi-Purpose Port Assignments
MPP
Pin
MPP0 0x2 S0_TXD Out High Console Port (RJ-45) TXD
MPP1 0x2 S0_RXD In High Console Port (RJ-45) RXD
MPP2 0x1 PCI1_GNTn[0] Out Low GNT to PTMC Site A
MPP3 0x1 PCI1_REQn[0] In Low REQ from PTMC Site A
MPP4 0x1 PCI1_GNTn[1] Out Low GNT to PTMC Site B
MPP5 0x1 PCI1_REQn[1] In Low REQ from PTMC Site B
MPP6 0x0 GPIO6 Out Low Disk-on-Chip Lock
MPP7 0x4 INITACT Out High I2C EEPROM Active*
MPP14 0x0 GPIO14 In Low Pushbutton Interrupt
MPP15 0x0 GPIO15 In Low CPU Temp Sensor TCRIT
MPP16 0x4 WD_NMIn Out Low Watchdog Signal to IPMI
MPP17 0x0 GPIO17 In Low INTA from PTMC site A
MPP18 0x0 GPIO18 In Low INTB from PTMC site A
MPP19 0x0 GPIO19 In Low INTC from PTMC site A
MPP20 0x0 GPIO20 In Low INTD from PTMC site A
MPP21 0x0 GPIO21 In Low INTA from PTMC site B
MPP22 0x0 GPIO22 In Low INTB from PTMC site B
MPP23 0x0 GPIO23 In Low INTC from PTMC site B
MPP24 0x0 GPIO24 In Low INTD from PTMC site B
MPP25 0x0 GPIO25 In High T8110L Clock Error
MPP26 0x0 GPIO26 In High T8110L System Error
MPP27 0x0 GPIO27 In Low PHY A Interrupt
MPP28 0x0 GPIO28 In Low PHY B Interrupt
MPP29 0x0 GPIO29 In Low PHY R Interrupt (RJ-45)
MPP30 0x0 GPIO30 In Low Disk-on-Chip Interrupt
MPP31 0x0 GPIO31 In Low Disk-on-Chip Busy Signal
Multiplex
Number
Pin Function
In/Out of
Disco III
Active
High/Low
Signal Description
* By default, the HW400c/2 uses the I2C EEPROM during boot. The EEPROM
must contain the appropriate register setting to configure MPP7 as the INITACT
output. This signal is then pulled low after the EEPROM loads to initiate the
processor boot
October 10, 2006 Copyright 2006, SBE, Inc. Page 24
HighWire HW400c/2 User Reference Guide Rev 1.0
3.3 Computer Telephony Bus Controller
The HW400c/2 includes the Agere T8110L CT Bus Controller to control TDM bus
switching between the backplane (CompactPCI J4 connector) and the local bus,
which is connected to the JN3 connector on each of the two PTMC sites.
3.3.1 H.110 Interface (T8110L)
The Agere T8110L is a H.110 CT Bus controller that provides a complete interface
between the backplane H.110 CT bus and local PTMC CT bus through a dynamically
controllable switching fabric. The H.110 interface connects to all 32 bi-directional
TDM streams of the backplane H.110 bus via the CPCI J4 connector using the
PICMG 2.5 R1.0 standard mapping. It can access any of the 4096 time slots carried
on the H.110 bus.
The local CT bus, with 32 bi-directional TDM connections, can be programmed for
data rates of 2.048Mb/s, 4.092Mb/s or 8.192Mb/s. The local CT bus of the T8110L
is connected to each of the PTMC sites via the JN3 connectors.
The PTMC configuration 2 (PT2MC) type modules only support 20 CT bus streams, while PTMC
configuration 5 (PT5MC) modules support all 32 CT bus streams.
3.3.2 T8110L Clocking Interface (T8110L)
The T8110L LSC [3:0] output pins are connected to the PTMC Output Clock Drivers
located in the CPLD. The LSC[3:0] pins are programmed as shown in Table 6.
Figure 10 shows the local CT Bus clocking signals and how they are routed.
October 10, 2006 Copyright 2006, SBE, Inc. Page 25
HighWire HW400c/2 User Reference Guide Rev 1.0
Figure 10. Local CT Bus Clocking Block Diagram
Control for the local “A” and “B” bus drivers is provided by bits 4, 5, 6, and 7 in the
Clock Select Register (CSR). Refer to Section 4.2.1 for further details. Figure 11
shows the implementation.
Figure 11. Local CT Bus Clock Generation
October 10, 2006 Copyright 2006, SBE, Inc. Page 26
HighWire HW400c/2 User Reference Guide Rev 1.0
The T8110L can be programmed such that its local frame reference (LREF [3:2])
puts are used to generate all of the TDM bus clocks and syncs. The T8110L Local
in
Clock Reference Inputs have been assigned to the PTMC JN3 H.110 clock pins as
shown in Table 13.
ble 13. LREF [3:2] Assignments
Ta
LREF input Assigned to Clock
LREF2 PT_NETREF1
LREF3 PT_NETREF2
3.3.3 Operation in Non-H.110 Backplane
The defau
lt HW400c/2 configuration has the H.110 interface installed. However, in
the event that the HW400c
have an H.110 bus or the H.110 interface is not installed, the CT_EN pin on J4 (pin
) The state of the CredD
C23 is not grounded. T_EN pin is sto in bit 7 of the CPL
BSR r (see 4.2.2). If H.110 is not present, the H.110
egister for access by software
interfaabled.
ce should not be en
Even ble on thectPCI bal CT
if the H.110 bus is not availa Compaackplane, the loc
Bus connections are still valid and therefore PTMC Site A and PTMC Site B can
commis local to 400c/2
unicate via the CT Bus that the HW board.
3.4 Layer 2 Ethernet Switch
The Broadcom BCM5388 Layer 2 Ethernet sw
the HW400c/2 board. The BCM5388 has four
MAC/PHYs, and four additional Gigabit MACs with external RGMII connections.
Three of the additional MACs are connected to Broadcom BCM5461S external
PHYs, and one is connected directly to the MV64462 MAC port as shown in Table
14.
Table 14. Layer 2 Switch Port Assig
Switch P
ort Device or Port PHY Address Connection Type
7 MV64462 System Controller N/A MAC-to-MAC RGMII
6 Front Panel RJ-45 00110 1 External PHY
2 PT5MC Slot A, Link Port A N/A 1 Integral PHY
4 Y PT5MC Slot A, Link Port B 00100 1 External PH
3 PT5MC Slot B, Link Port A N/A 1 Integral PHY
5 PT5MC Slot B, Link Port B 00101 1 External PHY
0 PSB Link Port A N/A 1 Integral PHY
1 PSB Link Port B N/A 1 Integral PHY
/2 board is used in a PICMG 2.16 chassis that does not
itch connects to the various devices on
Gigabit Ethernet ports with integral
nments
October 10, 2006 Copyright 2006, SBE, Inc. Page 27
HighWire HW400c/2 User Reference Guide Rev 1.0
3.4.1 Switch Re
3.4.2 MV64462 S s
gisters Initialization and Monitoring
The switch is initialized and its registers polled by utilizing its SPI bus interface.
This interface is connected through the CPLD. For a description of how to access the
SPI interface, please refer to Section 4.4.
y tem Controller Ethernet Interface
The Marvell MV64462 System Controller on
BCM5388 Ethernet switch. The connection speed must be set to 1
MAC-to-MAC connection with the clock sou
transmitter signals from the switch are connected to
stem controller, and vice-versa for a direct MAC-to-MAC connection.
sy
3.4.3 Front Panel (RJ-45) Ethernet Interface
he HW400c/2 boardlded RJ-45 (with integrated transformer
T includes a fully shie
nd twos) located at the front panel that provides an Ethernet LAN
a
in
M
L
The Link
green LED
terface. The port is auto-negotiating and auto-sensing, and operates at 10/100/1000
bps. The left LED (looking at the port) indicates Link/Activity/Speed and the right
ED indicates collision detection (See Figure 12).
/Activity/Speed LED indication is as follows:
the HW400c/2 can be accessed via the
000 Mbps and is a
rced from the Ethernet switch. The
the receiver signals on the
solid green when the network link is up;
•
• blinking at 3
• blinking at 6 Hz for 100 Mb/s Tx or Rx;
• and blinking at 12 Hz for 1000 Mb/s Tx or Rx.
Link/activit speed Collision y/
Figure 12. Front panel Ethernet RJ-45 LEDs
Hz for 10 Mb/s Tx or Rx;
Ethernet
October 10, 2006 Copyright 2006, SBE, Inc. Page 28
HighWire HW400c/2 User Reference Guide Rev 1.0
3ernet Ports .4.4 PT5MC Eth
Each of the two PT5MC sites on the HW400c/2 have two 10/100/1000 Mbps ports
connected to the Ethernet switch. The signals conform to PICMG ECN 2.15-1.0001, using the first 24 pins of the respective JN4 connectors.
The JN4 Ethernet connections are switched to the Com
FET switch specially designed for signals such as Gigabit Ethernet. The PTID bits
ontrol the FET, when a PT5MC module is installed in either mezzanine card site.
c
Should a non-PT5MC module be installed in one of the sites, the JN4 signals for th
site are routed to the CompactPCI J5 connector as user I/O according to PICMG 2.3
R1.0.
N4 pins 5, 6, 11, 12, 17, 18, 23 and 24 are switched to ground through discrete FETs
!
!
J
t the JN4 connector when a PT5MC module is installed. This has the effect of
a
grounding the respective connections at the
aution must be exercised not to damage circuitry on an installed RTM.
c
PT5MC cards with network connections through Pn4, must be transformer coupled o
the link to the layer 2 switch will not be established.
The HW400c/2 includes eight on-board LED
Ethernet ports. The LEDs are labeled L0-L8
connector J5.
The BCM5388 has a serial LED interface, fro
e the CPLD, which contains a state
be xtracted. The serial LED signal is routed to
ac
hine that decodes the LED states for each port. The eight status LEDs on the top m
edge of the HW400c/2 board can be configured to show the status for all eight
Ethernet ports. Each status LED gives the status for its corresponding port in the
Link/Activity/Speed format. The CPLD LED registers control the selection of
Ethernet status, boot status, or general debug modes for the eight LEDs.
The serial LED interface signals are also routed to the RTM through CompactPCI
connector J3.
LED Interface section in the
LEDMODE settings on the BCM5388 are hardwired to “101” (see Serial
BCM5388 datasheet).
s for monitoring the status of the various
and are located near CompactPCI
m which the status of all eight ports can
October 10, 2006 Copyright 2006, SBE, Inc. Page 30
HighWire HW400c/2 User Reference Guide Rev 1.0
The Link/Activity/Speed LED indication is as follows:
• solid gree
• blinking at 3 Hz for 10 Mb/s Tx or Rx;
• blinking at 6 Hz for 100 Mb/s Tx or Rx;
• blinking at 12 Hz f
An optional front panel 2-high LED is provided as a status indicator for the Ethernet
ports. The optional LEDs a
not present. The left LED indicates Link/Activity/Speed and the right LED indicates
ollision detection for the selected port. A port is selected by setting the appropriate
C
CPLD bit. The default selection (when present) is the Marvell MV64462 System
Controller MAC.
See Section 4.2 for details
n when the network link is up
or 1000 Mb/s Tx or Rx.
re shown as LEDs C and D in Figure 3, and by default are
on setting the LED modes.
October 10, 2006 Copyright 2006, SBE, Inc. Page 31
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5 Mezzanine Card Sites
The HW400c/2 board supports I/O expansion using either one or two industrystandard PTMC and/or PMC modules. This section provides technical details for
these expansion sites.
3.5.1 PT5MC Type Mezzanine Cards
!
The PT5Mn to the local PCI bus (32-bit,
33-133 MHz PCI or PCI-X), the local 32 TDM stream H.110 bus, two Gigabit
hernet poser I/O connecteCI J5 backplane
Et
nnector.
co
PT5MC cards with network connections
e link to the h will not hed.
thlayer 2 switcbe establis
C mezzanine card support includes connectio
rts, and 31 pins of Ud to the CompactP
through Pn4, must be transformer coupled or
3.5.2 PTezzanine Cards
2MC Type M
The PT2MC mezzanine card support includes connection to the local PCI bus (32-bi
33-133 MHz PCI or PCI-X), the local 20 TDM stream H.110 bus, and 55 pi
ser I/O connected to the CompactPCI J5 backplane connector. RMII signals are not
U
supported, therefore these lines cannot be used by the PT2MC cards.
3.5.3 PMC Type
Mezzanine Cards
he PMC mezzanine card support includes connection to the local PCI bus (32-bit,
T
33-133 MHz PCI or PCI-X), and 55he CompactPCI
J5 backp
lane connector.
cards have as user defined I/Oowever, on th00c/2, these lines
PMC
igned only to the CT bus and RGMII bus, so when a PMC card is installed the signals on Jn3 are
are ass
tated (see Tabl
tri-se 17).
specified Jn3 or 64 bit PCI. He HW4
t,
ns of
pins of User I/O connected to t
October 10, 2006 Copyright 2006, SBE, Inc. Page 32
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.4 Mezzanine Card Power
Each of the two mezzanine card sites on the HW400c/2 is allotted a portion of the
total power budget for the board. For the standard version, the mezzanine power
budget is 16.2 Watts for each slot, while the optional high-power version allows 26.4
atts for each slot. The power budget is divided between the 3.3V, 5V, and 12V
W
po
wer rails as shown in Table 16.
16. Mezzanin Card Power Bu
Tablee dget
ower (pe
HW400c/2
Version
zzanine C rd
Mea
Total Power
(per site
)
3.3V power
(Per slot)
Pr site)
5V po
(Per slot)
wer
12V power
(Per slot)
Standard
without J4
Standard
wi
th J4
Optional High
Powe4
r with J
29.4 Wat1a12 WWat
26.4 Wat1 W7.5 W2.4 Wat
ts 5 W tts atts 2.4 ts
ts 6.5atts atts ts
The starsion wier supplied from tpactPCI J4
connectds the higt power rat for the mezzanine card slots, because t hat
ndard veth additional powhe Com
or yielhesing
version has a lower power processor th thnal highversion.
3.5.5 C Connr Summy
PTMC/PMectoar
Table 1arizes thezzanine card connections for each supported type. Both
sitand B suppe saf cctor pi
Section 3.5.7, an.5.8
7 summe m
es A ort thme array oonnections. Connen outs are shown in
s 3.5.6,d 3
ble 17. PTM /PMC Connector Summary
TaC
Mezzanine
Type
Card
N1/JN2 NN4
JJ 3 J
10 Watts 16.2 Watts 5 Watts 1.2 Watts
ane optio-power
PMC
PT2MC
PT5MC
PCI or
PCI-X
PCI or
PCI-X
PCI or
PCI-X
Not Used (t) s User I/Ori-stated55 Pin
Local CT Bu
(20-bit)
Local CT Bus
(32-bit)
s
55 Pins User I/O
2 LAN Ports
31 Pins User I/O
October 10, 2006 Copyright 2006, SBE, Inc. Page 33
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.6 PTMC Jn1 and Jn2 PCI Connectors
Communication using the local PCI bus is done across two PTMC/PMC connectors,
JN1 and JN2. Table 18 shows the 32-bit PCI connector pin assignment for JN1 an
JN2 on the HW400c/2 as defined by the PMC specification
Table 18. PTMC Jn1 and Jn2 Connector Pin Assignments
d
IEEE P1386.1.
Pn1 32-Bit PCI Pn2 32-Bit PCI
Pin
Signal Name Signal Name
#
-
*
Pin
#
-
+
-
*
+
+
+
-
*
Pin
Signal Name Signal Name
#
+
+
+
+
Pin
#
-
*
-
*
-
*
+
+
-
+
+
+
-
-
+
+
-
-
-
-
+
-
October 10, 2006 Copyright 2006, SBE, Inc. Page 34
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.7 PTMC Jn3 CT Bus Connector
Table 19 shows the PTMC Pn3 CT Bus connector pin assignment for the HW400c/2
for both Configuration #2 (PT2MC) and Configuration #5 (PT5MC). The signal
definitions for Pn3 are per the PICMG 2.15 specification.
For PT2MC cards, the PT2MC MII signals are tri-stated (Hi Z), as they are hard wired to the CTbus for
PT5MC use.
PTMC Serial Port signals (STX and SRX) are not connected on the HW400c/2.
October 10, 2006 Copyright 2006, SBE, Inc. Page 35
HighWire HW400c/2 User Reference Guide Rev 1.0
.5.8 PTMC Jn4 LAN/User I/O Connector
3
Table 20 (Site A) and Table 21 (Site B) show the PTMC Pn4 LAN and/or User I/O
connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC User
I/O only) and C
3.5.8.1M4
LPak Port A) and ernet Sw2 an
MC netk connectio thrmustormerupled or
PT C Site A Jn
s tabe coections from TM Jn4, tpact PCI
Thile shows thnn PC Site Ao the Com
nector PMC, the sigls fothernet pink Ports and B.
conor J5 and, fT5nar the Eorts, L A
(LinLPb (Link Port B) for PTMC Site A go to the Ethitch ports d 4
ectiv 14.
respely. See Table
PT5 cards withwornsough Pn4, be transf co
linkestablished.
!
the to the layer 2 switch will not be
onfiguration #5 (PT5MC LAN and
User I/O).
October 10, 2006 Copyright 2006, SBE, Inc. Page 36
HighWire HW400c/2 User Reference Guide Rev 1.0
Tabl
e 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment
Pn4 PT2MC Pn4 PT5MC
Pin
#
Signal
Name Signal Name
Pin Pin Pin
# #
Signal Name Signal Name
+
-
#
+
-
+
-
+
-
+
-
+
-
+
-
+
-
October 10, 2006 Copyright 2006, SBE, Inc. Page 37
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.8.2 PTMC Site B Pn4
This table shows the connections from PTMC Site B Jn4 to the Compact PCI
onnector J5 and, for PT5MC, the signals for the Ethernet ports, Link Ports A and B.
c
LPa (Link Port A) and LPb (Link Port B) for PTMC Site A go to the Ethernet Switch ports 3 and 5
espectively. See Tar
ble 14.
ed or
!
PT5MC cards with network connections through Pn4, must be transformer coupl
the link to the layer 2 switch will not be established.
Table 21. PTMC Site B Configuration #2/#5 Pn4 Connector Pin Assignment
Pn4 PT2MC Pn4 PT5MC
Pin
#
Signal
Name Signal Name
Pin Pin
# #
Signal Name Signal Name
+
-
+
-
Pin
#
+
-
+
-
+
-
+
-
+
-
+
-
October 10, 2006 Copyright 2006, SBE, Inc. Page 38
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.9 PTMC Site Voltage Keying
Voltage key pon accordance with IEEE 1386. See
ection 2.10.3.
S
sts are installed at each PTMC site i
he HW400c/2 local PCI bus I/O voltage is 3.3 volts only. Therefore, PTMC and
!
T
MC modules with 5 volt only I/O signals cannot be used on the HW400c/2
P
board, and residing at each site.
are prevented from being installed by a key post
3.6 IPMI System Management
The HW400c/2 board inclu IPMm
Mans (SMB) d bMI
infornly accessughsed to
mation is o
monort the heahe H
des anI controller that interfaces to the Syste
as define
ible thro
y the PICMG 2.9 specification. T
he IPagement Bu
u an IPMI Shelf Manager, and is
W400c/2. itor and replth of t
ay nont in fact, not even have power.
An IPMI Shelf manager mt be prese the system, and IPMI may, in
either case, the IPMI circuitry on board is for monitoring purposes only and, if disabled or not used,
In
as no affect the normal operation of the HW400c/2.
h
3.6.1 IPMI Controller
The IPMI controller on the HW400c/2 is the QLogic Zircon PM with board-specific
firmware. The Zircon PM complies with PICMG hot-swap requirements.
The Zircon PM communicates with the System Management device (residing o
slot 0 or other card) through its I
2
C Port 0, connected through the CompactPC
connector. It also connects to the Geographical Address bits from the CompactPCI
J2 or J4 connector for reading the physical slot address. Figure 13 shows the major
functions of the Zircon PM controller. Table 22 lists the GPIO port functions.
n the
I J1
October 10, 2006 Copyright 2006, SBE, Inc. Page 39
HighWire HW400c/2 User Reference Guide Rev 1.0
Figure 13ram
. IPMI Block Diag
Table 22. GPIO Port Assignments for IPMI
GPIO Port I/O Description
GPIO_00 Input /PWRON monitor (active low)
GPIO_01 Input HEALTHY monitor (active high)
GPIO_07 Output Blue LED control (low = on, high = off)
Ejector Latch monitor, L_STAT
(low = closed, high = open)
3.6.2 Temperatu
re and Voltage Monitor
IPMI functions implemented on the HW400c/2 include board temperature sensors
TS0 and TS1 connected to I
oltage), 2.5V, 3.3V, 5V and other supply voltages are connected to A/D input ports
v
2
rt 1 on the Zircon PM. The 1.1V (MPC744X core
C Po
on the Zircon PM through precision voltage-divider networks. These connections
(see Table 23 and Table 24) allow remote monitoring of the temperatures and
voltages on the HW400c/2 by a system management device (shelf manager).
October 10, 2006 Copyright 2006, SBE, Inc. Page 40
HighWire HW400c/2 User Reference Guide Rev 1.0
Table 23. Voltage Monitor A/D Port Assignments for IPMI
Supply Voltage Monitor A/D Port
5-Volt A2D1
3.3-Volt A2D2
1.1-Volt (CPU core) A2D3
1.5-Volt (System controller core) A2D4
2.5-Volt (SDRAM) A2D5
Table 24. HW400c/2 Temperature Sensor Locations
2
Device
Location I
C Port 1 Address
TS0 (U84)
TS1 (U83) CPU Internal Temperature 1
3.6.3 Hot Swap
Ejector Latch Detection
he IPMI controller has the capability to read the state of the hot swap ejector switch,
T
otherwise known as the L_STAT signal. This signal is connected to a GPIO pin on
the Zircon PM (see Table 22). L_STAT = 0 indicates the ejector latch is closed,
L_STAT = 1 indicates it is open, and that the board is about to be removed
3.6.4 Blue (Hot Swap) LED Control
The IPMI controller has the capability to turn on the Blue Front Panel LED. A GPIO
pin on the Zircon PM is connected through the CPLD to the LED (see Table 22).
3.6.5 Boot Status Monitor
MV64462 System
Controller
0
There are four (4) register bits in the CPLD reserved for indicating the boot status
le TtedIO port as
vel from the processor.hese bits are connec
shown in Tabpower-up default var
valur SBE us
es are reserved foe.
to the Zircon PM GP
lue of the
se bits is “0000.” All othele 22. The
October 10, 2006 Copyright 2006, SBE, Inc. Page 41
HighWire HW400c/2 User Reference Guide Rev 1.0
3.6.6 Board Reset via IPMI
The IPMI controller has the capability to issue a board reset. A GPIO port on the
Zircon PM (see Ta
set signal from the Host CompactPCI bus. A standard IPMI command is issued to
re
ble 22) is connected to the CPLD and OR’ed with the /P_RST
initiate the board reset. IPMI commands are issued through an IPMI Shelf Manager
3.6.7 IPMI System Power Supply
The Vsm supply pin on the CompactPCI J1 connector delivers 5V to the
IPMI
circuit. The PICMG 2.9 specification sets the maximum current drawn from the Vsm
pin at 100mA. The
0mA maximum continuous current. However, due to power-up inrush or a short
6
cuit, the current could exceed 100mA. Therefore, a current-limiting switch is
cir
Zircon PM, together with all its supporting devices, draws about
connected at the Vsm pin.
3.6.8 IPMI Firmw
are EEPROMs
here are two Atmel AT24C512 (64 KB) EEPROMs connected to I2C Port 2 on the
T
Zircon PM. The Ehe runtime firmware. The
EEPROM at U87 i of information related to Field
EPROM at U90 is for storage of t
s for boot code, as well as storage
Replaceable Units (FRU), such as serial number. These assignments are shown in
Table 25.
The EEPROMs can be pre-programmed (default), or thgrammed onboard via the 64462 Two-Wire
MVSerial Interface (TWSI), See Table 7.
ey can be pro
The IPMI EEPROMs pre-programmed at the factory should always be used.
Programming on board is usually unnecessary, and is recommended only for expert
!
users, as misconfiguration could result in unpredictable behavior.
When programming the EEPROMs on-board, the Zircon PM must be held in the reset state by installing
the IRST jumper on the J7 header (see Table 8). Table 25shows the I
2
C addresses of each EEPROM.
Table 25. Firmware EEPROM Addresses
EEPROM Function EEPROM Type I
Boot/FRU (U87) AT24C512 0
Runtime (U90) AT24C512 1
2
C Port 2 Address
October 10, 2006 Copyright 2006, SBE, Inc. Page 42
HighWire HW400c/2 User Reference Guide Rev 1.0
3.6.9 Zircon PM
3.6.10 IMPI Get
Reset
At power
within tolerance.
-up, the Zircon PM is held in reset state until the 3.3V supply voltage is
Device ID
The response to the IPMI command “GetDeviceID” from the Shelf Manager is of the
standard format.
GetDeviceID.” Unique Product ID numbers (byte offsets 11 and 12) are assigned as
shown in Table 26
he three least significant bits of the Product ID numbers for the HW400c/2 board
T
are always “111” to maintain continuity with the earlier HW400 Product ID
assignm
(ETR) in the CPLD register bank. SeeSection 4.2.11 for details.
ent scheme. The LSB value is also reflected in the Extended Type Register
HW400c/2 Pro
See Appendix A for the complete response format to
Table 26. Product ID number
duct Features
(see Table 5)
Standard Version 0x00, 0x07
Product ID number
(MSB, LSB)
October 10, 2006 Copyright 2006, SBE, Inc. Page 43
HighWire HW400c/2 User Reference Guide Rev 1.0
3.7 Hot Swap Support
The HW400c/2 complies with the PICMG 2.1 specification for full hot swap in
CompactPCI systems as defined by the PICMG 2.1 R2.0 specification. Hot swap
functions, such as power FET control, are provided by a Linear Technologies
LTC1664 Hot Swap Controller.
3.7.1 Hot Swap o
n J1 and J2
All signals to and from the CompactPCI backplane connectors J1 and J2 are
precharged to a voltage of 1.0V. This voltage is derived from the 3.3V early power
s
ource.
3.7.2 Hot Swap on J3
The Ethernet PSB sigs
operation.
There are power pins assi
Section 3.4.5.1). The
the Hot Swap controller.
3.7.3 Hot Swap on J4
Signals to and from th Jge of
0.7V. This voltage isr
nal on J3 do not require a precharge voltage for hot swap
gned to palces that would normally be User I/O on J3 (see
se pins are part of “late power” and are switched on and off by
e recharged to a volta
4 H.110 CT Bus connector are p
de ived from the 3.3V early power source.
3.7.4 Hot Swap on J5
The J5 rear I/O signals arswap
considerations must b
the J5 rear I/O connector
October 10, 2006 Copyright 2006, SBE, Inc. Page 44
e not bussed on the backplane. Any special hot
e handled by the PTMC modules and/or RTM making use of
.
HighWire HW400c/2 User Reference Guide Rev 1.0
3.7.5 Hot Swap Sequence
The hot swap
W400c/2 board, and the host system board that is capable of basic, full, or high-
H
sequence is a coordination between the operator, the hardware on the
availability hot swap. Table 27 outlays the Hot Swap insertion and extraction
sequences.
Table 27. Overview of
Sequence
INSERTION he board is thee
EXTRACTION is extracted from the ensure, the fo
Type Sequence Process
For a complete description of all hot swap functions, see the PICMG 2.1 R2.0 specification.
Hot Swap Insertion/Extraction Sequences
When t inserted into enclosure, th following
occurs:
1. Hardware Trns on the bluD.
2. The L_S signal is forcis
sensed
3. The PC
signal to
The hos
d instructI bridge blue L
e off stateblue LED assur s the operato
5. Th
the board is functio
When the board
occurs:
1. The bottom C flippe
the extraction sequence. The ejectch forces the
L_STnal to a
2. The Pge sensesnge in L_d
causes ENUM# to toggle, informing the host system
board that the HW400c/2 board is about to be extracted.
3. The operator then waits for the blue LED to turn on
before attempting to fully eject the HW400c/2 board.
4. The host system halts all applications associated with the
HW400c/2 board that is about to be extracted.
5. The host system then instructs the PCI bridge to turn on
the blue LED.
6. After the blue LED turns on, the operator can continue
with the extraction of the board.
tue LE
ATed to a high state that
by th
e PCI bridge.
I brid host via the ENUM#
indat a boarted.
icate thrd has been inse
t syard initia0c/2
s the PC
of the
clollowing
ompactPCI ejector isd down to start
AT sighigh state.
CI brid the chaSTAT an
s thege inform system
li04. stem bozes the HW4
to turn ff the
nal.
o
e
tor swi
board
Ean
r that
D.
October 10, 2006 Copyright 2006, SBE, Inc. Page 45
HighWire HW400c/2 User Reference Guide Rev 1.0
4 PROGRAMMING INFORMATION
The HW400c/2 memory map and progra
is section.
th
mmable register information is provided in
.1 HW400c/2 M
4emory Map
Table 28 shows the m2 board.
emory map for the HW400c/
Table 28. HW400c/2 Memory Ma
p
Address
Start (Hex)
0 F F 256MB Mem0/Mem16 MB 0FFFFF SDRAM25256 MB
0 F FMem0/Mem12 MB B 1FFFFF SDRAM 512MB51512 M
0 F F0/Mem1 GB 3FFFFF SDRAM 1GB Mem11 GB
0 F FMem0/Mem1 GB 7FFFFF SDRAM 2GB22 GB
October 10, 2006 Copyright 2006, SBE, Inc. Page 47
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.1 Clock Select Register (CSR)
The Clock Select Register (CSR) is a Read/Write register. This register selects
whether or not the H.110 Controller (T8110L) drives the H.110 and local CT bus
sync and clock. The register bit definitions are shown in Table 30.
n be generated by either the HW400c/2 board or from
The backplane H.110 Bus “A”
the H.110 backplan
ogramming of the H.110 B).
Alternatical CT us “A” and “B” clocks
_C8A-SRC and L_S8110L LSC[3:0] pins should be programmed properly prior
LC8B- RC bits. The T
enabling the clock onto th local CT bus. See Section 3.3.2 for clock routing details. L_N1-SRC and
toe
L_N2-SRETRE 1 and NETREF2 onto the local
_N2-SRC =LEF2 (PT_NETREF2) not driven by T8110L
L 0 ocal CT Bus NETR
s NETREF2
_N1-SRC =LEF1 (PT_NETREF1) not driven by T8110L
L 0 ocal CT Bus NETR
_C8A-SRC = 0 Local CT Bus “A” clocks (C8A and FRAMEA) not driven by
L
=
L_C8B-SRC = 0 Local CT Bus “B” clocks (C8B and FRAMEB) not driven by
= 1 Local CT Bus “B” clocks (C8B and FRAMEB) are driven by
_C8A-SRC = 0 H.110 “A” clocks (C8A and FRAMEA) not driven by T8110L
H
iven by T8110L
H_C8B-SRC = 0 H.110 “B” clocks (C8B and FRAMEB) not driven by T8110L
H.11ocks (C8B and FRAMEB) are driven by T8
L_C8
A-
S
RC
ereand H_C8B-SRC settings must match the
vely, the lo B can be enabled onto the local CT bus via the
C enable NF CT bus.
L_C
8B-
SR
C
and “B” clocks ca
fore, the H_C8A-S. TheRC
us Controller (T8110Lpr
H_CH_C
SRC
8A-
8B-
SRC
ReseRrved served
e
= 1 Local CT Bu(PT_NETREF2) driven by T8110L
= 1 Local CT Bus NETREF1 (PT_NETREF1) driven by T8110L
T8110L
1 Local CT Bus “A” clocks (C8A and FRAMEA) are driven by
T8110L
T8110L
T8110L
= 1 H.110 “A” clocks (C8A and FRAMEA) are dr
= 1 0 “B” cl110L
October 10, 2006 Copyright 2006, SBE, Inc. Page 48
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.2 Board Status Register (BSR)
The Board Status Register (BSR) is a Read/Write register. This register reflects the
presence of the CT bus (H.110, see Section 3.3.3), the state of the FACT (Factory)
mper in J7 (see Figure 9), and can control and report the state of two of the status
D
= 001 Disk-on-Chip Size is 128 MB (default)
= 010
= 011
= 100 Disk-on-Chip Size is 1 GB
= 101 Disk-on-Chip Size is 2 GB
= 110 Disk-on-Chip Size is 4 GB
= 111 Disk-on-Chip Size is 8 GB
Disk-on-Chip Size is 256 MB
Disk-on-Chip Size is 512 MB
4.2.5 Geographi
Tgd08
Bit 7 Bit 6 Bit 0
Reserved RedGA2 GA1 GA0 ReservedserveGA4 GA3
c Addressing Register (GAR)
he Geographic Addressing Register (GAR) is a Read Only register. This register
T
shpactPCI
ows the value of the Geographic Address Bits as read from the Com
backplane connectors J2 and/or J4.
Geical Asing Bine aal locslot) iompa
ographddresits def physication (n the CctPCI
b. Ts o4 sidee r bo
ackplanehe settingf J2 and Jhould be ntical. Theason forth
connectors mirroring the bitthat in sonfigurns (e.g. lane
r a non H.110 backplane) one or the other connector may not be present. For a
o
definitione Geohic Address Bits, see PIC
of thgrapMG 2.0 and PICMG 2.5.
able 34. Geo raphic A dressing Register (CSR) Offset Address 0x
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
GA[4:0] = Geographic Address Bits as read from CompactPCI J2
s is ome catioa non-PCI backp
onnectors and/or J4 (backplane) c
October 10, 2006 Copyright 2006, SBE, Inc. Page 50
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.6 PTMC Reset Register (PRR)
PTMC Reset Register (PRR) is a Read/Write register that asserts and de-asserts reset
to the individual PTMC sites. The Reset pulse applied to the PTMC modules must
conform to the PCI standard, that is, it must be at least 10 PCI clock cycles long.
he PTMC Control Register (PCR) is a Read/Write register. The interoperability of
T
ach PTMC mezzanine card can be detected by reading this register. After reading
e
each card’s PTID bits, the processor can enable the card by setting the site’s PTEN
bit to “1”. No processor inter
are the codes for PT2MC and PT5MC, respectively. When either of these codes is
detected by the CPLD, the PTEN bit for the site is set to “1” automatically, and th
card in that site is enabled.
Table 36. PTMC
Control Register (PCR) Offset Address 0x0A
P
TENB = 0 PTMC Site B Disabled
ite
TIDB[2:0] = 000 Site B is 32-bit PMC type, or is not present
P
= 010 Site B is PT2MC type
= 101 Site B is PT5MC type
= 111 Site B is 64-bit PMC t
TENA
P= 0 PTMC Site A Disabled
= 1 PTM
TIDB[2:0] = 000 Site A is 32-bit PMC type, or is not present
P
= 101 Site A is PT5MC type
= 111 Site A is 64-bit PMC type, or PT7MC type
= 010 Site A is PT2MC type
vention is required for PTIDx[2:0] = 010 or 101, which
PTMC S= 1 B Enabled
ype, or PT7MC type
C Site A Enabled
e
October 10, 2006 Copyright 2006, SBE, Inc. Page 51
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.8 Board Option Register (BOR)
The Board Option Register (BOR) is a Read Only register. This register indicates the
configuration and product type. Bit 5, bit 2, bit 1 and bit 0 are always “1”
B= 0 PTMC Site A PCI Incapable
= 1 PTMC Site A PCI Capable
= 0 PTMC Site B PCI Incapable
1 TMC Site B PCI Capable
4.2.9 General Purpose Register (GPR)
for the
The General Purpose Registe
indicate boot status informat
r (GPR) is a Read/Write register that can be used to
ion to the IPMI controller. The HW400c/2 boot status
can also be indicated by the on board surface-mount LEDs during the boot process
(LEDB[1:0] = 00).
Table 38. General Purpose Register (GPR) Offset Address 0x0E
= 0011 oot status level = 3
= 0100 oot status level = 4
…. .
= 0010 Boot status level = 2
= 1111 Boot status level = 15
Btus l (defau
B
B
…
October 10, 2006 Copyright 2006, SBE, Inc. Page 52
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.10 PCI Status Register (PSR)
The PCI Status Register (PSR) is a Read-Only register and indicates the status of
host and local PCI buses. The bits of this register are defined as follo
ws.
the
Table 39. PCI Status Register (PSR) Offset Address 0x0F
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R RR eservedeservedeservedLPCI2 LPCI1 LPCI0 eservedNOPCI
LPCI = 0 Local PCI Bus running in PCI mode
=L
PCI[1:0] = 00 Local PCI Bus running at 33 MHz
L
= 11 Local PCI B
NOPCI = 0 Host PCI Bus is present (cPCI backplane has PCI)
= 1 No Host PCI bus on cPCI backplane
1 ocal PCI Bus running in PCI-X mode
= 01 Local PCI Bus running at 66 MHz
= 10 Local PCI Bus running at 100 MHz
us running at 133 MHz
4.2.11 Extended
Bit 7 Bit 6
ETR7 ETR6 ETR5 ETR4 ETR3 1 1 1
Type Register (ETR)
he Extended Type Register (ETR) is a Read-Only register that indicates the type of
T
board. It is only used in the case when bits 0-2 in the Board Option Regi
is set to “111”. The ETR[2:0] bits are permanently set to “111”, while ETR[7:3]
represents the board type.
Table 40. Extended Type Register (ETR) Offset Address 0x10
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ETR[7:3] = 00000 HW400c/2 Standard Version
= 00001 Reserved for future versions
= 00010 Reserved for future versions
ster (BOR)
October 10, 2006 Copyright 2006, SBE, Inc. Page 53
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.12 Hardware Revision Register (HRR)
The Hardware Revision Register (HRR) is a Read-Only register. It contains the
current major and minor (optional) hardware revision for the board.
CPLL[5:0] = 0x0B Default setting for HW400c/2 Standard Version
(CPU core clock is 1.0 GHz when system bus clock is
. Reading this register (along with PLLB) can help so
ncy. Ple
cifications d
es. a
166 MHz)
October 10, 2006 Copyright 2006, SBE, Inc. Page 54
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.14 PLL Configuration Register B (PLLB)
The PLL Configuration Register B (PLLB) is a Read-Only register. It contains the
settings for the System bus and Device bus (external) PLLs. Reading this regis
long with PLLA) can help software determine the CPU operating frequency, as
(a
well a
s the Device bus operating frequency.
ter
Table 43. PLL Configuration Register B (PLLB) Addr3
SPLL[1:0] = 00 is 100 MHz
= 01System bus clock
= 10 System bus clock is 166 MHz (Default for HW400
= 11 System bus clock is 200 MHz
PLL[1:0]
D= 00
= 01
= 10
= 11
System bus clock
is 133 MHz
standard version)
Device bus clock is 100 MHz
Device bus clock is 133 MHz (Default for HW
standard version)
Reserved
Reserved
c/2
400c/2
October 10, 2006 Copyright 2006, SBE, Inc. Page 55
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.15 LED Register B (LEDB)
The LED Register B (LEDB) is a Read/Write register. It contains controls for the
eight on-board surface-mount LEDs as well as the optional LAN status LEDs.
Table 44. LED Register B (LEDB) Offset Address 0x14
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STLEDD S1 LEDB0 TLEDC LAN2 LAN1 LAN0 LEDB2 LEDB
STLEDD LED
= 1
TLEDC = 0 Status LED C off
S
AN[2:0] indicate Port 0 Status
L= 000 Status LEDs C and D
= 001 Status LEDs C and D indicate Port 1 Status
…. ….
= 111 Status LEDs C and D indicate Port 7 Status
EDB2 ntrolled by register bits STLEDC
L= 0 Status LEDs C and D co
EDB[1:0] = 00 On-Board LEDs indicate Boot Status (default)
L
= 01 On-Board LEDs indicate LAN Status
= 10
= 11 On-Board LEDs controlled by LED Register A
y LEDB[1:0] are further explained below in Table 45.
n-Board LED (L7 – L0) functions determined bO
= 0 Status D off
Status L
= 1 Status LED C on
Status LEDs C and D indicate Port 2 Status = 010
and STLEDD
Status LEDs C and D indicate LAN Status for port = 1
defined by LAN[2:0]
On-Board LEDs indicate BCM5388 Ethernet Switch Load
Status
E
D D on
Table 45. On-board LED functions as determined by LEDB [1:0]
LEDB
[1:0]
00
01
10
11
L7
M538
BC
LE
LOAD7 LOAD6 LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0
LEDEDALEDA2 LEDA1 LEDA0 A7 L6 LEDA5 EDA4 LEDA3 L
8
DERR
AN7 LANLAN5 LAN4 LANL6 3 LAN2 LAN1 LAN0
L6 L5 L4 L3 L2 L1 L0
RC_BREINITABTSTTST2ST1 0
ZIOOT SET CT 3 B BTBTST
October 10, 2006 Copyright 2006, SBE, Inc. Page 56
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.16 Device Control Register (DCR)
The Device Control Register (DCR) is a Read/Write register, which controls the CP
U
timer enable and three resets.
The Reset pulse applied to any device must conform to the specifications of that particular device.
Please refer to the applicable device manual for details.
Table 46. Device Control Register (CSR) Offset Address 0x
15
BBBBBB
it 7 it 6 it 5 it 4 it 3 it 2 Bit 1 Bit 0
ReCReReDOT8T T served Reserved TREN servedservedCRST 110L_RSETHRS
he CPU Timer Register is a Read-Only register. It is used for measuring CPU
T
performan
PI serial clock, i.e. once every 640 ns.
S
The CPU Timer Register
Section 4.2.16). Otherwise, it is held to a count value of 0x00 when DCR bit 5 is “0.
Bit 7 B1 Bit 0
CTR7 CTR6 CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
TR[7:0] = 0x00 –> 0xFF (when DCR bit 5 = 1)
C
CTR[7:0] = 0x00 (when DCR bit 5 = 0)
October 10, 2006 Copyright 2006, SBE, Inc. Page 57
ce. The register value increments once for each tick of the (1.5625 MHz)
is enabled by writing a “1” to DCR bit 5 (CTREN, see
Table 47. CPU Timer Register (CTR) Offset Address 0x16
it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.18 Warm Reset Register (WRR)
The Warm Reset Register is a Read/Write Register. Writing a value of 0x77 to the
Warm Reset Register initializes a Warm Reset. The actual reset signal is driven by
the CPLD 1-2 milliseconds after writing 0x77 to the WRR. The CPU, System
Controller, CPLD registers, T8110, Disk on Chip, Ethernet Switch and PHYs, and
local PCI (PCI1) are all reset. Host PCI (PCI0) reset is not affected. Writing a value
ther than 0x77 to the WRR has no effect, except the value is latched and readable.
October 10, 2006 Copyright 2006, SBE, Inc. Page 58
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.21 SPI Read Byte Offset Register (SOR)
The SPI Byte Offset Select Register is a Read/Write register. It is used for selectin
the desired byte offset (within the register selected by the SAR) when rea
e BCM5388 Ethernet Switch SPI port. In the case where the entire register is not
th
ding from
g
being read, the SOR can be set to a non-zero value to index to the desired starting
byte.
The Read Byte Count Register is a Read/Write register. It is used for setting the
umber of bytes to be read when reading from the BCM5388 SPI port. When this n
register is written, the internal SPI Read State Machine is initiated. After all
requested bytes are read from the BCM5388, the RBC value is cleared.
itten, contains 3 bytes, then WBC[3:0] must be set to 0011. When this register is wr
4.2.24 SPI Data egisters (S – S
RDR0DR7)
The SPI Dae Read/Write registers. They are used for hol
ta Registers arding data
ytes to be read from or w
ritten values ot be uring an SPI
Wcannread back. They are written to the BCM5388 d
rite operation. Similarly, read values are not affected by writes. They are read
w
om the BCM5388 after an SPI read operation, and remain until the next operation.
fr
In the case of a single-byte read o
case of a multi-byte read or write, SDR0 is the least significant data byte (LSB) and
e remaining one to seven bytes are written to SDR1- SDR7 (last byte is MSB - up
th
to eight bytes total).
Table 54. SPI Data Registers (SDRn) Offset Address 0x20-0x27
Regis
ter Offset Byte
SDR0 0x20 LSB
S(2-byte DR1 0x21 MSB register)
Ster) DR2 0x22 MSB (3-byte regis
SDR3 0x23 MSB (4-byte register)
SDR4 0x24 MSB (5-byte register)
SDR5 0x25 MSB (6-byte register)
SDR6 0x26 MSB (7-byte register)
SDR7 0x27 MSB (8-byte register)
ritten to the BCM5388 SPI port. b
r write, only SDR0 (offset 0x20) is used. In the
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4.2.25 SPI Error and Status Register (SESR)
The SPI Error Register is a Read Only register. SBSY clears when the previous
operation is completed, and the SPIFER, RACKER, and BYTER error flags clear
when the next operation is started.
SBSY can be polled immediately after writing to the RBC or WBC registers.
PIFER, RACKER and BYTER are valid after SBSY=0 (Interface Ready), but are
S
cleared when writing to the RBC or WBC registers for the next operation.
T
able 55. SPI Error and Status Register (SESR) Offset Address 0x1F
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ReserBSY ved Reserved Reserved Reserved BYTER RACKER SPIFER S
SBSPI Interface ready for ree ope
SY = 0 ad/writration
= 1 ation in pess
PIR = 0 SPIF Check passed
S FE
= 1 RACK Check failed; no operation performed
BYTER
= 1 Byte count was zero; no operation performed
= 1 SPIF Check failed; no operation performed
= 0 RACK Check passed RACKER
= 0
SPI Interface busy; operrogr
Byte count was OK
4.2.26 EEPROMddress (EAR)
ARegister
he EEPRO Addres Register is a Read/Write register. It is used for selecting the
TMs
desired (bit waddress when accessing the serial EEPRO
16-ord) M.
Table 56. EEPROM Address Regi
ster (EAR) Offset Address 0x28
Bit 7
EAR7 EAR6 EAR5 EAR4 EAR3 EAR2 EAR1 EAR0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EAR[7:0] = 0x00 – 0xFF (Word Address)
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4.2.27 EEPROM Operation/Status Register (EOS
The EEPROM Operation and Status Register is a Read/Write register. It is used for
initiating a read or write operation to the EEPROM, and chec
tatus after a write operation.
s
R)
king the programming
Bits 0-3 are self-clearing, and bit 7 clears when the next operation is started.
Attempting
stalled results in a write error, setting WERR bit. These addresses are reserved for
in
to write EEPROM word addresses 0x00-0x0F without the FAC jumper
SBE board ID identification and are programmed by SBE during board
manufacturing.
Ta9
ble 57. EEPROM Operation/Status Register (EOSR) Offset Address 0x2
Bit 7 Bit 5 Bit 3 Bit 2 1 Bit 0
WERR d ReservedERD EWDS R EWEN ReserveEBSY EW
R R R R W W W W
Bit 6 Bit 4 Bit
EWEN: Writing a “1” to this bit initiates a EWEN cycle, required before a write.
EWR: Writing a “1” to this bit initiates a write, using the EAR address and
EDR data.
EWDS: Writing a “1” to this bit initiates a EWDS cycle, required after a write.
RD: Writing a “1” to this bit initiates a read, using the EAR address and
E
EDR data.
EBSY = 0 EEPROM is ready for next write operation
= 1 EEPROM is busy writing (no reads or writes allowed)
WE 0 Write operation completed successfully
RR =
= 1 Write error, operation not completed
For mnsult the device data sheets. Devices supported include
ore information on the serial EEPROM, co
Atmel AT93C66A, Microchip 93LC66C, and ST Microelectronics M93C66.
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4.2.28 EEPROM Data Registers (EDR0 – EDR1)
They are used for holding
EEPROM Data Registers are Read/Write registers. The
data bytes to be read from or written to the serial EEPROM.
Values written to EDR0-1 are stored in an internal shift register and cannot be read
bacading EDR0-1. They are written to the EEPROM during a write operation.
k by re
Reading EDR0-1 returns serial data obtained from the most recent EEPROM ERD
ope
ration.
All read/write operations are 2-bytes, since the EEPROM is organized in a x16
format. EDR0 is the least significant data byte (LSB) and EDR1 is the most
sign
ificant data byte (MSB).
Ta
ble 58. EEPROM Data Registers (EDRn) Offset Address 0x2A-0x2B
Ri
eg ster Offset Byte
EDR0 0x2A LSB
EDR1 0x2B MSB
4.3 Accessing the Serial EEPROM
The serial EEPROM (Atmel AT93C66A and other manufacturers) is organized
256 words of 2 bytes each. One word address is accessed per operation using the
CPLD state machine.
4.3.1 Reading a
n EEPROM Address
A. Set to EEPROM Address
address.
B. Check the EBSY flag in the EEPROM Operation/Status Register (EOSR, see
Section 4.2.26). If set to “0”, proceed to the next step.
C. Write a “0x08” to the EOSR. This starts the read operation, which typically
takes 35 us to complete.
. Check the EBSY flag. If set to “0”, the D
E. Read the data bytes from the EEPROM Data Registers EDR0 (LSB) and EDR1
(MSB). See section 4.2.27
with
Register (EAR, see Section 4.2.25) to the desired word
data is ready – proceed to the next step.
for the register description.
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4.3.2 Writing an
EEPROM Address
A. Check the EBSY flag in the EEPROM Oper
Section 4.2.26). If set to “0”, proceed to the next ste
B. Write a “0x01” to the EOSR. This starts the Write Enable operation (EWEN).
C. Check the EBSY flag. If set to “0”, EWEN is complete – proceed to the next
step.
. Set the EEPROM Address Register (EAR, see Section 4.2.25) to the desired
D
word address.
E. Write data bytes to
F. Write a “0x02” to the EOSR. This starts the write operation, which typically
takes 3 ms to complete.
G. step.
Check the EBSY flag. If set to “0”, proceed to the next
H. Check the WERR flag. If set to “0”, the write was successful. Otherwise, a writ
protect or other error pre
I. If writing more data, repeat steps [D] through [H]. If finished writing, proceed
the next step.
J. Write a “0x04” to the EOSR. This starts the Write Disable operation (EWDS).
the EEPROM Data Registers EDR0 (LSB) and EDR1 (MSB).
vented the write operation from completing.
ation/Status Register (EOSR, see
p.
e
to
4.4 Accessing t
4.4.1 Registers
4.4.2 BCM5388
he SPI Interface
Third for
s is a description of the interface in the CPLD on the HW400c/2 boa
ccessing the read and write registers of the BCM5388 Ethernet switch. The CPLD
a
acts as a simplified wrapper for customer and test access to the complex, multi-state
serial SPI interface of the Ethernet switch. The switch has up to 255 p
registers and up to 255 registers per page. The registers vary in length from 1 to 8
bytes, and are byte addressed
ages of
in the CPLD
efer to Sections 4.2.18 to 4.2.24 for CPLD register details. These are the registers
R
within the CPLD used to access the registers of the BCM5388 Ethernet switch.
(These are NOT the Eth
description, page addresse
registers).
ernet switch registers. See the BCM5388 User Guide for full
s, register addresses and byte lengths of each of its
Registers Access Rules
There are a few rules for accessing the BCM5388 registers that must be followed fo
successful reads and writes. For writes, the exact register size must be written to the
WB
C register, or the write operation will not be completed. For reads, setting the
r
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HighWire HW400c/2 User Reference Guide Rev 1.0
RBC to a size that exceeds the actual register size will result in an incorrect read
e. valu
No error flags will be set to indicate these types of errors.
er size values
!
When reading or writing the BCM5388 registers, ensure that the regist
re in strict accordance with the BCM5388 data sheet.
a
4.4.3 Reading BCM
An incorrect read value will result if this count exceeds the size of the Ethernet
!
5388 Register
. Check the SBSY flag in the SPI Error and Status Register, bit 0 (SESR, see
A
Section 4.2.24). If set to “0”, proceed to the next step.
B. Set the SPI Page Register (SPR, see Section 4.2.18) to the desired register page
of the Ethernet switch.
C. Set the SPI Address Register (SAR, see Section 4.2.19) to the desired register
base byte address within the selected page.
D. Set the SPI Read Byte Address Offset Register (SOR, see Section 4.2.20) to the
first byte to be read of the Ethernet switch register:
‘0’ for the first byte, bits 0-7 (LSB) of the register
‘1’ for the 2
E. Set the Read Byte Count Register (RBC, see Section 4.2.21) to the count of bytes
to read. This step initiates reading from the switch to the CPLD.
switch register. There are no error flags to indicate this type of error.
F. Poll the SBSY flag until it equals “0”.
G. Check the SESR for any error flags. If no errors, proceed to the next step.
nd
byte, bits 8-15, and so on.
H. Read each byte out of the SPI Data Registers (SDR0-7, see Section 4.2.23). The
first byte is LSB.
4.4.4 Writing a BCM5388 Register
A. Check the SBSY flag in the SPI Error and Status Register, bit 0 (SESR, see
Section 4.2.24). If set to “0”, proceed to the next step.
B. Set the SPI Page Register (SPR, see Section 4.2.18) to the desired register page
of the Ethernet switch.
C. Set the SPI Address Register (SAR, see Section 4.2.20) to the desired register
base byte address within the selected page. (There is no byte offset for writing.)
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HighWire HW400c/2 User Reference Guide Rev 1.0
D. Write the bytes to be written into the SPI Data Reg
4.2.24), beginning with LSB in SDR0.
E. Set the Write By te Count Register (WBC, see Section 4.2.23) to the count of
bytes to write. This step initiates writing to the Ethernet switch.
!
The register will not be written if this count differs from the size of the Ethernet
switch register. There are no error flags to indicate this type of error.
F. Poll the SBSY flag until it equals “0”.
G. Check the SESR for any error flags. If no errors, the operation is complete.
isters (SDR0-7, see Section
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HighWire HW400c/2 User Reference Guide Rev 1.0
N
5 LINUX ON THE H
W400C/2 AND HOST SYSTEM
The HW400c/2 uses an off the shelf 2.6.9 PPC Linux kernel distribution from Gentoo
(
www.gentoo.org) with some additional files added specific to the HW400c/2, and
with the GenericHDLC WAN stack enabled. The Gentoo Linux kernel may be
delivered as a generic compressed archive that can be downloaded, or on a CD-ROM
available from SBE. The compressed image is the tar gzip (.tgz) format, the form
typically used for software obtained from the SBE website at http://www.sbei.co
To summarize, the Linux kernel for the HW400c/2 is installed on a host system that
also runs Linux. See Figur
the host system in the /opt/gentoo/ directory and must be made available
HW400c/2 board via NFS. After correctly configuring the network interface on the
HW400c/2 with U-boot (the Boot ROM program), the Gentoo Linux kernel is
downloaded to the HW400c/2 board using tftp. You can then boot the Linux kernel
which mounts the NFS root file system. The PPC version of the Gentoo Linux
distribution contains the necessary PPC architecture to allow the kernel and all
drivers to be compiled natively on the HW400c/2, eliminating the need to for a cr
compile development envi
The next few sections list the requirements and explains the processes required for
installing Gentoo Linux for the S
Section 5.5 explains how to config
ernel.
k
HW400c/2
U-boot
ASCII
terminal
m.
e 14. The root file system for the HW400c/2 is installed on
to the
,
oss-
ronment on the host system.
BE HighWire 400c/2 on a host Linux system.
ure your HW400c/2 and how to boot the Linux
Linux 2.6
etwork connection
Host System
Services:
nfs
tftp
Console port
9600 8n1
bootp
PPC OS:
/opt/gentoo
Figure 14. HW40 c/2 Network and System environment
0
5.1 Host Hardwa
re and Software Requirements
In order to install Gentoo Linux as a development environment on a host Linux
system, the host system must satisfy the following minimum requirements:
• Intel Pentium or compatible processor
• 64 Mbytes (or better) RAM
• 750 Mbytes available disk space
• Ethernet
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HighWire HW400c/2 User Reference Guide Rev 1.0
• Recent distribution of Linux installed. Because Gentoo Linux is based on the
2.6 series Linux kernel, it is best to use Gentoo Linux in conjunction with a
host that has a Linux distribution based on the 2.6 kernel.
5.2 Network and System Configuration
Booting Linux on the HW400c/2 requires services that are traditionally installed as
part of a server or d
development system that you will use to host one or more HW400c/2s and your
desktop Linux distribution supports a server-class installation, we suggest that you
use this installati
your desktop Linux system includes a firewall, you might find that it is pre-
If
configured to suppress many of the types of communications (FTP, TFTP, DHCP,
NFS, etc.) that the HW400/c2 requires in order to boot. If you cannot successfully
boot your board using the instructions provided in this
cannot communicate with the system on which you installed the Gentoo Linux
distribution, make sure that you have either disabled any default firewall installation,
or that you have at least enabled the specific services necessary to boot Linux as
described in this chapter.
evelopment Linux installation. If you are putting together a
on class.
section because the board
5.3 Installing Lin
!
ux on your host system
For simplicity, the following instructions assume that you are installing from a
downloaded
Copy the archive file to /opt and uncompress it. You should use the followin
ommands to uncompress the archive and extract its contents: c
tar -zxvf <downloaded#
# c
d <extracted_directory>
Oncxtion
e e tracted, you will find a complete Gentoo PPC Linux source code distribu
under /
kernel i
The version of Gentoo from
operation on the HW400c/2. The Gentoo Linux distribution for the HW400c/2 be
obtained from SBE.
You m
xamples in this section show the standard prompt for the root user, #. You should
e
ot type the # character when entering the commands described in this section.
n
Before installing the Linux kernel you should read any available Release Notes.
copy Gentoo Linux for the SBE HW400c/2 from SBE’s ftp archive.
g
_file>
opt/gentoo. This file system will be used to create the downloadable
mage for the HW400c/2.
www.gentoo.org does not have the extra files needed f
ust have root privileges to install the Gentoo Linux distribution. All of the
or
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.4 Configuring
5.4.1 Modifying
5.4.2 Configurin
!
the Host System
The next few sections describe daemons and system services that must be installed
and correctly activated in order to boot the Linux kernel on the HW400c/2 and
subsequently compile applications for the HW400
c/2.
the Host Path
nce all software is compiled natively on the HW400c/2, there is no need to modify
Si
the host’s path.
g the Host NFS Server
The Linux kernel is a ready-to-run root file system for your target architecture,
enabling you to boot your target embedded system over the network using the
exported file system as the target’s root file system. Although you might eventuall
ant to use a small, specific root file system as an initial disk-on-chip imw
nal product, having access to a complete Linux distribution and tool set for your
fi
target system provides you with access to a wide range of Linux software for testing
and debugging purposes.
To export the root file system, you will need to edit
your host machine, adding an entry for that file system that looks something like the
following:
p
# /o t/gentoo 10.0.0.10(rw,no_root_squash)
Thin
s e try consists of two fields:
the /etc/exports file on
age for your
• of the directory being exported by the host system as the
The full pathname
root file system for
•
Access information for the exported file system. This consists of the IP
address of the system that you want to be able to access the exported file
system, followed by a description of the type of access that the target system
will have to the exported file system, enclosed within parentheses.
The IP address of the target system depends on the IP address that is assign to the
HW400c/2 board. The value shown in the previous example is a commonly used
non-routable IP address, and is the IP address used in the examples in this sect
You should s
r you can simply enter a * in order to grant access to the exported file system to any
o
host.
Using * to specify the IP addresses of hosts permitted to access an exported file
system is extremely insecure and should only be done if you are on a trusted, private,
non-routable network and the system exporting the file system is not exposed to the
Internet.
pecify the IP address that you have assigned to your HW400c/2 board,
the target system
ion.
y
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HighWire HW400c/2 User Reference Guide Rev 1.0
The parenthesized access privilege values shown in the previous example should be
sufficient. These access privileges specify that the target system at the specified IP
dress will have read/write access to the exported file system, and that the user ID
ad
ID) of the root user on the target system will not be prevented from writing or
(U
modFS mounted file system.
ifying files in the N
fter adding appropriate entries to the /etc/exports file on the host system, you
A
will then need to restart (or start) the NFS daemon on your host system, which can
usually be accomplished by using the following commands:
# /etc/rc.d/init.d/nfslock restart
# /etc/rc.d/init.d/nfs stop
# /etc/rc.d/init.d/nfs start
You should separately start and stop the NFS service rather than simply restarting it
because the only restarts the wrapper service,
ther than the mountd andnfsd daemons.
ra
nfs restart rpc.mountd
The commands shown in the previous listing are for a Red Hat Linux system running on the Host. If you
are using another Linux distribution such as Mandrake, Debian, or others, the commands to start, stop,
or restart the NFS lock and mount daemons may be different.
For more information about NF
S, see the following:
• The NFS FAQ at http://nfs.sourceforge.net/
• The NFS HOWTO at http://nfs.sourceforge.net/nfs-howto/
5.4.3 Configurin
g Host tftp services
One of the ways the SBE HW400c/2 boots is by using the Trivial File Transfer
Protocol (TFTP) to download a kernel image to the board. This
requires that a TFTP
server be available on the system on which you are hosting the Gentoo Linux kernel.
n mpart of a network-
Oost modern Linux systems, the TFTP server is installed as a
capable system installation, but is usually deactivated. This section explains ho
w to
activate the TFTP server on your Linux system and how to copy the Gentoo Linux
kernel into the area from which the TFTP server can deliver the kernel to the
HW400c/2.
ain a binary
version for most Linux distributions from http://www.rpmfind.net/ by searching for the strin
not availabIf a TFTP server isle on your Linux distribution or installed system, you can obt
g tftpd.
Before configuring the TFTP daemon itself, make sure that the entries for the
TFTP
protocol are not commented out in the /etc/services file. This file is typically
consulted by each net
hould use. You must be root to edit this file. Entries in this file are commented out if
s
ey are preceded with a hash-mark (#) in the file - to activate them, use your favorite
th
work service in order to determine the network ports that it
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HighWire HW400c/2 User Reference Guide Rev 1.0
text editor to remove the hash mark on each line that contains the string tftp. Active
TFTP entries in /etc/services should look like the following:
tftp 69/tcp
tftp 69/udp
Depending on the Linux distribution and version you are using on the host, Linux
systems typically use one of two mechanisms to activate and manage network servers
such as TFTP servers. These are the Extended Internet Services Daemon, xinetd
tand the older Internet Services Dameon, inetd. Bo h the xinetd and inetd
manage a variety of network services by monitoring various network ports and
tarting the appropriate daemon in response to a valid request. Ts
more modern of thes
an the older inetd.
th
e two mechanisms, and is generally viewed as being more secure
To determine which of these mechanisms your system uses to manage Internet
services, you can use the system’s ps
This example shows that the sy
services. In this case, you should follow
om this command on your system shows that it is running the inetd, proceed to
fr
stem is using the xinetd server to manage Internet
the instructions in Section 5.4.5. If the output
the next section,Section 5.4.4.
,
he xinetd is the
.. .
5.4.4 Configuring tftp with inetd
he servers that can be managed by the are listed in the file
Tinetd /etc/inetd.conf. Each line in this file contains the entry for a specific server.
To enable the TFTP server, edit the file /etc/inetd.conf as the root user on
your system, and locate the line that looks like the following:
#tftp dgram udp wait root /usr/sbin/tcpd in.tftpd
Uncomment (remark) from the beginning of this line, save the
modifie
d file, and exit the editor.
Add the option and value -s /tftpboot to the end of this line. This specifies the
direr in which
cto y in which the TFTP server will look for files. This is the directory
you wil
HighW
l put the compiled Gentoo Linux kernel image (
ire HW400c/2 will download and boot.
Next, force the inetd to reread its configuration file. Because all Linux
distribu
tions use different mechanisms for starting and stoppping system processes,
the easiest way to do this is to send the HUP signal to the running inetd process.
o do th s, you must first locate the process ID of the inetd process that is
Ti
currently running on your system using the ps (process status) command, as in the
following example:
move the hash
uImage
) that the SBE
October 10, 2006 Copyright 2006, SBE, Inc. Page 71
The alxww options to ps cause the command to display all system processes in an
extremely wide listing. The grep then searches for the string inet in the resulting
output. Each line of the output from the command shown in this example therefore
displays information about a running command whose nam
e or arguments contain the
string inet. Of these, the first is the actual inetd process, and the third whitespace-
separated field in this output is its process ID (578 in this example), which is the
information that you will need to restart the process.
After collecting this information, you can cause the inetd process to reread its
configuration file b
# kill -HUP 578
After executing this command, the TFTP s
y executing a command like the following:
erver will be started on your system in
response to incoming TFTP requests.
e system is running a Linux distribution such as Red Hat Linux that starts and stops system
If th
processes using rc scripts, you may simply restart the inetd by invoking these scripts in the follo
way:
# /etc/rc.d/init.d/inet restart
This command will stop and then restart all of the Internet services on the Linux system. You may not
want to do this if your system is running Internet services on which other systems depend, as it will
cause a slight interruption in those services
he final step in configuring the TFTP server on the host Linux systeT
.
m is to copy the
Gentoo Linux kernel that the SBE HighWire HW400c/2 will download and boot
from into the /tftpboot directory so that the board can access it:
• If the /tftpboot directory does not already exist, create it as the root user
on the host system with the mkdir /tftpboot command.
# mkdir /tftpboot
• Copy the compiled Gentoo Lin
/tftpboot
directory from the top level of the directory structure that was
ux kernel file, uImage, into the
created when unpacking the files of the downloaded Gentoo Linux archive.
You can now proceed to the Section 5.4.6 to set up communications with your SBE
HW400c/2 bx.
oard to download and boot Gentoo Linu
wing
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HighWire HW400c/2 User Reference Guide Rev 1.0
d 5.4.5 Configuring tftp with xinet
The servers that can be managed by the xinetd are each listed in a server-specific
configuration file located in the directory /etc/xinetd.d. The file for the TFTP
server is aptly named tftp, and looks like the following:
# default: off
description: The tftp server serves files using the Trivial File Transfer \
#
Po
# rot col. The tftp protocol is often used to boot diskless \
# ws
ork tations, download configuration files to network-aware printers, \
# and to start the installation process for some operating systems.
service tftp
{
no
socket_type = dgram
per_source = 11
cps = 100 2
flags = IPv4
}
disable =
protocol = udp
wait = yes
user = root
server = /usr/sbin/in.tftpd
server_args = -s /tftpboot
To enable the TFTP server, edit this file (as root), changing the line that reads
disable = yes so that it reads disable = no.
Next, force the xinetd to reread its configuration files. Because all L
istributions use different mechanisms for starting and stopping system processes, the
d
easiest way to do this is to send the HUP signal to the running xinetd process. To
do this, you must first l
ocate the process ID of the xinetd process that is currently
running on your system using the ps (process status) command, as in the following
example:
# ps -eal | grep xinet
5 S 0 2292 1 0 76 0 - 946 - ? 00:00:00 xinetd
The example line shows the xinetd process ID number, in the fourth whitespaceseparated field (2292 in this example), which is the information that you will need to
restart the process. After collecting this information, you can cause the xinetd
rocess to reread its configuration files by executing a command like the following: p
# kill -HUP 2292
fter executing this command, the TFTP server will be started on your system in
A
spequests.
re onse to incoming TFTP r
inux
stem
# /etc/rc.d/init.d/xinetd start
If your system is running a Linux distribution such as Red Hat Linux that starts and stops sy
rocesses using rc scripts, you can simply restart the xinetd by invoking these scripts in the p
y:
wa
# /etc/rc.d/init.d/xinetd stop
Then;
following
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HighWire HW400c/2 User Reference Guide Rev 1.0
This command will stop and then start all of the Internet services on your Linux system. You may not
want to do this if your system is running Internet services on which other systems depend, as it will
cause a slight interruption in those services.
he final step in configuring the TFTP server on your Linux system is to copy the
T
o
c mpiled Gentoo Linux kernel image uImage, into the /tftpboot directory so
tha
t the HW400c/2 can download it and boot:
• If the /tftpboot directory does not already exist, create it (as root) on
your systemmkdir command:
using the
# mkdir /tftpboot
• Copy the compiled Gentoo Linux kernel, uImage, into the /tftpboo
directory from top level of the dire
ctory structure that was created when you
unpacked the files in the downloaded SBE Gentoo Linux archive.
ooceed to Section 5.4.6 to set up communications with your SBE
Y u can now pr
Hioad and boot the Linux kernel.
ghWire HW400c/2 board and downl
t
5.4.6 Configuring
If you are not assigning a static IP address to be stored in the HW400c/2 non-volatile
me ory, it is necessary to configure a bootp server. Bootp (a precursor to DHCP)
will assign an IP address to a device with a specific MAC address based on what is
found in a look
broadcast a BOOTP_REQUEST over the network. If a server is actively running
b
matching MAC address is found, the server will send a BOOTP
H
A btpg bootp daemon, bootpd, and
a bo pnning on your system, enter:
If bootpd is running, you should see something similar to the following;
a bootp Server
m
up table called bootptab. At power up, the HW400c/2 will
ootpd, that server will look through its bootptab for a matching MAC address. If a
_REPLY to the
W400c/2’s MAC address and assign the IP address found in the bootptab file.
oo server has two prerequisites; an actively runnin
ot look up table, bootptab. To check if bootpd is ru
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HighWire HW400c/2 User Reference Guide Rev 1.0
If you don’t already have one, the easiest way to create a bootp server is to have it
reside on the same LAN subnet as the HW400c/2. Creating bootp relay agents for
bootp servers on different
LAN segments is beyond the scope of this document.
o set up a server with BOOTP with TFTP ability in a standard Linux box,
T
uncomment (or add) these two lines in inetd.conf)
This section describes the processes necessary to boot using each of the three
methods. In each case, the boot firmware U-boot, loaded in on-board flash, is
necessary to initialize the HW400c/2. The boot instructions for three methods
mentioned above diverge slightly from that point.
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.1 U-boot, Universal Bootloader
The HW400c/2 uses a boot ROM based on Das U-boot. U-boot (Universal
Bootloader) is an off-the-shelf freeware package found on Sourceforge.net. Ma
commands and environment variables are available in U-boot to facilitate the
f the Linux kernel from various locations.
o
5.5.1.1 U-boot commands
There are four basic U-boot commands that are used to configure the environment
ariables for the boot environment. All commands are available at the debug>
v
prompt. A complete list of U-boot environment variables can be found in Appendix
B .
help List all commands and environment variables
printenv Print a list of all valid environment variables that are currently in use.
This command can be shortened to print.
printenvat are not set (unused
In the command, Parameters th), have no value assigned, or an
incorrect value, will not be displayed.
setenv <variable_name> <value>Set an environment variable_name to value. Can be shortened to
set.
aveenv Save environment variable(s) to non-volatile memory. Can be
s
shortened to save.
ny
loading
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.1.2 U-boot environment variables
U-boot has large number of environment va
riables and commands. While most can
be used with the HW400c/2, only a few are necessary for the boot process. A
complete list of U-boot environment variables can be found in Appendix B .
Lis
t of basic boot variables:
bootargBoot arguments. Arguments passed to the kernel. Configures the
s
HW400c/2 console (debug) port for the Linux kernel, the location of
the IP address, if not static, the NFS device, and the NFS root path.
Multiple bootargs n
eed only be separated by a space (see Section
5.5.2.1). Sample bootargs;
for
console=ttyMM0,9600n8 Console port configuration
the Linux kernel. Console tty is
ttyMM0, 9600 baud, 8 bits, no
parity.
e conrg, most of the Linux boot messages will not be displayed.
. bootarg lines of around 250 characters can be executed, however, storing the bootargs in flash
2
memory is lid to 80 characters. See Table 10. If you need extra room for bootargs, please cal
SBE Technical S
sole boota1. Without th
mitel
upport.
ip=bootp
If bootp is used, get the IP
address from there. Other
settings a
5.5.2.2 fo
pply. See section
r setting static IP
addresses
nfsroot=/opt/gentoo NFS root file path
.
root=/dev/nfs rw NFS root device.
The name of the bootfile, e.g. uImage bootfile
bootcmdBoot commands executed during automatic boot (autoboot). M
ultiple
commands must be separated by a semi colon
followed by a space,
followed by the next command.
e semi colon must be backslash escaped or the second command will not be recorded. Example;
# set bootcmd tftpboot\; bootm
Th
bootdelay The delay time in seconds until autoboot (executes bootcmd)
begins. A countdown is displayed on the command line. Any
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HighWire HW400c/2 User Reference Guide Rev 1.0
keystroke will stop the countdown and drop into the U-boot debug
shell.
baudrate Baud rate of the HW400c/2 console (debug) port
ethaddr This
unit’s MAC address.
he MAC address is assigned by SBE at the time of manufacture, stored in non-volatile memory, and
T
must not be altered. Any attempt to change the MAC add
ress will be ignored.
ipaddrThis unit’s static IP address (if used) i
should be set to 0.0.0.0 for clarification. When us
n dot notation. If not used,
ing bootp, this
address is ignored.
serverip
The tftp server’s IP address in dot notation. If not used, should be set
to 0.0.0.0 for clarification. When using bootp, this address is
ignored.
gatewayip The gateway system’s IP address in dot notation. If n
be set to 0.0.0.0 for clarification. When using boo
ot used, should
tp, this address is
ignored.
etmask This unit’s netmask in dot notation. If not used, should be set to
n
0.0.0.0 for clarification. When using bootp, the mask is ignored.
Fixed environment variables.
These variables will be displayed and cannot be changed.
stdinSource of the HW400c/2’s standard input (keybo
Default= (debug port).
serial
ard).
stdout
Destination of the HW400c/2’s standard output (terminal screen).
Default= Cannot be deleted (debug port).
stderrDestination of the HW400c/2’s standard error (console error
messages). Default=serial (debug port).
ethact Active MAC port. Default=
mv_eth0
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.1.3 Power up call trace
For reference purposes, this is a summary of the power up calls after U-boot runs and
jumps to _start.
2. Urt. Normally _start is at address 0. See System.map
-boot jumps to address _sta
3. The call to gigateak_setup_arch() is made via the function pointer
ppction pointer is initialized in platform_init().
_md.setup_arch(). This func
4. gitra file needed for Gentoo to boot on the HW400c/2
gateak.c is the ex
k.c)
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.2 Booting with tftp
Tftp boot requires a tftp boot server and an NFS mounted file syste
dress is not assigned to the HW400c/2 through the boot console, a bootp server
ad
may also be necessary. The bootp server, tftp server, and the NFS server functions
5.5.2.1 U-boot pa
may or may not be the same machine.
rameters for tftp with bootp
The following example shows U-boot parameters necessary for a tftp download and
boot using a IP address obtained from a bootp server. The bootp server will assign an
IP address, a gatew
Ass listed in
ignments are based on the HW400c/2’s MAC address. The IP addresses
the printenv the unused IP
addd confusion and show that they are not in use.
resses are set to 0.0.0.0 to avoi
ay IP address, and a boot file image name from its bootptab.
October 10, 2006 Copyright 2006, SBE, Inc. Page 80
HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.2.2 U-boot pa
rameters for tftp with static IP address
The following example shows U-boot parameters necessary for a
boot w
ith a static IP address assigned using the U-boot command:
# set ipaddr <ip address>
Using this method, the gatew
(serverip), netmask (netmask), and
ay IP address (gatewayip), the tftp server IP address
boot file name (bootfile) must also be
assigned using the u-boot command set. The IP address and S
strings must then ad
use the save command to store the variables in non-
October 10, 2006 Copyright 2006, SBE, Inc. Page 81
HighWire HW400c/2 User Reference Guide Rev 1.0
TFTP from server 10.0.0.5; our IP address is 10.0.0.10
Filename 'uImage'.
Load address: 0x400000
Loading: ########################################
##################################
#################################################
#################################################
###############################
done
Bytes transferred = 1551015 (17aaa7 hex)
## Booting image at 00400000 ...
Image Name: Linux-2.6.9
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1550951 Bytes = 1.5 MB
Load Address: 00000000
Entry
Verifying Checksum ... OK
Uncompressing Kernel Image ... O
## Transferring control to Linux (at
setup_arch: enter
setup_arch: bootmem
gigateak_setup_arch: enter
gigateak_setup_arch: calling setup_bridge
IGNP jumper is installed
Host PCI is not present
mv64x60 initialization
mv64x60 initialization done
gigateak_setup_peripherals: enter
gigateak_intr_setup: enter
gateak_intr_setup: exit
gi
gigateak_setup_peripherals: exit
In gigateak_setup_ethernet
gateak_setup_arch: exit
gi
arch: exit
mv64460_init_irq: enter
mv64460_init_irq: exit
Point: 00000000
K
address 00000000) ...
Total memory = 256MB; using 512kB for hash table (at 80400000)
Linux version 2.6.9 (root@localhost) (gc
SBE Gigateak HW400c/2 port
Built 1 zonelists
Kernel command line: console=ttyMM0,9600n9 ip=bootp nfsroot=/opt/gentoo
PCI: Probing PCI hardware
gigateak_map_irq 14F1:8474 slot=1 pin=1 irq=81
gigateak_map_irq 14F1:8474 slot=1 pin=2 irq=82
SCSI subsystem initialized
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
Initializing Cryptographic API
MV64x60 watchdog driver
ipmi message handler version v33
ipmi device interface version v33
IPMI System Interface driver version v33, KCS version v33, SMIC version v33,
ipmi_si: Trying "kcs" at I/O port 0xca2
ipmi_si: Trying "smic" at I/O port 0xca9
ipmi_si: Trying "bt" at I/O port 0xe4
ipmi_si: Unable to find any System Interface(s)
IPMI Watchdog: driver version v33
Copyright (C) 2004 MontaVista Software - IPMI Powerdown via sys_reboot version
Serial: MPSC driver $Revision: 1.00 $
ttyMM0 at MMIO 0xf1008000 (irq = 36) is a MPSC
ttyMM1 at MMIO 0xf1009000 (irq = 38) is a MPSC
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
M
eth0: port 0 with MAC address 00:a0:d6:62:39:03
eth0: RX NAPI Enab
October 10, 2006 Copyright 2006, SBE, Inc. Page 82
HighWire HW400c/2 User Reference Guide Rev 1.0
HDLC support module revision 1.17
Cronyx Ltd, Synchronous PPP and CISCO HDLC (c) 1994
Linux port (c) 1998
Loading Adaptec I2O
Detecting Adaptec I2O RAID controllers...
megaraid cmm: 2.20.2.0 (Release Date: Thu Aug 19 09:58:33 EDT 2004)
megaraid: 2.20.4.0 (Release Date: Mon Sep 27 22:15:07 EDT 2004)
mice: PS/2 mouse device common for all mice
i2c /dev entries driver
NET: Registered protocol family 2
IP: routing cache hash table of 2048 buckets, 16Kbytes
TCP: Hash tables configured (established 16384 bind 32768)
ip_conntrack version 2.1 (2048 buckets, 16384 max) - 336 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
ipt_recent v0.3.1: Stephen Frost <sfrost@snowman.net>.
arp_tables: (C) 2002 David S. Miller
NET: Registered protocol family 1
NET: Registered pro
Sending BOOTP requests . OK
IP-Config: Got BOOTP answer from 10.0.0.5, my address is 10.0.0.10
IP-Config: Complete:
device=eth0, addr=10.0.0.10, mask=255.255.255.0, gw=10.0.0.2,
host=10.0.0.10, domain=, nis-domain=(none),
bootserver=10.0.0.5, rootserver=10.0.0.5, rootpath
Looking up port of RPC 100003/2 on 10.0.0.5
ooking up port of RPC 100005/1 on 10.0.0.5
L
FS: Mounted root (nfs filesystem).
V
Freeing unused ker
INIT: version 2.86
Gentoo Linux; http://www.gentoo.org/
Copyright 1999-2005 Gentoo Foundation; Distributed under the GPLv2
* Mounting proc at /proc ... [ o
* Mounting sysfs at /sys ... [ o
* Mounting /dev for udev ... [ o
* Populating /dev with saved
* Seeding /dev with needed nodes ... [ ok ]
* Setting up proper hotplug agent ...
* Setting id k ]
/sb n/udevsen as hotplug agent ... [ o
* Starting udevd ... [ ok ]
* Populating /dev with existing devices with udevstart ... [ ok ]
* Letting udev process events ... [ ok ]
* Finalizing udev configuration ... [ ok ]
* Mounting devpts at /dev/pts ... [ ok ]
* Activating (possible) swap ... [ ok ]
* Remounting root filesystem read/write ... [ ok ]
* Setting hostname to localhost ... [ ok ]
* Calculating module dependencies ... [ ok ]
* Checking all filesystems ... [ ok ]
* Mounting local filesystems ... [ ok ]
* Activating (possibly) more swap ...swapon: /dev/sda2: No such device or
* Setting system clock using the hardware clock [UTC] ... [ ok ]
* Configuring kernel parameters ... [ ok ]
* Updating environment ... [ ok ]
* Cleaning /var/lock, /var/run ... [ ok ]
* Cleaning /tmp directory ... [ ok ]
* Caching service dependencies ... [ ok ]
* Caching service dependencies ... [ ok ]
* Caching service dependencies ... [ ok ]
* Loading key mappings ... [ ok ]
* Setting terminal encoding to UTF-8 ... [ ok ]
* net.eth0: cannot start until the runlevel boot has completed
* Starting lo
* Bringing up lo ... [ ok ]
* Initializing random number generator ... [ ok ]
NIT: Entering runlevel: 3
I
* Caching service dependencies ... [ ok
* Starting eth0 [ ok
* Keeping current configuration for eth0 [ ok ]
[ ok ]
* Setting system clock ...Sat Jan 1 01:01:00 PST 2005 [ ok ]
* Starting sshd ... [ ok ]
[ ok ]
* Starting [ ok ]
http://snowman.net/projects/ipt_recent/
address [ !! ]
local ...
his is localhost.(none) (Linux ppc 2.6.9) 11:09:54
T
ocalhost login:
l
Building Number Three Ltd & Jan "Yenya" Kasprzak.
RAID: Version 2.4 Build 5go
tocol family 17
nel memory: 128k init
booting
device nodes ... [ ok ]
=
k ]
k ]
k ]
]
]
October 10, 2006 Copyright 2006, SBE, Inc. Page 83
HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.3 Booting with Disk on Chip
A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data
storage. DoC is a high-density flash device manufactured by M-Systems
Incorporated, and has a data bus width of 16 bits. The 128 MB device is standard on
e HW400c/2, with the option of populating other devices for OEM configuratithons.
e maximum input clock frequency of the device
5.5.3.1 Loading the Disk on Chip
Burst reads/writes to the DoC are not possible due to th
3 MHz) being slower than the 100 MHz device bus (3
The Disk-on-Chip may also be used for storing a Linux ker
ed for booting, making the HW400c/2 a true stand-alone us
clock.
nel, which in turn can be
blade. Limitations to the
kernel size are in direct proportion to the size of the RAM.
Loading the DoC requires that the HW400c/2 is b
andard tftp image. See Sectst
ion 5.5.2
ooted. You may do this with the
Loading the DoC with necessary images requires the following files, all must be
cated in the same directory. lo
A. docshell A binary DoC configuration utility fro
m M-Systems
B. fmtA script that invokes docshell to do the low-level
formatting of the disk-on-chip and to create two binary
partitions.
C. wr0 A script that invokes docshell to write uImage (kernel
image) to binary partition 0.
. wr1 Ramdisk to
DA script that invokes docshell to write u
binary partition 1.
E. uImageThe kernel image.
F. uRamdisk
The ramdisk image.
The sequence of commands to load the DoC (where # is the prompt) is as follows:
# ./fmt
# ./wr0
# ./wr1
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HighWire HW400c/2 User Reference Guide Rev 1.0
5.5.3.2 Creating a uRamdisk Image
uRamdisk is a tiny kernel image needed to boot uImage from the Disk on Chip.
uRamdisk has the same intent as a ramdisk on other linux platforms. It brings up
necessary drivers needed to access the real kernel image (uImage). After booti
the HW400c/2, the following commands will create uRamdisk.
Ramdisk can be written t with the docshell utility.
u
o disk-on-chip
5.5.3.3 Booting from DoC
U-boot, the bootargs
In variable should be set as follows:
# set bootargs ip=bootp root=/dev/ram0 rw console=ttyMM0,9600n8
ramdisk_siz
# saveenv oot variables to NVRAM
e=65536
# Save the U-B
Then boot from disk-on-chip as follows:
docload
#
# bootm 400000 800000
Alternately, rese
t the card and let auto boot run.
ng
October 10, 2006 Copyright 2006, SBE, Inc. Page 85
HighWire HW400c/2 User Reference Guide Rev 1.0
5.6 Compiling the Kernel (uImage)
Unlike other some other Linux distributions, the Gentoo kernel can be nativel
y
compiled on the HW400c/2 following standard Linux kernel build procedures.
Rebuilding the kernel is necessary when changing the kernel configuration
parameters.
These are the basic steps necessary to compile the kernel natively on the HW400c/2;
1. As root, change to the kernel source directory
# cd /usr/src/linux-2.6.9-gigateak
2. Set the date (see man date) MMDDHHmmYYYY
Where MM = 2 digit month
DD = 2 digit day
HH = 2 digit hour
mm = 2 digit minutes
YYYY = 4 digit year
# date 031310002006
3. Clean up old .config files
# make mrproper
4. Create a new .config file by copying the config-save file to
.config
# cp config-save .config
5. Create the changes in the .config file
# make oldconfig
6. Compile the kernel
# make
7. Create the kernel binary (uImage)
# make uImage
8. On the
host machine, copy uImage to /tftpboot
# cp uImage /tftpboot/.
ASCII terminals, such as Minicom and Hyperterminal, may not run menu driven kernel configuration
utilities such as menuconfig properly from the HW400c/2 console. There two options here, ssh to
the HW400c/2 from the host and use menuconfig from the host path:
/opt/gentoo/usr/src/linux, then finish the compile from the HW400c/2, or on the
HW400c/2, use the config utility (make config), which will step through each option individually.
October 10, 2006 Copyright 2006, SBE, Inc. Page 86
HighWire HW400c/2 User Reference Guide Rev 1.0
5.6.1 Gentoo Application Packages Management
“Portage” is the name of Gentoo's package management system. All Gentoo
packages can be found under /usr/portage. If a package is needed, for exam
firewall or ftp services, it can be found in the portage directory. Some of the packag
names are a bit obscure (for example, ssh is found under net-misc, while
xinetd is found under sys-apps), so some research may be necessary to locate
the needed package.
inetd is not automatically installed and activated under Gentoo as under some Linux distributions
o e command:
# rc-status --all
x
(e.g.Redhat, Suse). Use the emerge function to install these packages to gain n
T query the running status of services, from the HW400c/2 console use th
etwork access.
or more information about Portage see the man page portage(5), and
F
www.gentoo.org.
There are several HOW-TO’s for various applications and services located at
http://gentoo-wiki.com/Index:HOWTO
5.6.1.1 Emerge
Emerge is the command-line interface to the Portage system run nat
W400c/2. Emerge is primarily used for installing packages, and caH
ahas. Emerge can also update the
h ndle any dependencies that the desired package
poailable. Emerge gracefully handles
ge tree, making new and updated packages avrta
pd ting installed packages to newer releases as well. It handles both source and
au
binary packages, and it c
imilar in function to s
d
Emerge is not a root-user only program. You will only need root's permissions to install, uninstall, an
sync. Normal users can use commands to query what's installed, settings, etc. However, with this in
mind, there
are packages that should only be installed as root.
an be used to create binary packages for distribution. It is
yum and BSD ports.
ively on the
n automatically
For more information see the man page .
emerge(1)
ple,
e
October 10, 2006 Copyright 2006, SBE, Inc. Page 87
HighWire HW400c/2 User Reference Guide Rev 1.0
5.6.1.2 Enable remo
te login with ssh
Gentoo Linux installs sshd by default, but it is not enabled. Before starting
ssh server look through the configuration
thing that you should consider setting is
g to log in, an attacker first must login as a
lo ins as root, which means that in order
reg
ular user (in the wheel group) and then su. This would require knowing two
pa
ime HW400c/2 console as root:
possible. To start sshd on th
rname with su access making brute force attacks nearly sswords as well as a use
file at /etc/ssh/sshd_config. One
PermitRootLogin no. This disab
# /etc/init.d/sshd start
If daemon on every start up:
you want to add sshd as a default
# rc-update add sshd
default
5.6.1.3 Starting netw rk services; xinetd
o
A lot of services depend on having the xinetd service running. Unlike sshd,
Gentoo Linux does not install xinetd by default. Use the emerge utility to inst
xinetd and its dependencies from the HW400c/2 console as root:
# emerge xinetd
ait for the console messages to stop and return to a prompt.
W
To start xine
td on the HW400c/2 console:
# /etc/init.d/xinetd start
If you want to add xinetd as a default daemon on every start up:
# rc-update add xinetd default
5.6.1.4 Starting f
tp services; vsftpd
or ftp, Gnetoo Linux uses the standard Linux ftp daemon, vsftpd. Use the
F
merge utility to load the vsftpd daemon package. As root from the HW400c/2
e
onsole:
c
# emerge vsftpd
Wait for the console messages to stop and return to a prompt.
To start vsftp on the HW400c/2 console:
# /etc/init.d/vsftpd start
If you want to add xinetd as a default daemon on every start up:
up an
les
all
October 10, 2006 Copyright 2006, SBE, Inc. Page 88
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