SANYO VPC-Z380EX, VPC-Z380E, VPC-Z380 SERVICE MANUAL

SERVICE MANUAL

FILE NO.

Color Digital Camera

Contents

1. OUTLINE OF CIRCUIT DESCRIPTION .................... 2

2. DISASSEMBLY ........................................................ 11

3. ELECTRICAL ADJUSTMENT .................................. 14

4. TROUBLESHOOTING GUIDE................................. 19

5. PARTS LIST............................................................. 20

CABINET AND CHASSIS PARTS 1 ........................ 20

CABINET AND CHASSIS PARTS 2 ........................ 21

ELECTRICAL PARTS .............................................. 22

ACCESSORIES ....................................................... 28

PACKING MATERIALS............................................ 28

CIRCUIT DIAGRAM (Refer to the separate volume)

VPC-Z380E

(Product Code : 126 252 00) (U.K.)

VPC-Z380EX

(Product Code : 126 252 02) (Europe) (PAL General)

VPC-Z380

(Product Code : 126 252 01) (U.S.A.) (Canada)

PRODUCT SAFETY NOTICE

The components designated by a symbol ( ! ) in this schematic diagram designates components whose value are of

special significance to product safety. Should any component designated by a symbol need to be replaced, use only the part

designated in the Parts List. Do not deviate from the resistance, wattage, and voltage ratings shown.

CAUTION : Danger of explosion if battery is incorrectly replaced.

Replace only with the same or equivalent type recommended by the manufacturer. Discard used batteries according to the manufacturer’s instructions.

NOTE : 1. Parts order must contain model number, part number, and description.

2. Substitute parts may be supplied as the service parts.

3. N. S. P. : Not available as service parts.

Design and specification are subject to change without notice.

SR813/E, EX, U

REFERENCE No. SM5310087

1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CA1 CIRCUIT DESCRIPTION

1. IC Configuration

IC903 (RJ23J1AA0AT) CCD imager IC902 (74VHC04MTC) H driver IC904 (LR366854) V driver IC905 (AD9802) CDS, AGC, A/D converter

φ3B

Vφ3A

Vφ2

Vφ1B

Vφ1A

GND

VOUT

Vφ4

2. IC903 (CCD)

[Structure]

Interline type CCD image sensor

Optical size 1/2.7 inch format

Effective pixels 1292 (H) ×966 (V) Pixels in total 1344 (H) ×971 (V)

Optical black

Horizontal (H) direction: Front 3 pixels, Rear 49 pixels Vertical (V) direction: Front 2 pixels, Rear 3 pixels

Dummy bit number Horizontal : 28 Vertical : 2

Pin 1

Pin 9

Cy Mg Cy Mg Cy Mg

φRG

Mg Cy

（Note）

Hφ

Vertical register

Horizontal register



φSUB

GND

（Note）:Photo sensor

Fig. 1-2. CCD Block Diagram

Fig. 1-1.Optical Black Location (Top View)

Pin No.

2, 3

5, 6

7, 10

Symbol

V φ

3B, V φ3A

V φ2

V φ1B, V φ1A

GND

OUT

VDD

φSUB

φRG

H φ

H φ2

Pin Description

Vertical register transfer clock

GND

Signal output

Circuit power

Substrate clock

Protection transistor bias

Reset gate clock

Horizontal register transfer clock

Waveform

GND

Table 1-1. CCD Pin Description

Voltage

-7 V, 0 V

-7 V, 0 V, 13 V

-7 V, 0 V

-7 V, 0 V, 13 V

0 V

Aprox. 6 V

13 V Aprox. 6 V

(Different from every CCD)

-7V

8 V, 11.5 V

0 V, 3.5 V

When sensor read-out

−2 −

3. IC902 (H Driver) and IC904 (V Driver)

2319

PBLK

A/D

ACVDD

CMLEVEL

VRT

VTB

STBY CLPOB

ADCMODE

TIMING

GENERATOR

CLPDM PGACONT1

PGACONT2

SHP

SHD ADCCLK

DIN

ADCIN

DOUT

DRVDD

DVDD

ADVDD

37 20

3341

CLAMP

REFERENCE

CLAMP

CDS

PGA

MUX S/H

AD9802

An H driver (IC902) and V driver (IC904) are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. IC902 is an inverter IC which drives the horizontal CCDs (H1 and H2). In addition the XV1-XV4 signals which are output from IC102 are the vertical transfer clocks, and the XSG1 and XSG signal which is output from IC102 is superimposed onto XV1 and XV3 at IC904 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the electronic shutter, and the RG signal which is output from IC102 is the reset gate clock.

4. IC905 (CDS, AGC Circuit and A/D Converter)

The video signal which is output from the CCD is input to Pins (26) and (27) of IC905. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that CDS (correlated double sampling) is carried out. After passing through the CDS circuit, the signal passes through the AGC amplifier. It is A/C converted internally into a 10-bit signal, and is then input to IC102 of the CA2 circuit board. The gain of the AGC amplifier is controlled by the voltage at pin (29) which is output from IC102 of the CA2 circuit board and smoothed by the PWM.

GND

Fig. 1-3. IC902 Block Diagram

VSHT

VMb

V3B

V3A

MIX

Fig. 1-5. IC905 Block Diagram

VOFDH

XSG2B

XSUB

XV2

XV1

XSG1A

XV3

VDD

V1B

V1A

VMa

MIX

Fig. 1-4. IC904 Block Diagram

−3 −

GND

XSG2A

XV4

XSG1B

5. Transfer of Electric Charge by the Horizontal CCD

The transfer system for the horizontal CCD emplays a 2-phase drive method. The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-6. RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the timing in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the timing in (3), and the electric charge now moves to the floating diffusion. Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep. Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7.

(1)

H1 H2 H1 H2 H1 HOG RG

CCD OUT

Floating diffusion

(2)

H1 H2 H1 H2 H1 HOG RG

CCD OUT

(1) (2) (3)

3.5V

15.5V

12V

(3)

H1 H2 H1 H2 H1 HOG RG

Reset gate pulse

Direction of transfer

H Register

Electric charge

Floating diffusion gate is floated at a high impedance.

CCD OUT

Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage

6. Lens drive block

6-1. Shutter drive

The shutter drive circuit (PCTRL) which is output from the ASIC expansion port (IC109) is drived the shutter drive circuit, and then shutter plunger opened and closed.

6-2. Iris and focus drive

The stepping motor drive signal (IN1, IN2 and ENA) for using both iris and focus which is output from the ASIC expansion port (IC109) is drived by motor driver (LB1838M). Detection of the standard motoring positions is carried out by means of the photointerruptor (PI) inside the lens block.

C is charged equivalently

13V Pre-charge drain bias (PD)

Voltage output

RG pulse peak signal

Signal voltage

Black level

Fig. 1-7. Theory of Signal Extraction Operation

−4 −

1-2. CA2 CIRCUIT DESCRIPTION

1. Circuit Description 1-1. Digital clamp

The optical black section of the CCD extracts averaged values from the subsequent data to make the black level of the CCD output data uniform for each line. The optical black section of the CCD averaged value for each line is taken as the sum of the value for the previous line multiplied by the coefficient k and the value for the current line multiplied by the coefficient 1-k.

1-2. Signal processor

1. γ correction circui t

This circuit performs (gamma) correction in order to maintain a linear relationship between the light input to the camera and the light output from the picture screen.

2. Color generation circuit

This circuit converts the CCD data into RGB signals.

3. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y signals from the RGB signals.

4. Horizontal and vertical ape rture circuit

This circuit is used gemerate the aperture signal.

1-3. AE/AWB and AF computing circuit

The AE/AWB carries out computation based on a 64-segment screen, and the AF carries out computations based on a 6-segment screen.

1-4. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for controlling the SDRAM. It also refreshes the SDRAM.

1-5. Communication control

1. UART

The RS-232C can be sued for both synchronous and asynchronous transmission.

2. SIO

This is the interface for the 4-bit microprocessor.

3. PIO/PWM/SIO for LCD

8-bit parallel input and output makes it possible to switch between individual input/output and PWM input/output.

1-6. TG/SG

Timing generated for 1.3 million/1.09 million pixel CCD control.

1-7. Digital encorder

It generates chroma signal from color difference signal.

2. Outline of Operation

When the shutter opens, the reset signals (ASIC and CPU) and the serial signals (“take a picture” commands) from the 4-bit microprocessor are input and operation starts. When the TG/SG drives the CCD, picture data passes through the A/D and CDS, and is then input to the ASIC as 10-bit data. The AF, AE, AWB, shutter, and AGC value are computed from this data, and three exposures are made to obtain the optimum picture. The data which has already been stored in the SDRAM is read by the CPU and color generation is carried out. Each pixel is interpolated from the surrounding data as being either Ye, Cy, Mg and Gr primary color data to produce R, G and B data. At this time, correction of the lens distortion which is a characteristic of wide-angle lenses is carried out.

After AWB and γprocessing are carried out, a matrix is gen-

erated and aperture correction is carried out, and the data is then compressed by the JPEG method by (JPEG) and is then written to card memory (smart media). When the data is to be output to an external device, it is taken data from the memory and output via the UART. When played back on the LCD and monitor, data is transferred from memery to the SDRAM, and is displayed over the SDRAM display area.

3. LCD Block

During monitoring, YUV conversion is carried out for the 10bit CCD data which is input from the A/D conversion block to the ASIC and is then transferred to the DRAM so that the CCD data can be displayed on the LCD. The data which has accumulated in the DRAM is passed through the NTSC encoder , and after D/A conversion is carried out to change the data into a Y/C signal, the data is sent to the LCD panel and displayed. If the shutter button is pressed in this condition, the 10-bit data which is output from the A/D conversion block of the CCD is sent to the DRAM (DMA transfer), and after processor, it is displayed on the LCD as a freeze-frame image. During playback, the JPEG image data which has accumulated in the flash memory is converted to YUV signals, and then in the same way as during monitoring, it is passed through the NTSC endoder, and after D/A conversion is carried out to change the data into a Y/C signal, the data is sent to the LCD panel and displayed. The two analog signal (Y/C signals) from the ASIC are converted into RGB signals by the LCD driver, and these RGB signals and control signal which output from the LCD driver are used to drive the LCD panel. The RGB signals are 1H transposed so that no DC component is present in the LCD element, and the two horizontal shift register clocks drive the horizontal shift registers inside the LCD panel so that the 1H transposed RGB signals are applied to the LCD panel. Because the LCD closes more as the difference in potential between the COM (common polar voltage: fixed at DC) and the R, G and B signals becomes greater, the display becomes darker; if the difference in potential is smaller, the element opens and the LCD become brighter.

−5−

1-3. PW1 POWER CIRCUIT DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the following blocks. Switching controller (IC501) Digital 5 V and analog system power output (Q5001, T5001) Digital 3.5 V system power supply (Q5007) Digital 2.6 V system power output (IC503) LCD system power supply (Q5008, T5002) Backlight power supply output (Q5011, T5003)

2. Switching Controller (IC501)

This is the basic circuit which is necessary for controlling the power supply for a PWM-type switching regulator, and is provided with four built-in channels, only CH1 (digital 5 V, analog system), CH3 (LCD system), CH2 (digital 3.5 V) and CH4 (backlight) are used. Feedback from 5 V (D) (CH1), 3.2 V (D) (CH2) , 5.0 V (L) (CH3) and 7.7 V (L) (CH4) power supply outputs are received, and the PWM duty is varied so that each one is maintained at the correct voltage setting level.

2-1. Short-circuit protection circuit

If output is short-circuited for the length of time determined by the condenser which is connected to Pin (17) of IC501, all output is turned off. The control signal (P ON, P(A) ON and LCD ON) are recontrolled to restore output.

3. Digital 5 V and Analog System Power Output

5 V (D) , 13 V (A), -7.0 V (A) and 5 V (A) are output. Feedback for the 5 V (D) is provided to the switching controller (Pins (28) and (29) of IC501) so that PWM control can be carried out.

4. Digital 3.5 V System Power Output

3.5 V (D) is output. Feedback is provided to the swiching controller (Pin (25) and (26) of IC501) so that PWM control can be carried out.

5. Digital 2.6 V Power Output

2.6 V (D) is output. 2.6 V (D) can be controled regular voltage by series regulator IC (IC503).

6. LCD System Power Output

5 V (L) 1, 5 V (L) 2, 7.5 V (L), 13.5 V (L) and -15 V (L) are output. Feedback for the 5 V (L) is provided to the switching controller (Pin (11) and (12) of IC501) so that PWM control can be carried out.

7. Backlight Power Supply output

7.7 V (L) is output. Feedback is sent to pins (7) and (8) of the switching controller (IC501) for PWM control to be carried out.

−6−

1-4. PW1 STROBE CIRCUIT DESCRIPTION

1. Charging Circuit

When UNREG power is supplied to the charge circuit and the CHG signal becomes High (3.3 V), the charging circuit starts operating and the main electorolytic capacitor is charged with high-voltage direct current. However, when the CHG signal is Low (0 V), the charging circuit does not operate.

1-1. Power switch

When the CHG signal switches to Hi, Q5406 turns ON and the charging circuit starts operating.

1-2. Power supply filter

L5401 and C5401 constitute the power supply filter. They smooth out ripples in the current which accompany the switching of the oscillation transformer.

1-3. Oscillation circuit

This circuit generates an AC voltage (pulse) in order to increase the UNREG power supply voltage when drops in current occur. This circuit generates a drive pulse with a frequency of approximately 50-100 kHz. Because self-excited light omission is used, the oscillation frequency changes according to the drive conditions.

2. Light Emission Circuit

When RDY and TRIG signals are input from the ASIC expansion port, the stroboscope emits light.

2-1. Emission control circuit

When the RDY signal is input to the emission control circuit, Q5409 switches on and preparation is made to let current flow to the light emitting element. Moreover, when a STOP signal is input, the stroboscope stops emitting light.

2-2. Trigger circuit

When a TRIG signal is input to the trigger circuit, D5405 switches on, a high-voltage pulse of several kilovolts is generated inside the trigger circuit, and this pulse is then applied to the light emitting part.

2-3. Light emitting element

When the high-voltage pulse form the trigger circuit is applied to the light emitting part, currnet flows to the light emitting element and light is emitted.

※ Beware of electric shocks.

1-4. Oscillation transformer

The low-voltage alternating current which is generated by the oscillation control circuit is converted to a high-voltage alternating current by the oscillation transformer.

1-5. Rectifier circuit

The high-voltage alternating current which is generated at the secondary side of T5401 is rectified to produce a highvoltage direct current and is accumulated at electrolytic capacitor C5412 on the main circuit board.

1-6. Voltage monitoring circuit

This circuit is used to maintain the voltage accumulated at C5412 at a constance level. After the charging voltage is divided and converted to a lower voltage by R5417 and R5419, it is output to the SY1 circuit board as the monitoring voltage VMONIT. When this VMONIT voltage reaches a specified level at the SY1 circuit board, the CHG signal is switched to Low and charging is interrupted.

−7−

1-5. SY1 CIRCUIT DESCRIPTION

1. Configuration and Functions

For the overall configuration of the SY1 circuit board, refer to the block diagram. The configuration of the SY1 circuit board centers around a 4-bit microprocessor (IC301). The 4-bit microprocessor handles the following functions.

1. Operation key input, 2. Mode LCD display, 3. Clock control, 4. Power ON/OFF, 5. Storobe charge control

34~37

39~41

42~44

45~47

48~61

62~64

Signal

SCAN OUT3

LCD ON 2

P(A) ON

P ON

CHG ON

ASIC TEST

MAIN RESET

ASIC RESET

STBY (R) LED

STBY (G) LED

SELF LED

LCD ON 1

AD ON

RXD

SCK

S. REQ

DIN CONNECT

BAT OFF

RESET

XIN

XOUT

VSS

VDD

XCOUT

XCIN

AVSS

VREF

BATTERY

CHG VOL

AV JACK

CARD

SCAN IN 0~3

VLC3

NOT USED

COM3~COM1

NOT USED

S14~S1

SCAN OUT 0~2

I/O

Table 4-1. 4-bit Microprocessor Port Specification

Key matrix output 3

LCD monitor ON/OFF signal (2) L : ON

DC/DC converter (analog) ON/OFF signal L : ON

DC/DC converter (digital) ON/OFF signal L : ON

Flash charge ON/OFF signal L : ON

ASIC reset control signal

SPARC reset signal L : Reset output

ASIC reset signal L : Reset output

Standby LED (red) ON/OFF signal L : LED light

Standby LED (green) ON/OFF signal L : LED light

Self-timer LED ON/OFF signal L : LED light

LCD monitor ON/OFF signal (1) L : ON

AD converter power ON/OFF signal L : ON

RS-232C RXD input terminal

Serial clock output ( → ASIC) Serial data output ( → ASIC) Serial data input ( ← ASIC)

Serial communication request singnal L : Serial request

DIN jack connection detection signal H : Connection

Battery OFF detection signal L : OFF

Reset input

Main clock oscillation terminal (1 MHz)

Main clock oscillation terminal

GND

VDD

Clock oscillation terminal (32.768 kHz)

Clock oscillation terminal

Analog GND input terminal

Analog reference voltage input terminal

Battery voltage input (AD input)

Strobe charge voltage input (AD input)

AV output cable connection detection signal L : Connection

Memory card attachment detection signal L : Attachment

Key matrix input 0~3

Mode LCD power input terminal

LCD common output

Mode LCD segment output

Key matrix output 0~2

Outline

−8−

2. Internal Communication Bus

The SY1 circuit board carries out overall control of camera operation by detecting the input from the keyboard and the condition of the camera circuits. The 4-bit microprocessor reads the signals from each sensor element as input data and outputs this data to the camera circuits (ASIC) or to the LCD display device as operation mode setting data. Fig. 4-1 shows the internal communication between the 4-bit microprocessor, ASIC and SPARC lite circuits.

RESET

S. REQ

4-bit

Microprocessor

ASIC SO

ASIC SI

ASIC SCK

RESET

Fig. 4-1 Internal Bus Communication System

3. Key Operaiton

For details of the key operation, refer to the instruction manual.

SCAN

SCAN OUT

TEST

PLAY/CAMERA

SPECIAL

LENS COVER

BARRIER

MODE

SET

CARD LID

FLASH

SHUTTER 2nd

ASIC

DATA BUS

IMAGE

MONITOR

SHUTTER 1st

32-bit

SPARC lite

Table 4-2. Key Operation

−9−

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