SANYO VPC-S3 Service Manual 00-18
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CP1 CIRCUIT DESCRIPTION
1. IC Configuration
IC903 (RJ23P3AB0DT) CCD imager
IC901 (LR36688U) V driver
IC906 (AD9948) H driver, CDS, AGC and A/D converter
2. IC903 (CCD imager)
[Structure]
Interline type CCD image sensor
Image size Diagonal 6.67 mm (1/2.7 type)
Pixels in total 2152 (H) x 1567 (V)
Recording pixels 2048 (H) x 1536 (V)
Pin No.
1
2
3
4
5
6
7
8
9
10
Symbol
OD
GND
OFD
PW
ø
RS
NC
OOFD
øH1
øH2
øV5A
Output transistor drain
GND
Overflow drain
P well
Reset transistor clock
NC
Overflow drain output
Horizontal shift register clock
Horizontal shift register clock
Vertical shift register clock
Pin Description
Pin No.
11
12
13
14
15
16
17
18
19
20
20
1
GND
19
G
R
G
R
G
Vertical CCD
R
2
GND
18
ØV5B
3
OFD
17
16
B
G
B
G
B
G
Horizontal CCD
4
PW
G
R
G
R
G
R
5
ØRS
OS
OD
ØV1A
ØV6
Fig. 1-1. CCD Block Diagram
Symbol
ø
V4
øV3B
øV3A
øV2
øV1B
øV1A
øV6
øV5B
GND
OS
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
Vertical shift register clock
GND
Video output
ØV1B
ØV2
14
15
B
G
G
R
B
G
G
R
B
G
G
R
7
6
NC
OOFD
(Note) : Photo diode
13
ØV3A
8
ØH1
ØV3B
12
B
G
B
G
B
(Note)
G
9
ØH2
Pin Description
ØV4
11
10
ØV5A
Table 1-1. CCD Pin Description
– 2 –
3. IC901 (V Driver)
V driver is necessary in order to generate the clocks (vertical
transfer clock, horizontal transfer clock and electronic shutter
clock) which driver the CCD.
IC901 is V driver. In addition the XV1-XV4 signals which are
output from IC101 are the vertical transfer clocks, and the
XSG signal which is output from IC102 is superimposed onto
XV1, XV3 and XV5 at IC901 in order to generate a ternary
pulse. In addition, the XSUB signal which is output from IC101
is used as the sweep pulse for the electronic shutter.
4. IC906 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(27) of IC906. There are inside the sampling hold block, AGC
block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (32). The video signal is carried out
A/D converter, and is output by 10-bit.
5. Lens drive block
5-1. Shutter drive
The shutter drive signal (SIN1 and SIN2) which is output from
the ASIC expansion port (IC106) is drived the shutter constant
level driver (IC951), and then shutter plunger is opened and
closed.
5-2. Iris drive
The iris stepping motor drive signals (IIN1 and IIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951).
5-3. Focus drive
The focus stepping motor drive signals (FIN1, FIN2, FIN3 and
FIN4) which are output from the ASIC (IC101) are used to
drive by the motor driver (IC951). Detection of the standard
focusing positions is carried out by means of the
photointerruptor (FPI-E) inside the lens block.
CCDIN
RG
H1-H4
VRT
VREF
2~36 dB
VGA
PxGA
CDS
HORIZONTAL
4
DRIVERS
CLAMP
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
VD
HD
Fig. 1-2. IC906 Block Diagram
VRB
ADC
CLAMP
REGISTERS
SL
INTERNAL
SCK
10
SDATA
DOUT
CLI
5-4. Zoom drive
The zoom DC motor drive signals (ZIN1 and ZIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951). Detection of the zoom positions is carried out
by means of photoreflector (ZPI-E) inside the lens block.
– 3 –
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