SANYO VPC-R1EX, VPC-R1E, VPC-R1, VPC-R1G, VAR-G5U OUTLINE OF CIRCUIT DESCRIPTION

1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CA-A CIRCUIT DESCRIPTIONS

Around CCD block

1. IC Configuration

IC903 (RJ24J1AA0PT) CCD imager
IC902 (TC74VHC04FTP) H driver
IC904 (LR366854) V driver
IC905 (AD9806KST) CDS, AGC, A/D converter

PI4

PI3

(NC)

3 2 1 21

4

(NC)

(NC)

2324

(NC)

22

PI2

PI1

2. IC905 (CCD)

[Structure]

Frame transfer type CCD image sensor

Optical size 1/2.8 type
Effective pixels 1300 (H) x 980 (V)
Pixels in total 1353 (H) x 1006 (V)
Optical black

Horizontal (H) direction: left 2 pixels, right 51 pixels
Vertical (V) direction: upper 10 pixels, below 12 pixels

Dummy bit number Horizontal : 20 Vertical : 4

10

V

12

2

Fig. 1-1.Optical Black Location (Top View)

Pin No. Symbol

1, 2, 23, 24

NC

H

Pin Description

-

51

PS1

5

PS2

6

7

VPW

8

VOUT

9

Waveform

(LCC24
Top View)

10

11 12 16

PR

VSS

VDD

VRD

PH4

151413

PH1

Fig. 1-2. CCD Terminal Name

Voltage

PH2

20

19

18

17

PH3

PS3

PS4

NSUB

VOG

3, 4

5, 6

7

8

9

10

11

12

13, 15
14, 16

17

18

19, 20

PI3, PI4

PS1, PS2

PW

VOUT

VDD

VSS GND

VRD

PR

PH4, PH2

PH1, PH3

VOG

VSUB

PS4, PS3

21, 22 PI1, PI2

Image clock

Accumulation clock

P well

CCD output

Power

Reset drain

Reset gate

Horizontal register clock

CCD output gate

N substrate

Accumulation clock

Image clock

Table 1-1. CCD Pin Description

Frame shift

Frame shift

Line sending

Frame shift

Line sending

Frame shift

DC

DC

DC

DC

DC

DC

0~12 V

0~12 V

8 V

Approx. 13 V

20 V

0 V

20 V

L=18 V, H=23 V

L=2.5 V, H=7.5 V

L=0 V, H=5 V

3.3 V

L=26 V, H=29 V

0~12 V

0~12 V

– 2 –

3. IC903 (H Driver) and IC902 (V Driver)

An H driver (IC903) and V driver (IC902) are necessary in
order to generate the clocks (vertical transfer clock, horizon­tal transfer clock and electronic shutter clock) which driver
the CCD.
IC902 is an inverter IC which drives the horizontal CCDs (H1
and H2). In addition the VREG 0~7, VXREG2 and VXREG3
signals which are output from IC102 are the vertical transfer
clocks. The clock is drived until peak value which necessary
CCD at IC902.

14

CC

1A

1Y

2A

2Y

3A

3Y

GND

1

2

3

4

5

6

7

V

13

6A

12

6Y

11

5A

10

5Y

4A

9

4Y

8

4. IC901 (CDS, AGC Circuit and A/D Converter)

The video signal which is output from the CCD is input to
Pins (26) and (27) of IC901. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102.

SHD ADCCLK

22

21

GENERATOR

16

TIMING

A/D

AD9802

3341

ACVDD

ADVDD

43

10

2

DOUT

11

DRVDD

12

DVDD

17

PIN

DIN

ADCIN

PBLK

CLPDM SHP

CLAMP

27

26

CDS

29

2319

PGA

36

CLAMP

REFERENCE

48

37 20

CMLEVEL

VRT

47

VTB

STBY CLPOB

18

Fig. 1-5. IC901 Block Diagram

30

MUX S/H

ADCMODE

Fig. 1-3. IC903 Block Diagram

GND

1

OUT_1

2

OUT_2

3

OUT_3

4

OUT_4

5

OUT_5

6

OUT_6

7

OUT_7

8

OUT_8

9

OUT_9

10

OUT_10

OUT_NSUB

CAP5V

CAPNS

GND

11

12

13

14

15

Power circuit

OCNT circuit
DUTY circuit

OCNT circuit

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VDD

OCNT

DUTY

IN_1

IN_2

IN_3

IN_4

IN_5

IN_6

IN_7

IN_8

IN_9

IN_10

IN_NSUB

VDD

Fig. 1-4. IC902 Block Diagram

– 3 –