Ordering number : ENN6507
22002TN (OT) No. 6507-1/17
Overview
The STK672-080 is a stepping motor driver hybrid IC that
uses power MOSFETs in the output stage. It includes a
built-in microstepping controller and is based on a
unipolar constant-current PWM system. The STK672-080
supports application simplification and standardization by
providing a built-in 4 phase distribution stepping motor
controller. It supports five excitation methods: 2 phase,
1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase
excitations, and can provide control of the basic stepping
angle of the stepping motor divided into 1/16 step units. It
also allows the motor speed to be controlled with only a
clock signal.
The use of this hybrid IC allows designers to implement
systems that provide high motor torques, low vibration
levels, low noise, fast response, and high-efficiency drive.
Compared to the earlier SANYO STK672-050, the
STK672-080 features a significantly smaller package for
easier mounting in end products.
Applications
• Facsimile stepping motor drive (send and receive)
• Paper feed and optical system stepping motor drive in
copiers
• Laser printer drum drive
• Printer carriage stepping motor drive
• X-Y plotter pen drive
• Industrial robots and other stepping motor applications
Features
• Can implement stepping motor drive systems simply by
providing a DC power supply and a clock pulse
generator.
<Control Block Features>
• One of five drive types can be selected with the drive
mode settings (M1, M2, and M3)
—2 phase excitation drive
—1-2 phase excitation drive
—W1-2 phase excitation drive
—2W1-2 phase excitation drive
—4W1-2 phase excitation drive
• Phase retention even if excitation is switched.
• The MOI phase origin monitor pin is provided.
• The CLK input counter block can be selected to be one of
the following by the high/low setting of the M3 input pin.
—Rising edge only
—Both rising and falling edges
Note*: Conditions: VCC1 = 24 V, IOH= 2.0 A, 2W1-2
drive used.
Continued on next page.
Package Dimensions
unit: mm
4186
1
15
46.6
41.2
12.7
25.5
(6.6)
14
×
2.0=28
3.6
0.5
2.0
8.5
4.0
0.4
2.9
1.0
[STK672-080]
STK672-080
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Stepping Motor Driver (Sine Wave Drive) Output Current: 2.8 A (No Heat Sink*)
Unipolar constant-current chopper (external excitation PWM) circuit with built-in microstepping controller
Thick-Film Hybrid IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
• The CLK input pin include built-in malfunction
prevention circuits for external pulse noise.
• ENABLE and RESET pins provided. These are Schmitt
trigger inputs with built-in 20 kΩ (typical) pull-up
resistors.
• No noise generation due to the difference between the A
and B phase time constants during motor hold since
external excitation is used.
• Microstepping operation supported even for small motor
currents, since the reference voltage Vref can be set to
any value between 0 V and 1/2 VCC2.
<Driver Block>
• External excitation PWM drive allows a wide operating
supply voltage range (VCC1 = 10 to 45 V) to be used.
• Current detection resistor (0.15 Ω) built into the hybrid
IC.
• Power MOSFETs for minimal driver loss
• Motor output drive currents IOHup to 2.8 A (When Tc =
105°C).
No. 6507-2/17
STK672-080
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage1 V
CC
1 max No signal 52 V
Maximum supply voltage2 V
CC
2 max No signal –0.3 to +7.0 V
Input voltage V
IN
max Logic input pins –0.3 to +7.0 V
Phase output current I
OH
max 0.5 seconds, single pulse, with VCC1 applied. 3.3 A
Repeatable avalanche current Ear max 30 mJ
Power loss Pd max
θc-a = 0 8 W
Operating substrate temperature Tc max 105 °C
Junction temperature Tj max 150 °C
Storage temperature Tstg –40 to +125 °C
Specifications
Absolute Maximum Ratings at Tc = 25°C
Parameter Symbol Conditions Ratings Unit
Supply voltage1 V
CC
1 With input signals present 10 to 45 V
Supply voltage2 V
CC
2 With input signals present 5 ±5% V
Input voltage V
IH
0 to VCC2 V
Phase driver voltage handling V
DSS
Tr1, 2, 3, and 4 (the A, A, B, and B outputs) 100 (min) V
Phase current 1 I
OH
1 Tc = 105°C, CLK ≥ 200 Hz 2.8 A
Phase current 2 I
OH
2 Tc = 80°C, CLK ≥ 200 Hz 3 A
Allowable Operating Ranges at Ta = 25°C
Parameter Symbol Conditions
Ratings
Unit
min typ max
Control supply current I
CC
Pin 6 input, with ENABLE pin held low. 2.1 14 mA
Output saturation voltage Vsat R
L
= 12 Ω 0.65 1 V
Average output current Io ave Load: R = 3.5 W/L = 3.8 mH per phase 0.445 0.5 0.56 A
FET diode Forward voltage Vdf If = 1 A 1 1.5 V
[Control Inputs]
Input voltage
V
IH
Except for the Vref pin 4 V
V
IL
Except for the Vref pin 1 V
Input current
I
IH
Except for the Vref pin 0 1 10 µA
I
IL
Except for the Vref pin 125 250 510 µA
[Vref Input Pin]
Input voltage V
I
Pin 7 0 2.5 V
Input current I
I
Pin 7, 2.5-V input 330 415 545 µA
[Control Outputs]
Output voltage
V
OH
I = –3 mA, pin MOI 2.4 V
V
OL
I = +3 mA, pin MOI 0.4 V
Electrical Characteristics at Tc = 25°C, VCC1 = 24 V, VCC2 = 5 V
Continued on next page.
Continued from preceding page.
No. 6507-3/17
STK672-080
Parameter Symbol Conditions
Ratings
Unit
min typ max
[Current Distribution Ratio (A·B)]
2W1-2, W1-2, 1-2 Vref θ = 1/8 100 %
2W1-2, W1-2 Vref θ = 2/8 92 %
2W1-2 Vref θ = 3/8 83 %
2W1-2, W1-2, 1-2 Vref θ = 4/8 71 %
2W1-2 Vref θ = 5/8 55 %
2W1-2, W1-2 Vref θ = 6/8 40 %
2W1-2 Vref θ = 7/8 21 %
2 Vref 100 %
PWM frequency fc 37 47 57 kHz
Continued from preceding page.
Note: A constant-voltage power supply must be used.
The design target value is shown for the current distribution ratio.
14
13
15
12
11
10
9
8
6 7 5 4 3 2
+
+
–
–
1
M1
M2
CWB
CLOCK
Excitation mode
control
Excitation state monitor
CR oscillator PWM control
Phase
advance
counter
Current
distribution
ratio switching
Phase excitation drive
signal generation
Reference clock
generation
Pseudo-sine
wave generator
Raising edge/falling edge
detection and switching
M3
RESET
MoI
ENABLE
SUB
PG
BBBABAVref
V
CC
2
A13256
Internal Block Diagram
No. 6507-4/17
STK672-080
Test Circuit Diagrams
No. 6507-5/17
STK672-080
11
8
9
7
13
1
2
3
4
5
A
RL
AB
B
BB
6
+
VCC2
VCC2
STK672-080
Start
Vref=2.5V
V
1
2
3
4
5
A
AB
B
BB
6
VCC1
STK672-080
V
A
A13257
A13258
Vsat Vdf
IIH, I
IL
loave, Icc, fc
To measuring Io ave: With SW1 set to the b position, input Vref and switch SW2.
To measuring fc: With SW1 set to the a position, set Vref to 0 V, and switch SW3.
To measuring Icc: Set the ENABLE pin low.
+
Start
11
8
9
7
13
1
2
3
4
5
A
a
b
a
b
AB
B
SW2
SW3
SW1
BB
6
15
VCC2
Vref
ENABLE
VCC1
VCC1
STK672-080
A13260
8
1
6
A
A
2.5V
VCC2
M1
STK672-080
A13259
9
M2
12
M3
11
CLK
10
CWB
14
13
RESET
15
ENABLE
7
Vref
A
A
fc
I
IL
I
IH
No. 6507-6/17
STK672-080
7
5
A
Two-phase stepping motor
AB
6
14148
14149
141412
15
11
13
10
14
+
+
VCC2=5V
VCC2=5V
SG
100µF or higher
PG
Vref
Ro1
Ro2
VCC2=5V
CLK
ENABLE
CBW
Vf ≈ 0.3V
RESET
MoI
VCC1=10V to 45V
STK672-080
A13261
B
BB
RoX
4
3
2
1
Ioave
IOLI
OH
0A
Motor current waveform
A13262
Simplified power-on reset circuit
(This circuit cannot be used to detect
drops in the power-supply voltage.)
Always perform a power-on reset operation when the V
CC
2 supply voltage is first applied to this hybrid IC.
A value of about 100 Ω is recommended for
R
O
2 to minimize the influence of the Vref
pin internal impedance, which is 6 kΩ.
R
O
X: The input impedance is 6 kΩ ±30%.
Functional Description
2W1-2 Phase Excitation Drive (microstepping operation)
[Setting the Motor Current]
The motor current IOHis set by the Vref voltage on the hybrid IC pin 7. The following formula gives the relationship
between IOHand Vref.
ROX = (RO2 × 6 kΩ) ÷ (RO2 + 6 kΩ)·············(1)
Vref = VCC2 × ROX ÷ (RO1 + ROX) ··············(2)
1 Vref
IOH= — × ——·············································(3)
k R
S
K: 4.7 (Voltage division ratio), Rs: 0.15 Ω (The hybrid IC’s internal current detection resistor (precision: ±3%)
Applications can use motor currents from the current (0.05 to 0.1 A) set by the duty of the frequency set by the oscillator
up to the limit of the allowable operating range, IOH= 2.8 A
[Function Table]
M2 0 0 1 1
M1
0 1 0 1
Phase switching clock edge timing
M3
1 2 phase excitation 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation Rising edge only
0 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation 4W1-2 phase excitation Rising and falling edges
Forward Reverse
CWB 0 1
ENABLE Motor current is cut off when low
RESET Active low
No. 6507-7/17
STK672-080
D1
Rs
L2
VCC1
I
OFF
L1
MOSFET
Enable
Divider
Latch circuit
CR
oscillator
Current
divider
Noise
filter
ØA (control signal)
AND
Q
S
R
800kHz
45kHz
Vref
A=1
–
+
I
ON
A13263
Functional Description
External Excitation Chopper Drive Block Description
Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required.
When a high level is input to øA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the
comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be
input, the Q output will go high, and the MOSFET will be turned on as its initial value.
The current IONflowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs
potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will
invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the
current I
OFF
will be regenerated to the power supply. This state will be maintained until the time when an input to the
latch circuit set pin occurs.
In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant
current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize
with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the
same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when
the motor is locked.
Driver Block Basic Circuit Structure
Input Pin Functions
Pin No. Symbol Function Pin circuit type
11 CLK Phase switching clock Built-in pull-up resistor CMOS Schmitt trigger input
10 CWB Rotation direction setting (CW/CCW) Built-in pull-up resistor CMOS Schmitt trigger input
15 ENABLE Output cutoff Built-in pull-up resistor CMOS Schmitt trigger input
8, 9, 12 M1, M2, M3 Excitation mode setting Built-in pull-up resistor CMOS Schmitt trigger input
13 RESET System reset Built-in pull-up resistor CMOS Schmitt trigger input
7 Vref Current setting Input impedance 6 kΩ (typ.) ±30%
Input Signal Functions and Timing
• CLK (phase switching clock)
Input frequency range: DC to 50 kHz
Minimum pulse width: 10 µs
Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Built-in multi-stage noise rejection circuit
Function
—When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge.
—When M3 is low: The phase moves on both the rising and falling edges of the CLK signal, for a total of two steps
per cycle.
• CWB (Method for setting the rotation direction)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Function
—When CWB is high: The motor turns in the clockwise direction.
—When CWB is low: The motor turns in the counterclockwise direction.
Notes: When M3 is low, the CWB input must not be changed for about 6.25 µs before or after a rising or falling edge
on the CLK input.
• ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold
as the internal state of this hybrid IC.)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Function
—When ENABLE is high or open: Normal operating state
—When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly
turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the
reset input have any effect on the hybrid IC state.
CLK Input Acquisition Timing (M3 = Low)
No. 6507-8/17
STK672-080
CLK input
System clock
Phase excitation counter clock
Control output timing
Excitation counter up/down
Control output switching timing
A13264
No. 6507-9/17
STK672-080
Output Pin Functions
Pin No. Symbol Function Pin circuit type
14 MoI Phase excitation monitor Standard CMOS structure
• M1, M2, and M3 (Excitation mode and CLK input edge timing selection)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Valid mode setting timing: Applications must not change the mode in the period 5 µs before or after a CLK signal rising
or falling edge.
Mode Setting Acquisition Timing
M2 0 0 1 1
M1
0 1 0 1
Phase switching clock edge timing
M3
1 2 phase excitation 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation Rising edge only
0 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation 4W1-2 phase excitation Rising and falling edges
Function:
• RESET (Resets all parts of the system.)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Function
—All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at
least 10 µs.)
At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to
about 71% after the reset is released.
Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must
apply a power on reset when the VCC2 power supply is first applied.
• Vref (Sets the current level used as the reference for constant-current detection.)
Pin circuit type: Analog input structure
Function
—Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a
voltage less than the control system power supply voltage VCC2 minus 2.5 V.
—Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5 V as the
upper limit.
Output Signal Functions and Timing
• A, A, B, and B (Motor phase excitation outputs)
Function
—In the 4 phase and 2 phase excitation modes, a 3.75 µs (typical) interval is set up between the A and A and B and B
output signal transition times.
CLK input
System clock
Mode setting
Mode switching clock
Hybrid IC internal setting state
Phase excitation clock
M1 to M3
Mode switching timing
Excitation counter up/down
A13265
Phase States During Excitation Switching
• Excitation phases before and after excitation mode switching <clockwise direction>
No. 6507-10/17
STK672-080
B24 24
27
28
31
3
4
5
8
11
12
15
16
19
20
25
A
A
A
0
16
17
1
A
A
B
B
B 24
25
26
27
28
29
30
31 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1617
18
19
20
21
24
26
28
30
0
2
4
6
8
10
12
14
16
18
20
22
22
23
A
A
B
B
8
9
12
4
28
20
20
24
28
0
4
8
12
16
B24
26
28
30
A
A
A
0
16
18
20
22
24
28
0
4
8
12
16
20
20
28
4
12
20
28
4
0
12
16
16
18
20
22
24
25
27
29
31 1
3
5
7
923
22
8
24
20 10
26
18
12
16
14
28
30
6
4
2
0
1121
1319
1517
24
28
0
4
8
12
16
20
26
28
30
0
2
4
6
8
10
12
14
2
4
6
B
B
A
B
A
B
30 2
26 6
10
14
22
18
A
B
A
B
A
B
A
B
B
A
A
B
B
8
10
12
14
12
4
28
20
2W1-2 phase → 2 phase
W1-2 phase → 2 phase
1-2 phase → 2 phase
2 phase → 1-2 phase
Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 to M2)
Excitation phase immediately before setting the excitation mode
2W1-2 phase → 1-2 phase
W1-2 phase → 1-2 phase
1-2 phase → W1-2 phase
2 phase → W1-2 phase 2 phase → 2W1-2 phase
2W1-2 phase → W1-2 phase
W1-2 phase → 2W1-2 phase
1-2 phase → 2W1-2 phase
24
0
8
16
20
22
30
28 4
1220
14
6
28
4
12
A
B
A
B
29
1
25
5
9
13
21
24
28
0
4
8
12
16
20
17
A
B
A
B
29
5
13
21
28204
12
17
A
B
A
B
A13266
No. 6507-11/17
STK672-080
• Excitation phases before and after excitation mode switching <counterclockwise direction>
B24
23
24
25
28
29
0
1
4
5
8
9
12
13
16
17
20
21
A
A
A
0
16
15
31
A
A
B
B
B 24
25
26
27
28
29
30
31 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1617
18
19
20
21
24
26
28
30
0
2
4
6
8
10
12
14
16
18
20
22
22
23
A
A
B
B
8
7
12
4
28
20
20
24
28
0
4
8
12
16
B24
30
A
A
A
0
16
22
24
28
0
4
8
12
16
20
20
28
4
12
16
28
24
20
0
4
12
16
18
20
22
24
25
27
29
31 1
3
5
7
923
22
8
24
20 10
26
18
12
16
14
28
30
6
4
2
0
1121
1319
1517
24
28
0
4
8
12
16
20
26
28
30
0
2
4
6
8
10
12
14
6
B
B
A
B
A
B
30 2
26 6
10
14
22
18
A
B
A
B
A
B
A
B
B
A
A
B
B
8
14
12
4
28
20
24
0
8
16
20
26
2
10
28 4
1220
28 4
1220
18
28
4
12
A
B
A
B
30
3
27
7
11
15
23
24
28
0
4
8
12
16
20
19
A
B
A
B
27
3
11
19
A
B
A
B
A13267
2W1-2 phase → 2 phase
W1-2 phase → 2 phase
1-2 phase → 2 phase
2 phase → 1-2 phase
2W1-2 phase → 1-2 phase
W1-2 phase → 1-2 phase
1-2 phase → W1-2 phase
2 phase → W1-2 phase 2 phase → 2W1-2 phase
2W1-2 phase → W1-2 phase
W1-2 phase → 2W1-2 phase
1-2 phase → 2W1-2 phase
No. 6507-12/17
STK672-080
M1
0
M2
0
M3
RESET
CWB
CLK
MOI
0
1
2 Phase Excitation Timing Chart (M3=1) 1-2 Phase Excitation Timing Chart (M3=1)
2W1-2 Phase Excitation Timing Chart (M3=1)W1-2 Phase Excitation Timing Chart (M3=1)
M1
1
0
1
0
M2
0
M3
RESET
CWB
CLK
MOI
M1
1
1
0
M2
0
M3
RESET
CWB
CLK
MOI
0
M1
1
0
1
0
1
0
M2
M3
RESET
CWB
CLK
MOI
MOSFET Gate Signal
Comparator Reterence Voltage
A
A
B
B
Vref A
Vref B
100%
71%
100%
71%
Comparator Reterence Voltage
Vref A
100%
92%
71%
40%
Vref B
100%
92%
71%
40%
MOI
Comparator Reterence Voltage
Vref A
100%
92%
83%
71%
55%
40%
20%
MOI
MOSFET Gate Signal
A
A
B
B
MOSFET Gate Signal
Comparator Reterence Voltage
A
A
B
B
Vref A
Vref B
100%
71%
100%
71%
MOSFET Gate Signal
A
A
B
B
Vref B
100%
92%
83%
71%
55%
40%
20%
A13268
Excitation Time and Timing Charts
• CLK rising edge operation
• CLK rising and falling edge operation
No. 6507-13/17
STK672-080
M1
0
M2
0
M3
RESET
CWB
CLK
MOSFET Gate Signal
Comparator Reterence Voltage
A
A
B
B
MOI
Vref A
Vref B
100%
71%
100%
71%
Comparator Reterence Voltage
Vref A
Vref B
100%
92%
83%
71%
55%
40%
20%
20%
0
M1
1
0
M2
0
M3
RESET
CWB
CLK
0
M1
0
M2
0
1
M3
RESET
CWB
CLK
MOI
100%
92%
83%
71%
55%
40%
Comparator Reterence Voltage
Vref A
100%
97%
88%
77%
66%
48%
31%
66%
48%
31%
14%
92%
83%
71%
55%
40%
20%
0
M1
1
0
1
0
M2
0
M3
RESET
CWB
CLK
MOI
0
MOSFET Gate Signal
A
A
B
B
MOSFET Gate Signal
Comparator Reterence Voltage
A
A
B
B
MOI
Vref A
Vref B
100%
71%
40%
92%
100%
92%
71%
40%
MOSFET Gate Signal
A
A
B
B
Vref B
100%
97%
88%
77%
14%
92%
83%
71%
55%
40%
20%
A13269
1-2 Phase Excitation Timing Chart (M3=0) W1-2 Phase Excitation Timing Chart (M3=0)
4W1-2 Phase Excitation Timing Chart (M3=0)2W1-2 Phase Excitation Timing Chart (M3=0)
Thermal Design
<Hybrid IC Average Internal Power Loss Pd>
The main elements internal to this hybrid IC with large average power losses are the current control devices, the
regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss
during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2
phase excitation.
The losses in the various excitation modes are as follows.
fclock IOH· fclock
2 phase excitation Pd
2EX
= (Vsat + Vdf) · ——— · IOH· t2 + ————— · (Vsat · t1 + Vdf · t3)
2 2
fclock IOH· fclock
1-2 phase excitation Pd
1-2EX
= 0.64 · {(Vsat + Vdf) · ——— · IOH· t2 + ————— · (Vsat · t1 + Vdf · t3)}
4 4
fclock IOH· fclock
W1-2 phase excitation Pd
W1-2EX
= 0.64 · {(Vsat + Vdf) · ——— · IOH· t2 + ————— · (Vsat · t1 + Vdf · t3)}
8 8
fclock IOH· fclock
2W1-2 phase excitation Pd
2W1-2EX
= 0.64 · {(Vsat + Vdf) · ——— · IOH· t2 + ————— · (Vsat · t1 + Vdf · t3)}
16 16
fclock IOH· fclock
4W1-2 phase excitation Pd
4W1-2EX
= 0.64 · {(Vsat + Vdf) · ——— · IOH· t2 + ————— · (Vsat · t1 + Vdf · t3)}
16 16
Here, t1 and t3 can be determined from the same formulas for all excitation methods.
–L R + 0.35 –L VCC1 + 0.35
t1 = ———— · n (1 – ————— · IOH) t3 = —— · n (——————————)
R + 0.35 VCC1 R IOH· R + VCC1 + 0.35
However, the formula for t2 differs with the excitation method.
2 3
2 phase excitation t2 = ——— – (t1 +t3) 1-2 phase excitation t2 = ——— – t1
fclock fclock
7 15
W1-2 phase excitation t2 = ——— – t1
2W1-2 phase excitation
t2 = ——— – t1
fclock 4W1-2 phase excitation fclock
Motor Phase Current Model Figure (2 Phase Excitation)
fclock: CLK input frequency (Hz)
Vsat: The voltage drop of the power MOSFET and the current detection resistor (V)
Vdf: The voltage drop of the body diode and the current detection resistor (V)
I
OH
: Phase current peak value (A)
t1: Phase current rise time (s) V
CC
1: Supply voltage applied to the motor (V)
t2: Constant-current operating time (s) L: Motor inductance (H)
t3: Phase switching current regeneration time (s) R: Motor winding resistance (W)
No. 6507-14/17
STK672-080
t3 t1
t2
I
OH
A13270
Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss
from the thermal resistance of the hybrid IC substrate, namely 25.5 °C/W.
105 – 50
For a Tc max of 105°C at an ambient temperature of 50°C PdEX= ———— = 2.15 W
25.5
105 – 40
For a Tc max of 105°C at an ambient temperature of 40°C PdEX= ———— = 2.54 W
25.5
This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above.
(See ∆Tc – Pdcurve in the graph on page 17.)
<Hybrid IC internal power element (MOSFET) junction temperature calculation>
The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal
resistance θj-c.
Tj = Tc + θj-c × Pds (°C)
Here, we determine Pds, the loss for each transistor, by determining PdEXin each excitation mode.
Pds = Pd/4
Since the average loss includes the loss of the current detection resistor, we take that voltage drop into consideration in
the calculation.
Vsat = IOH· Ron + IOH· Rs
Vdf = Vdf + IOH· Rs
The steady-state thermal resistance of a power MOSFET is 15.6°C/W.
No. 6507-15/17
STK672-080
4
0
8
12
16
20
0 2 4 6 8 10 12 14 16
2
1.0
3
7
5
10
2
10
2 3 5 7
100
2 3 5
No. Fin 25.5(°C/W) No. Fin 25.5(°C/W)
40°C
50°C
60
°C
θc-a=
Tc max – Ta
(°C/W)
Tc max=105°C
Pd
Guaranteed ambient
temperature
2 mm thick Al plate (with no surface preparation)
(with the surface painted black)
Vertical
standing type
Convection
cooling
<Determining the Size of the Hybrid IC Heat Sink>
Determine θc-a for the heat sink from the average power loss determined in the previous item.
Tc max: Hybrid IC substrate temperature (°C)
Ta: Application internal temperature (°C)
Pd
EX
: Hybrid IC internal average loss (W)
Determine θc-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below.
The ambient temperature of the device will vary greatly according to the air flow conditions within the application.
Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum
plate side) will never exceed a Tc max of 105°C, whatever the operating conditions are.
Tc max – Ta
θc-a = —————— [°C/W]
Pd
EX
IC internal average power dissipation, Pd — W
Heat sink thermal resistance, θc-a — °C/W
Heat sink thermal resistance, θc-a — °C/W
Heat sink area, S — cm
2
Pd — θc-a
S — θc-a
No. 6507-16/17
STK672-080
35
37
39
41
43
45
47
49
51
53
55
4 4.5 5 5.5 6
39
41
35
37
43
45
47
49
51
53
55
0 20 40 60 80 100 120
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 0.5 1 21.5 2.5 3 3.5
0.4
0
0.2
0.6
0.8
1
1.2
1.4
1.6
0 0.5 1 1.5 2 2.5 3
0.5
0
1
1.5
2
2.5
0 10 20 30 40 50
0.5
0
1
1.5
2
2.5
0 20
40
60 80 100 120
100
0
50
150
200
250
300
350
400
450
0 20
40
60 80 100 120
100
150
50
0
200
250
300
350
400
450
0 0.5 1 1.5 2 2.5
IOH=1A
Vref=0
Vref=2.5V
Vref=2V
Vref=1
IOH=2
Tc=105°C
Tc=105°C
Tc=25°C
Tc=25°C
Tc=25°C
Supply voltage, VCC2 — V
PWM frequency, fc — kHz
fc — VCC2
Substrate temperature, Tc — °C
PWM frequency, fc — kHz
fc — Tc
Motor current, IOH— A
Output saturation voltage, Vsat — V
Motor Current vs. Output Supply Voltage
Motor current, IOH— A
Internal diode forward voltage, Vdf — V
Internal Diode Forward Voltage vs. Motor Current
Motor voltage, VCC1 — V
Motor current, I
OH
— A
Motor Current vs. Motor Voltage
Substrate temperature, Tc — °C
Motor current, I
OH
— A
Motor Current vs. Substrate Temperature
Reference voltage, Vref — V
Input current, IVref —µA
Reference Voltage vs. Input Current
Substrate temperature, Tc — °C
Reference voltage input current, IVref — µA
Reference Voltage Input Current vs. Substrate Temperature
PS No. 6507-17/17
STK672-080
This catalog provides information as of February, 2002. Specifications and information herein are subject
to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
Notes • The above current ranges apply when the output voltage is not in the avalanche state.
• The above operating substrate temperatures (Tc) are measured when the motor is operating. Since Tc will vary depending on the ambient
temperature (Ta), the value of I
OH
, and whether IOHis continuous or intermittent, the actual values of Tc must be verified (measured) in an actual
operating end product.
Motor current, IOH— A
Reference voltage, Vref — V
Motor Current vs. Reference Voltage
Hybrid IC internal average power dissipation, Pd — W
Substrate temperature rise, ∆Tc — °C
∆Tc — Pd
CLK frequency, PPS - Hz
Substrate temperature rise, ∆Tc — °C
Substrate Temperature Rise Test
Operating substrate temperature, Tc — °C
Motor current, I
OH
— A
Motor Current (I
OH
) Derating Curves for the Operating Substrate Temperature Tc
2
VCC1: 24 V motor: PK264-02B
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 0.5 1 1.5 2 2.5
60
50
40
30
VCC1 : 24V
Test motor : PK264-02B
20
Motor current :
IOH :
10
2-phase excitation: 1.5 A
2W1-2 phase excitation: 2 A
With no heat sink
0
0 2 3 5 7
2W1-2ex
2ex
2 3 5 7
1000
10000
2 3 5 7
100000
80
70
60
50
40
30
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5
3.5
3
2.5
2
1.5
1
0.5
0
0 20 40 60 80 100 120
Hold mode
CLK ≥ 200Hz
Motor voltage: 24 V
Motor resistance (R): 0.4 Ω
Inductance (L): 1.2 mH
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