SANYO LC9998G Datasheet
CMOS LSI
Ordering number : EN*5219
22896HA (OT) No.5219-1/11
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/5" Optical Size PAL Color
Solid-State Image Sensor
LC9998G
Overview
The LC9998G is a 1/5" optical size frame transfer type
CCD (charge-coupled device) solid-state image sensor
developed for use in color video cameras.
Features
• Effective number of pixels (total pixels): 499H × 582V
(532H × 600V)
• Number of optical black pixels:
Horizontal direction: Front: 7 pixels
Back: 26 pixels
Vertical direction: Front: 14 pixels
Back: 4 pixels
• Dummy bits: Horizontal direction: 4 pixels
• Horizontal resolution: 220 TV lines
• Supports miniature, compact camera designs.
• Package: 20-pin half-pitch transparent DIP
• Horizontal shift register: 5 V drive
• Supports variable-speed electronic shutter operation
Device Structure
• 1/5" type frame transfer CCD image sensor
• Unit cell size: 5.8 µm (H) × 3.75 µm (V)
• Chip size: 4.18 mm (H) × 5.10 mm (V)
• Parallel gate CCD sensor
• Built-in high-sensitivity output amplifier
• Cy-G-Ye stripe complementary color filter
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Package Dimensions
unit: mm
3217
Preliminary
[LC9998G]
Parameter Symbol Conditions Ratings Unit
V
DD
V
PW
= 0 V –0.3 to +18 V
V
GG
V
PW
= 0 V –0.3 to +5 V
Maximum supply voltage NSUB-PW –0.3 to +50 V
NSUB - ø1 to ø4,
–0.3 to +55 V
øS1 to øS4:
Horizontal clock pin øR V
PW
= 0 V –0.3 to +18 V
Other clock pins V
PW
= 0 V –15 to +18 V
Other pins V
PW
= 0 V –0.3 to +10 V
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –30 to +80 °C
Block Diagram
Pin Assignment
No.5219-2/11
LC9998G
Pixel Arrangement
Pin Functions
No.5219-3/11
LC9998G
Pin No. Symbol Function Pin No. Symbol Function
1 NSUB N-substrate 20 NSUB N-substrate
2 VPW P-well 19 øS4
3 ø4 18 øS1
Storage area clock
4 ø3
Image area clock
17 øS2
5 ø2 16 øS3
6 ø1 15 øH1
Horizontal area clock
7 øR Reset gate 14 øH2
8 V
DD
Supply voltage 13 V
OG
CCD output gate
9 V
OUT
CCD output 12 V
GG
Load gate
10 NSUB N-substrate 11 NSUB N-substrate
Specifications
Clock Voltage Conditions at Frame frequency = 3.58 MHz
Note: 1. Insert 47 pF capacitors as shown in Figure 2.
2. Adjust V
HSUB
within the range where image degradation does not occur so that the saturated output level is maximized.
Figure 1
Figure 2
No.5219-4/11
LC9998G
Parameter Symbol Conditions min typ max Unit
Imaging block pulses
Pulse amplitude V
PIF
*1
14.0 14.5 15.0 V
ø1, ø2, ø3, ø4
Low level V
LIF
–10.0 –9.5 –9.0 V
Storage block pulses
Pulse amplitude V
PSL
14.0 14.5 15.0 V
øS1, øS2
Low level V
LSL
–7.0 –6.5 –6.0 V
Storage block pulses
Pulse amplitude V
PSL
14.0 14.5 15.0 V
øS3, øS4
Low level V
LSL
–8.0 –7.5 –7.0 V
Horizontal transfer pulses
Pulse amplitude V
PH
4.5 5.0 5.5 V
øH1, øH2
Low level V
LH
0 0 0.5 V
Reset gate
Pulse amplitude V
PR
4.5 5.0 5.5 V
øR
Low level V
LR
4.2 4.5 4.8 V
Substrate pulse
High level V
HSUB
*2
See Figure 1.
30.0 40.0 V
øNSUB
Low level V
LSUB
17.5 18.0 18.5 V
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