SANYO LC89978M Datasheet
Overview
The LC89978M is a CCD delay line for multi television
system that incorporates a comb filter to remove noise
from the chrominance signal and a 1-H delay line for the
luminance signal.
Features
• 5-V single-voltage power supply
• Built-in 4 × PLL frequency multiplier circuit allows 4fsc
operation from an fsc (3.58 MHz) input.
• Can be switched between the NTSC/M, PAL/GBI, and
PAL/M formats by setting control pin values.
• Includes a built-in crosstalk exclusion comb filter for the
chrominance signal that provides high-precision comb
characteristics in an adjustment-free circuit.
• Peripheral circuits provided on chip for operation with a
minimum of external components.
• Positive-phase signal input, positive-phase signal output
(luminance signal)
Functions
• CCD shift registers (for chrominance and luminance
signals)
• Timing generator and clock driver for CCD
• Delay time selective circuit
• CCD signal adder
• Auto-bias circuit
• Sync tip clamp circuit (luminance signal)
• Center bias circuit (chrominance signal)
• Sample-and-hold circuit
•4 ×PLL frequency multiplier circuit
• 4fsc clock output circuit
• High voltage generator for CCD Reset Drain (RD).
Package Dimensions
unit: mm
3111-MFP14S
CMOS LSI
Ordering number : EN5546A
73097HA (OT)/N3096HA (OT) No. 5546-1/7
SANYO: MFP14S
[LC89978M]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
CCD Delay Line for Multi-System
LC89978M
Parameter Symbol Conditions Ratings Unit
Supply voltage V
DD
–0.3 to +6.0 V
Allowable power dissipation Pd max 250 mW
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –55 to +125 °C
Specifications
Absolute Maximum Ratings at Ta = 25°C
No. 5546-2/7
LC89978M
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage V
DD
4.75 5.00 5.25 V
Clock input amplitude V
CLK
300 500 1000 mVp-p
Clock frequency F
CLK
Sine wave 3.579545 MHz
Chrominance signal input amplitude V
IN-C
350 500 mVp-p
Luminance signal input amplitude V
IN-Y
400 572 mVp-p
Allowable Operating Ranges at Ta = 25°C
Pin Assignment
Block Diagram
No. 5546-3/7
LC89978M
CONT1 CONT2 Mode (representative) Chrominance signal delay (number of CCD stages) Luminance signal delay (number of CCD stages)
Low Low PAL/GBI 2H (1833.5) + 0H (1.5) 1H (913)
Low High PAL/M 2H (1821.5) + 0H (1.5) 1H (907)
High Low — — —
High High NTSC/M 1H (911.5) + 0H (1.5) 1H (907)
Control Pin Functions
Parameter Symbol Conditions
Ratings
Unit
min typ max
Switching voltage level: low V
L
–0.3 0.0 +0.5 V
Switching voltage level: high V
H
2.0 5.0 6.0 V
Switching Voltage Levels
Function of the 4FSC Pin
This pin provides a 4fsc clock signal generated by the 4 × PLL frequency multiplier circuit.
Note: *Since the control pins have built-in pull-down resistors (about 70 kΩ), leaving these pins opens effectively sets them to the low level.
Continued on next page.
Parameter Symbol
Switch states Ratings
Unit
SW1 SW2 SW3 SW4 Test conditions min typ max
I
DD-1
a a a b *1
Supply current I
DD-2
a b a b *1 31 36 41 mA
I
DD-3
b b a b *1
[Chrominance signal characteristics] (with no input to Y-IN)
V
INC-1
a a a b *2
V
INC-2
a b a b *2 1.9 2.4 2.9 V
DC output voltage
V
INC-3
b b a b *2
V
OUTC-1
a a a b *2
V
OUTC-2
a b a b *2 1.4 1.9 2.4 V
V
OUTC-3
b b a b *2
G
VC-1
a a a b *3
Voltage gain G
VC-2
a b a b *3 –2 0 +2 dB
G
VC-3
b b a b *3
C
D-1
a a a b *4
Comb depth C
D-2
a b a b *4 –40 –35 dB
C
D-3
b b a b *4
L
NC-1
a a a b *5
Linearity L
NC-2
a b a b *5 –0.3 0.0 +0.3 dB
L
NC-3
b b a b *5
L
CK4C-1
a a a b *6
Clock leakage (4fsc) L
CK4C-2
a b a b *6 10 50 mVrms
L
CK4C-3
b b a b *6
L
CK1C-1
a a a b *6
Clock leakage (fsc) L
CK1C-2
a b a b *6 0.5 1.5 mVrms
L
CK1C-3
b b a b *6
Electrical Characteristics at VDD= 5.0 V, Ta = 25°C, F
CLK
= 3.579545 MHz, V
CLK
= 500 mVp-p
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