Sanyo LC898023K Specifications

Ordering number : ENN*6614
82500RM (OT) No. 6614-1/12
Functions
• CD-ROM decoder/encoder functions
• CD decoder/encoder functions
• Pit and wobble CLV servo
• CAV audio functions
• Subcode encoder/decoder functions
• ATIP demodulator/ATIP decoder
• Write strategy function (CD-R/RW)
• CD-DSP function with built-in digital servo
Features
• ECC and EDC correction/addition (decoding/encoding) for CD-ROM data.
• ECC error correction/addition (decoding/encoding) for subcode data
• Servo control implemented in a digital servo system (decoding/encoding)
• Wobble CLV servo control using ATIP data (encoding)
• ATIP decoding function and CRC check function (decoding/encoding)
• CIRC code generation and addition and EFM modulation (encoding)
• CAV audio functions
• Write strategy function supports 8× and 16× recording.
• Built-in SCSI interface (supports Ultra SCSI)
• Supports 40× decoding and 16× encoding. Clock frequencies: CD-ROM block: 33.8688 MHz, SCSI block: 20 MHz
• Ultra SCSI data transfer rate: 20 Mbyte/s (Maximum synchronous transfer rate), Fast SCSI: 10 Mbyte/s (Maximum synchronous transfer rate), 5 Mbyte/s
(Maximum asynchronous transfer rate) Uses 16-bit data bus 50 ns EDO DRAM.
• From 1 to 64 Mbits of buffer RAM can be used. (16-bit data bus EDO DRAM)
• The user can freely set up the CD main channel, C2 flag, and subcode areas in buffer RAM.
• Batch transfer function (Function for transferring the CD main channel, C2 flag, subcode, and other data in a single operation)
• Multi-transfer function (Function for automatically transferring multiple blocks to the host in a single operation)
Package Dimensions
unit: mm
3210-SQFP208
28.0
(3.2)
30.6
0.15
0.2
0.35
3.8max
0.5
30.6
(0.5)
(1.25)
28.0
1
52
156 105
53
208
104
157
Preliminary
SANYO: SQFP208
[LC898023K]
LC898023K
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40× Playback/16× Write CD-R/RW Encoder/Decoder IC
with Built-in SCSI Interface
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
“BURN-Proof” stands for Proof against Buffer Under RuN error, not for proof against burning. “BURN-Proof” is a trademark of SANYO Electric Co.,Ltd.
No. 6614-2/12
LC898023K
Parameter Symbol Conditions Ratings Unit
Supply voltage
V
DD
5 max Ta 25°C –0.3 to +6.0 V
V
DD
3 max Ta 25°C –0.3 to +4.6 V
I/O voltages
V
I
5, VO5 Ta 25°C –0.3 to VDD5 + 0.3 V
V
I
3, VO3 Ta 25°C –0.3 to VDD3 + 0.3 V Allowable power dissipation Pd max Ta 70°C 750 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Soldering conditions (pins only) 10 seconds 260 °C
Specifications
Absolute Maximum Ratings at VSS= 0 V
Parameter Symbol Conditions
Ratings
Unit
min typ max
[I/O cells, 5.0 V power supply]
Supply voltage V
DD
5 4.5 5.0 5.5 V
Input voltage range V
IN
0V
DD
5V
[Internal cells, 3.3 V power supply]
Supply voltage V
DD
3 3.0 3.3 3.6 V
Input voltage range V
IN
0V
DD
3V
Allowable Operating Ranges at Ta = –30 to +70°C, VSS= 0 V
Parameter Symbol Conditions
Ratings
Unit
min typ max
High-level input voltage V
IH
TTL level inputs: (2), (14)
2.2 V
Low-level input voltage V
IL
0.8 V
High-level input voltage V
IH
TTL level inputs with built-in pull-up resistors: (13)
2.2 V
Low-level input voltage V
IL
0.8 V
High-level input voltage V
IH
TTL level Schmitt trigger inputs: (1)
2.5 V
Low-level input voltage V
IL
0.6 V
High-level input voltage V
IH
(15)
2.0 V
Low-level input voltage V
IL
0.8 V
High-level input voltage V
IH
CMOS level Schmitt trigger inputs: (3)
0.8 V
DD
V
Low-level input voltage V
IL
0.2 V
DD
V
High-level input voltage V
IH
CMOS level inputs with built-in pull-up resistors: (4)
0.7 V
DD
V
Low-level input voltage V
IL
0.3 V
DD
V
Analog input voltage V
ANI
(5) 1/4 V
DD
3/4 V
DD
V
High-level output voltage V
OHIOH
= –12 mA: (8) VDD– 2.1 V
Low-level output voltage V
OLIOL
= 12 mA: (8) 0.4 V
High-level output voltage V
OHIOH
= –8 mA: (7) VDD– 2.1 V
Low-level output voltage V
OLIOL
= 8 mA: (7) 0.4 V
High-level output voltage V
OHIOH
= –2 mA: (6), (13), (14) VDD– 2.1 V
Low-level output voltage V
OLIOL
= 2 mA: (6), (13), (14) 0.4 V
Low-level output voltage V
OLIOL
= 48 mA: (15) 0.4 V
Low-level output voltage V
OLIOL
= 8 mA: (12) 0.4 V
Low-level output voltage V
OLIOL
= 1 mA: (9) 0.4 V
High-level output voltage V
OHIOH
= –4 mA: (11) VDD– 2.1 V
Low-level output voltage V
OLIOL
= 4 mA: (11) 0.4 V
Analog output voltage V
ANO
(10) 1/4 V
DD
3/4 V
DD
V
Input leakage current I
IL
VI= VSS, VDD: (1), (2), (14), (15) –10 +10 µA
Output leakage current I
OZ
In the high-impedance output state: (9), (11), (12) –10 +10 µA
Pull-up resistance R
UP
(12), (13) 40 80 160 k
Pull-up resistance R
UP
(4) 50 100 200 k
Electrical Characteristics at Ta = –30 to +70°C, VSS= 0 V, VDD= 4.5 to 5.5 V
The applicable pin groups are listed on the following page.
Applicable Pins
[INPUT]
(1) · · · · · · WOBBLE, CS, RD, WR, DEF, HFL, TES (2) · · · · · · SUA0 to SUA7, TEST0 to TEST4, RESET (3) · · · · · · WRITE (4) · · · · · · FG (5) · · · · · AD0, AD1, RREC, FE, TE, VREF, FR, OPP, JITIN, PCKISTF, PCKISTP, EFMIN, EFMIN2, SLCIST1,
SLCIST2
[OUTPUT]
(6) · · · · · · LDON (7) · · · · · EFMG, SHOCK, LOCK, EFMO, SSP2/1, RAPC, WAPC, H11TO, LDH, ATEST3, ATEST1, WDAT,
NWDAT (8) · · · · · · PCK2, RA0 to RA9, CAS0 to CAS1, RAS0 to RAS2, LWE, UWE, OE, SUBSYNC (9) · · · · · · PDS1 to PDS3 (10) · · · · · DA0 to DA2, TDO, FDO, SLDO, SPDO, JITC, LOUT, ROUT, PDO, RPO, SLDO, SLCO1 to SLCO3 (11) · · · · · DSLB (12) · · · · · INT0, INT1, SWAIT
[INOUT]
(13) · · · · · D0 to D7, ID0 to ID15 (14) · · · · · ATIPSYNC, BICLK, BIDATA, ACRCNG (15) · · · · · ACK, ATN, BSY, C/D, DB0 to DB7, DBP, I/O, MSG, REQ, RST, SEL
Note: The XTAL0, XTAL1, XTALCK0, and XTALCK1 are not included in the DC characteristics.
SCSI Pin Input Characteristics
Active Negation Output Characteristics
Note: The active negation output characteristics only applies to DB0 to DB7, REQ, and DBPB
Rise Time Test Circuit
No. 6614-3/12
LC898023K
SCSI Driver
TP
47
Ω±
5%
15pF±5%
2.5V
+ –
A13188
Parameter Symbol Conditions
Ratings
Unit
min typ max
Input threshold voltage
V
t + t1
VDD= 4.50 to 5.50 V 1.60 2.00 V
V
t – t1
VDD= 4.50 to 5.50 V 0.80 1.10 V
Hysteresis width V
tt1
VDD= 5.0 V 0.41 0.5
Parameter Symbol Conditions
Ratings
Unit
min typ max
Output high voltage V
OH
2.5 V
Output low voltage V
OL
0.4 V
No. 6614-4/12
LC898023K
De-scramble &
Buffering
Address generator
Microcontroller
RAM access
Address generator
Address generator
ECC & EDC
SCSI I/F Block
Address generator
Data output input I/F
Bus
Arbiter
&
DRAM
controller
External
Buffer
DRAM
Each Block Bus control signal
Each Block Register R0-R87
CD-DSP I/F
& SYNC Detector
Digital Servo
&
CIRC EnDec
HOST
Micro
controller
decoder
PLL
&
Clock
generator
*8
DAC
*9
TEST0 to 4
*13
*10
*6 *7
*3
*2
CAV-Audio
Sub-code ECC
Address generator
*1
Write Strategy
&
Link-position
*12
Sub-code I/F
de-interleve/interleve
Address generator
ATIP/CLV servo
ATIPSYNC
INT0, INT1
SWAIT
XTALCK0
XTAL0
XTALCK1
XTAL1
Each Block
SCSI Block
Data bus[0:7]
Address bus[0:21]
RAM Data bus[0:15]
LC898023K
A13191
*1 DSLB (pin96) to FR (pin123), AD0 (pin127) to SPDO (pin142), SHOCK (pin147) to PCK2 (pin155) *2 SUBSYNC *3 DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D, ACK, ATN *6 RD, WR, SUA0 to SUA7, CS *7 D0 to D7 *8 IO0 to IO15
*9 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE *10 WOBBLE, BIDATA, BICLK *12 WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, TEST2/1, WDAT, NWDAT, EFMG *13 LOUT, ROUT
Block Diagram
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