SANYO LC89512W Datasheet
Ordering number : EN*4852B
O3095HA (OT)/D1694TH (OT) No. 4852-1/5
Overview
The LC89512W integrates a real-time error correction
circuit and a SCSI interface in a single chip.
Functions
• CD-ROM error correction function, subcode readout
function, SCSI interface
Features
• Support for double-speed drives at an operating
frequency of 16.9344 MHz
Either SRAM (120 ns), DRAM (80 ns) or pseudo
SRAM (85 ns) can be used.
• Support for quad-speed drives at an operating frequency
of 33.8688 MHz
SRAM (70 ns) must be used.
• Built-in SCSI interface with built-in 48 mA sink buffer
(Only the TARGET function is supported.)
• Built-in 12-byte output FIFO for sub-CPU to host
computer data transmission
• Built-in 12-byte input FIFO for host computer to subCPU data transmission
• Subcode data can be written to buffer RAM and the subCPU can read the subcode values by connecting the
LC89512 to the CD-DSP subcode pin.
• Sub-CPU access of buffer RAM through the LC89512
• Built-in function for buffer RAM internal data transfer
• Pseudo-SRAM (128-kword × 8-bit and smaller) can be
used.
• DRAM (two 256-kword × 4-bit chips or two 1-Mword ×
4-bit chips) can be used.
• Transfer speeds:
2.8 MB/second (asynchronous mode) (for CD-ROM
decode only operation)
4.2 MB/second (synchronous mode) (CD-ROM decode
operation is not supported in synchronous mode)
Both of these transfer modes use a 16.9344 MHz clock.
(The transfer speed depends on the frequency used.)
• Operating frequencies: 16.9344 MHz (up to double
speed), 33.8688 (quad speed)
Package Dimensions
unit: mm
3181A-SQFP100
Preliminary
SANYO: SQFP100
[LC89512W]
LC89512W
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
CD-ROM Error Correction LSI
with Built-In SCSI Interface
CMOS LSI
Block Diagram
No. 4852-2/5
LC89512W
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