Sanyo LC8772C8B Specifications

Ordering number : ENN*6842

LC8772C8B/B2B/96B/80B

8-Bit Single-Chip Microcontroller

Preliminary
Overview

The LC8772C8B, LC8772B2B LC877296B and LC877280B are 8 bit single chip microcontrollers with the following
on-chip functional blocks :

- CPU: operable at a minimum bus cycle time of 100 ns

- On-chip ROM Maximum Capacity : LC8772C8B 128K bytes
LC8772B2B 112K bytes
LC877296B 96K bytes
LC877280B 80K bytes

- On-chip RAM capacity: 2048 bytes

- LCD controller / driver

- 16 bit timer / counter (can be divided into two 8 bit timers)

- 16 bit timer / PWM (can be divided into two 8 bit timers)

- Timer fo r use as date / time clock

- Synchronous serial I/O port (with automatic block transmit / receive function)

- Asynchronous / synchronous serial I/O port

- 12-channel × 8-bit AD converter

- Small signal detector

- 14-source 10-vectored interrupt system

All of the above functions are fabricated on a single chip.

Features

(1) Read-Only Memory (ROM)

- 131072 × 8bits (LC8772C8B)

- 114688 × 8bits (LC8772B2B)

- 98304 × 8bits (LC877296B)

- 81920 × 8bits (LC877280B)

(2) Random Access Memory (RAM): 2048 × 9 bits (LC8772C8B, LC8772B2B, LC877296B, LC877280B)

(3) Minimum Bus Cycle Time: 100 ns (10 MHz)
Note: The bus cycle time indicates ROM read time.

(4) Minimum Instruction Cycle Time: 300 ns (10MHz)

CMOS IC

Ver.1.00
N2599

11901 RM (IM) SK No.6842-1/24

LC8772C8B/B2B/96B/80B

(5) Ports

- Input/output ports
Data direction programmable for each bit individually : 26 (P1n, P30-P35, P70-P7 3, P 8n)
Data direction programmable in nibble units : 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)

- Input ports : 2 (XT1,XT2)

- LCD ports
Segment output : 48 (S00-S47)
Common output : 4 (COM0-COM3)
Bias terminals for LCD driver 3 (V1-V3)

Other functions

Input/output ports : 48(PAn,PBn,PCn,PDn,P En,P Fn)
Input ports : 7 (PLn)

- Oscillator pins : 2 (CF1,CF2)

- Reset pin : 1 (

RES

)

- Power supply : 6 (VSS1-3,VDD1-3)

(6) LCD controller

- Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)

- Segment output and common output can be switched to general purpose input/output ports.

(7) Small signal detection (MIC signals etc)

- Counts pulses with the level which is greater than a preset value

- 2 bit counter

(8) Timers

- Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register

- Timer 1: PWM / 16 bit timer with toggle output function
Mode 0: 2 channel 8 bit timer (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.

- Base Timer

1) The clock signal can be selected from any of the following :

Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0

2) Interrupts of five different time intervals are possible.

(9) Serial-interface

- SIO 0: 8 bit synchronous serial interface

1) LSB first / MSB first is selectable

2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 Tcyc)

3) Consecutive automatic data communication (1-256 bits)

- SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

(10) AD converter

-8 bits × 12 channels

No.6842-2/24

LC8772C8B/B2B/96B/80B

(11) Re mo te control receiver circuit (connecte d to P73 / INT3 / T0IN termina l)

-Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 Tcyc)

(12) Watchdog timer

- The watching time period is determined by an external RC.

- Watchdog timer can produce interrupt or system reset

(13) Interrupts: 14 sources, 10 vectors

1) Three prior ity (low, high and highest) multiple interrupts are supported. During inte rrupt hand ling, an equal or

lower priority interrupt request is postponed.

2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.

In the case of equal priority levels, the vector with the lowest address takes precedence.

No. Vector Selectable Level Interrupt signal

1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L
4 0001BH H or L INT3/Base timer
5 00023H H or L T0H
6 0002BH H or L T1L/T1H
7 00033H H or L SIO0
8 0003BH H or L SIO1
9 00043H H or L ADC/MIC

10 0004BH H or L Port 0

• Priority Level : X > H > L

• For equal priority levels, vector with lowest address takes precedence.

(14) Subroutine stack levels: 1024 levels max. Stack is located in RAM.

(15) Multiplication and division

- 16 bit × 8 bit (executed in 5 cycles)

- 24 bit × 16 bit (12 cycles)

- 16 bit ÷ 8 bit (8 cycles)

- 24 bit ÷ 16 bit (12 cycles)

(16) Oscillation circuits

- On-chip RC oscillation for system clock use.

- CF oscillation for system clock use. (Rf built in, Rd external)

- Crystal oscillation low speed system clock use. (Rf built in, Rd external)

(17) Standby function

- HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop.)

1) Oscillation circuits are not stopped automatically.

2) Released by the system reset or interrupts.

-HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.

1) CF, RC and crystal oscillation circuits stop automatically.

2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt

No.6842-3/24

LC8772C8B/B2B/96B/80B

-X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.

1) CF and RC oscillation circuits stop automatically.

2) Crystal oscillator operation is kept in its state at HOLD mode inception.

3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
(4) Base-timer interrupt

(18) Package

- QIP100E

- SQFP100

(19) Development tools

- Evaluation chip : LC876096

- Emulator: EVA62S + ECB876500 (Evaluation chip board) + SUB877200 + POD100QFP
or POD100SQFP (Type B)

- Flash ROM version: LC87F72C8A

No.6842-4/24

Pin Assignment

Z

V2/PL5

V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3

P30
P31

VSS3

VDD3

P32
P33
P34
P35
P00
P01
P02
P03
P04
P05

LC8772C8B/B2B/96B/80B

V3/PL6

S47/PF7

S46/PF6

S45/PF5

S44/PF4

S43/PF3

S42/PF2

S41/PF1

S40/PF0

S39/PE7

S38/PE6

S37/PE5

S36/PE4

S35/PE3

S34/PE2

S33/PE1

S32/PE0

S31/PD7

S30/PD6

S29/PD5

S28/PD4

S27/PD3

S26/PD2

S25/PD1

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94
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98
99
100

1 2 3 4 5 6 7 8 9

P06

P07

P13/SO1

P10/SO0

P12/SCK0

P11/SI0/SB0

P14/SI1/SB1

P15/SCK1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CF1

RES

XT1/AN10

P16/T1PWML

P17/T1PWMH/BU

CF2

VSS1

VDD1

P80/AN0

P81/AN1

P82/AN2

P83/AN3

P84/AN4

P85/AN5

XT2/AN11

P86/AN6

S24/PD0

25

P87/AN7/MICIN

VSS2

26

VDD2

S23/PC7

S22/PC6

S21/PC5

51

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

27

28

29

30

S0/PA0

P72/INT2/T0IN

P73/INT3/T0IN

P70/INT0/T0LCP/AN8

P71/INT1/T0HCP/AN9

S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1

SANYO: QIP100E

No.6842-5/24

LC8772C8B/B2B/96B/80B

L

Z

S46/PF6

S45/PF5

S44/PF4

S43/PF3

S42/PF2

S41/PF1

S40/PF0

S39/PE7

S38/PE6

S37/PE5

S36/PE4

S35/PE3

S34/PE2

S33/PE1

S32/PE0

S31/PD7

S30/PD6

S29/PD5

S28/PD4

S27/PD3

S26/PD2

S25/PD1

S24/PD0

VSS2

VDD2

S47/PF7

V3/PL6
V2/PL5

V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3

P30
P31

VSS3

VDD3

P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
P06
P07

P10/SO0

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94
95
96
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98
99
100

1 2 3 4 5 6 7 8 9

10

11

12

13

14

15

16

17

18

19

20

21

S23/PC7

50

S22/PC6

49

S21/PC5

48

S20/PC4

47

S19/PC3

46

S18/PC2

45

S17/PC1

44

S16/PC0

43

S15/PB7

42

S14/PB6

41

S13/PB5

40

S12/PB4

39

S11/PB3

38

S10/PB2

37

S9/PB1

36

S8/PB0

35

S7/PA7

34

S6/PA6

33

S5/PA5

32

S4/PA4

31

S3/PA3

30

S2/PA2

29

S1PA1

28

S0/PA0

27

P73/INT3/T0IN

26

22

23

24

25

CF1

CF2

VSS1

VDD1

P80/AN0

P81/AN1

P82/AN2

P83/AN3

P84/AN4

P85/AN5

XT2/AN11

P86/AN6

P72/INT2/T0IN

P87/AN7/MICIN

P70/INT0/T0LCP/AN8

P71/INT1/T0HCP/AN9

P15/SCK1

RES

XT1/AN10

P16/T1PWM

P17/T1PWMH/BU

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

SANYO: SQFP100

No.6842-6/24

System Bl ock Diagram

j

LC8772C8B/B2B/96B/80B

Interrupt Control

IR PLA

SIO0

SIO1

Timer 0

Timer 1

Stand-by C ontr ol

CF

RC

X’tal

Clock

Generator

Bus Interface

Port 0

Port 1

Port 3

Port 7

ROM

PC

ACC

B Register

C Register

ALU

Base Timer

LCD Controller

INT0-3

Noise Re

ection Filter

Port 8

ADC

Weak Signa Detector

PSW

RAR

RAM

Stack Pointer

Watch Do g Timer

No.6842-7/24

LC8772C8B/B2B/96B/80B

Pin Assignment

Pin name I/O Function Option

VSS1
VSS2
VSS3
VDD1
VDD2
VDD3
PORT0
P00 to P07

PORT1
P10 to P17

PORT3
P30 to P35

PORT7
P70 to P73

- • Power supply (-) No

- • Power supply (+) No

I/O • 8bit input/output port

• Data direction programmable in nibble units

• Use of pull-up resistor can be specified in nibble units

• Input for HOLD release

• Input for port 0 interrupt

I/O • 8bit input/output port

• Data direction pr ogrammable for each bit

• Use of pull-up resistor can be specified for each bit individ ually

• Other pin functions
P10 SIO0 data output
P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output

I/O • 6bit Input/output port

• Data direction can b e specified for each bit

• Use of pull-up resistor can be specified for each bit individ ually

• 4bit Input/output port

I/O

• Data direction can be specified for each bit

• Use of pull-up resistor can be specified for each bit individ ually

• Other func tions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog

timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input
P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture

input

AD input port: AN8(P70), AN9(P71)

• Interrupt detection selection

Yes

Yes

Yes

No

INT0
INT1
INT2
INT3

Rising Falling Rising and

Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes

falling

No

No
Yes
Yes

H level L level

Yes
Yes

No
No

Yes
Yes

No
No

No.6842-8/24