Sanyo LC86E6560 Specifications

Ordering number : ENN*6750

CMOS IC

LC86E6560

8-Bit Single Chip Microcontroller

with the UVEPROM

Preliminary
Overview

The LC86E6560 is a CMOS 8-bit single chip microcontroller with UVERPOM for the LC866500 series. This
microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 60K-byte EPROM.
The program data is rewritable. It is suitable to develop the program.

Features

(1) Option switching by EPROM data

(2) Internal EPROM capacity : 61696 bytes
(3) Internal RAM capacity : 1152 bytes

(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1.0µs to 366µs
(6) Operating temperature : +10°C to +40°C
(7) The pin compatible with the LC866500 series mask ROM devices
(8) Applicable mask ROM version : LC866560/LC866556
(9) Factory shipment : QFC100S (with window)

The option function of the LC866500 series can be specified by the EPROM data.
LC86E6560 can be checked the functions of the trial pieces using the mass production board.

Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E6560.

Mask ROM version EPROM capacity RAM capacity

LC866560 61440 bytes 1152 bytes
LC866556 57344 bytes 1152 bytes

Ver.1.02
21897

91400 RM (IM) SK No.6750-1/21

LC86E6560

Notice for use

LC86E6560 is provided for the first release and small shipping of the LC866500 series.
At using, take notice of the followings.

(1) A point of difference LC86E6560 and LC866500 series.

Item LC86E6560 LC866560/56

Operation after reset
releasing

Pull-down resistor of the
following pins

•

S0/T0 - S6/T6
S7/T7 - S15/T15

•

•

S16 -S31
S32 - S47

•

•

S48 -S51
Operating temperature
range (Topg)
Power dissipa tion Refer to ‘electrical ch aracteristics’ on the semiconductor news.

The option is specified until 3ms
after going to a ‘H’ level to the
reset terminal by degrees.
The program is executed from
00H of the program counter.
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
Not provided

10°C to 40°C -30°C to 70°C

LC86E6560 uses 256 bytes that is a ddressed on FF00 H to FFFFH in the p rogram memory as the option configuratio n
data area. This option configuration cannot execute all options which LC866500 series have. Next tables show the
options that correspond and not correspond to LC86E6560.

• A kind of the option corresponding of the LC86E6560

A kind of option Pins, Circuits Contents of the option

Input/output form of
input/output ports

Port 0

Port 1

Port 3

1. N-channel open drain output

2. CMOS output *1

1. Pull-up MOS Tr. provide d

2. Pull-up MOS Tr. not provided *2

1. Input

*1

Output

2. Input
Output

1. Input

*1

Output

2. Input
Output

*1) Specified in a bit
*2) Specified in nibble unit. The port of N-channel open drain output does not have the Pull-up MOS Tr..

• A kind of the option not corresponding of the LC86E6560

A kind of option Pins, Circuits LC86E6560 LC866560/56

Pull-down resistor of the
high voltage withstand
output terminals

S0/T0 to S6/T6

•

•

S16 to S31
S32 to S47

•

Not provided
Provided (fixed)
Not provided

(2) Option

The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE” .

(3) ROM space

LC86E6560 and LC866500 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 61440 bytes that is addressed on 0000H to EFFFH.

The program is executed from
00H of the program counter
immediately after going to a ‘H’
level to the reset terminal.

Pull-down resistor
provided/not provided
Specified by the op tion
Provided (fixed)
Specified by the opt ion
Specified by the opt ion
Not provided

: Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
:CMOS
: Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
:CMOS

Specified by the opt ion
Specified by the opt ion
Specified by the opt ion

No.6750-2/21

LC86E6560

0FFFFH

0FF00H

0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH

9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH

0000H

The option

specified area

256 bytes

Program area

60K bytes

LC866560

The option

specified area

Program area

56K bytes

LC866556

No.6750-3/21

LC86E6560

How to use

(1) Preparation

A complete evaluation (EVA) file must be converted to an INTEL-HEX formatted (HEX) file for program to the
LC86E6560.
An EVA2HEX.EXE. can convert a EVA file to a HEX file.
Program the file that converted by the EVA2HEX to the LC86E6560.

(2) How to program for the EPROM

LC86E6560 can be programmed by the EPROM programmer with attachment ; W86EP6548Q.

• Recommended EPROM programmer

Productor EPROM programmer
Advantest R4945, R4944, R4943

Andou AF-9704
AVAL PKW-1100, PKW-3000

Minato electronics MODEL1890A

• ”27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must be set to ‘OFF’ at programming.

(3) How to use the data security function

“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.

1. Set ‘ON’ the jumper of attachment.

2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security.
It is not a trouble of the EPROM programmer or the LSI.

Notes

• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.

• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at
the sequence 2 above.

• Set to ‘OFF’ the jumper after executing the data security.

Data security

1 pin mark of LSI

1 pin

Not data security

W86EP6548Q

(4) How to eliminate

The programming data can be erased by using the EPROM eraser.

(5) Shielding

The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.

No.6750-4/21

Pin Assignment

S48/PG0
S49/PG1
S50/PG2
S51/PG3

P00
P01
P02
P03

VSS2

VDD2

P04
P05
P06
P07

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

LC86E6560

S47/PF7

S46/PF6

S45/PF5

S44/PF4

S43/PF3

S42/PF2

S41/PF1

S40/PF0

VDD4

S39/PE7

S38/PE6

S37/PE5

S36/PE4

S35/PE3

S34/PE2

S33/PE1

S32/PE0

S31/PD7

S30/PD6

S29/PD5

S28/PD4

S27/PD3

S26/PD2

S25/PD1

8079787776757473727170696867666564636261605958575655545352
81
82

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1 2 3 4 5 6 7 8 9

P30

P31

P32

P33

P16/BUZZ

P17/PWM0

P34

P35

P36

10

P37

11

P70/INT0

12

RES

13

XT1/P74

14

XT2/P75

15

VSS1

16

CF1

17

CF2

18

VDD1

19

P80/AN0

20

P81/AN1

21

P82/AN2

22

P83/AN3

23

P84/AN4

24

P85/AN5

S24/PD0

25

P86/AN6

S23/PC7

26

P87/AN7

S22/PC6

27

P71/INT1

S21/PC5

28

P72/INT2/T0IN

S20/PC4

29

P73/INT3/T0IN

VP

51

30

S0/T0

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1

SANYO : QFC100S

No.6750-5/21

System Bl ock Diagram

y

p

Base Timer

SIO0

SIO1

Timer 0

Timer 1

ADC

INT0 to 3

Noise Filter

SIO Automatic

transmission

RAM

128 b

tes

VFD controller

High voltage

ut

Out

Interrupt Control

Standby Control

CF

RC

X’tal

Colck

Generator

LC86E6560

Bus Interface

Port 1

Port 3

Port 7

Port 8

IR PLA

EPROM

Control

EPROM (48KB)

PC

ACC

B Register

C Register

ALU

PSW

RAR

RAM

Stack Pointer

Port 0

Watchdog T i mer

A15-A0
D7-D0
TA
CE
OE
DASEC

No.6750-6/21

LC86E6560

Pin Description

Pin Name I/O Function description Option

VSS1, 2 - Power pin (-) *4 - ­VDD1, 2, 3, 4 - Power pin (+) *4 - ­VP - Power pin (+) for the VFD output pull-down resist - ­PORT 0
P00 - P07

PORT 1
P10 - P17

PORT 3
P30 - P37

PORT 7

P70 - P73

- P75

P74

PORT 8

P80 -P83
P84 -P87

S0/T0 to
S6/T6 *6
S7/T7 to
S15/T15

*7

I/O •8-bit input/output port

Input/output in nibble units

•Input for port0 interrupt

•Input for HOLD release

•15V withstand at N-channel open drain output

I/O •8-bit input/output port

Input/output can be specified in bit unit.

•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM0 output)

I/O •8-bit input/output port

Input/output in bit unit

•15V withstand at N-channel open drain output

•4-bit input/output port
Input/output in bit unit

•2-bit input port

•Other pin functions
P70 : INT0 input/HOLD release/N-chan nel Tr.

I/O

output for watchdog timer
P71 : INT1 input/HOLD release input

I

P72 : INT2 input/timer0 event input
P73 : INT3 input with noise filter/timer0 event
input

: 32. 768kHz crystal oscillation terminal XT1

P74

P75 : 32.768kHz crystal oscillation terminal XT2

•Interrupt recei ved form, vector address
rising falling rising/

INT0
INT1
INT2
INT3

•4-bit input/output port

Input/output in bit unit

•4-bit input port

I

•Other function

I/O

AD input port (8 port pins)

O Output for VFD display controller segment/timing

in common

O •Output for VFD display controller segment

/timing with internal pull-down resistor in
common

•Internal pull-down resistor output

enable
enable
enable
enable

enable
enable
enable
enable

falling
disable
disable

enable

enable

H level L level Vector

enable

enable
disable
disable

•Pull-up resistor :
Provided/not provided
(each nibble)

•Output form :
CMOS/N-channel
open drain (each bit)
Output form :
CMOS/N-channel open
drain (each bit)

Output form :
CMOS/N-channel open
drain (each bit)

-

enable

enable
disable
disable

03H

0BH

13H

1BH

- -

- -

- TA (*5)

EPROM

mode

-

Data line
D0 to D7

-

EPROM
control
signal
DASEC(*1)

OE

(*2)

CE

(*3)

(Continue)

No.6750-7/21