Ordering number : ENN*6750
CMOS IC
LC86E6560
8-Bit Single Chip Microcontroller
with the UVEPROM
Preliminary
Overview
The LC86E6560 is a CMOS 8-bit single chip microcontroller with UVERPOM for the LC866500 series. This
microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 60K-byte EPROM.
The program data is rewritable. It is suitable to develop the program.
Features
(1) Option switching by EPROM data
(2) Internal EPROM capacity : 61696 bytes
(3) Internal RAM capacity : 1152 bytes
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1.0µs to 366µs
(6) Operating temperature : +10°C to +40°C
(7) The pin compatible with the LC866500 series mask ROM devices
(8) Applicable mask ROM version : LC866560/LC866556
(9) Factory shipment : QFC100S (with window)
The option function of the LC866500 series can be specified by the EPROM data.
LC86E6560 can be checked the functions of the trial pieces using the mass production board.
Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E6560.
Mask ROM version EPROM capacity RAM capacity
LC866560 61440 bytes 1152 bytes
LC866556 57344 bytes 1152 bytes
Ver.1.02
21897
91400 RM (IM) SK No.6750-1/21
LC86E6560
Notice for use
LC86E6560 is provided for the first release and small shipping of the LC866500 series.
At using, take notice of the followings.
(1) A point of difference LC86E6560 and LC866500 series.
Item LC86E6560 LC866560/56
Operation after reset
releasing
Pull-down resistor of the
following pins
•
S0/T0 - S6/T6
S7/T7 - S15/T15
•
•
S16 -S31
S32 - S47
•
•
S48 -S51
Operating temperature
range (Topg)
Power dissipa tion Refer to ‘electrical ch aracteristics’ on the semiconductor news.
The option is specified until 3ms
after going to a ‘H’ level to the
reset terminal by degrees.
The program is executed from
00H of the program counter.
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
Not provided
10°C to 40°C -30°C to 70°C
LC86E6560 uses 256 bytes that is a ddressed on FF00 H to FFFFH in the p rogram memory as the option configuratio n
data area. This option configuration cannot execute all options which LC866500 series have. Next tables show the
options that correspond and not correspond to LC86E6560.
• A kind of the option corresponding of the LC86E6560
A kind of option Pins, Circuits Contents of the option
Input/output form of
input/output ports
Port 0
Port 1
Port 3
1. N-channel open drain output
2. CMOS output *1
1. Pull-up MOS Tr. provide d
2. Pull-up MOS Tr. not provided *2
1. Input
*1
Output
2. Input
Output
1. Input
*1
Output
2. Input
Output
*1) Specified in a bit
*2) Specified in nibble unit. The port of N-channel open drain output does not have the Pull-up MOS Tr..
• A kind of the option not corresponding of the LC86E6560
A kind of option Pins, Circuits LC86E6560 LC866560/56
Pull-down resistor of the
high voltage withstand
output terminals
S0/T0 to S6/T6
•
•
S16 to S31
S32 to S47
•
Not provided
Provided (fixed)
Not provided
(2) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE” .
(3) ROM space
LC86E6560 and LC866500 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 61440 bytes that is addressed on 0000H to EFFFH.
The program is executed from
00H of the program counter
immediately after going to a ‘H’
level to the reset terminal.
Pull-down resistor
provided/not provided
Specified by the op tion
Provided (fixed)
Specified by the opt ion
Specified by the opt ion
Not provided
: Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
:CMOS
: Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
:CMOS
Specified by the opt ion
Specified by the opt ion
Specified by the opt ion
No.6750-2/21
LC86E6560
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0000H
The option
specified area
256 bytes
Program area
60K bytes
LC866560
The option
specified area
Program area
56K bytes
LC866556
No.6750-3/21
LC86E6560
How to use
(1) Preparation
A complete evaluation (EVA) file must be converted to an INTEL-HEX formatted (HEX) file for program to the
LC86E6560.
An EVA2HEX.EXE. can convert a EVA file to a HEX file.
Program the file that converted by the EVA2HEX to the LC86E6560.
(2) How to program for the EPROM
LC86E6560 can be programmed by the EPROM programmer with attachment ; W86EP6548Q.
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL1890A
• ”27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security.
It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at
the sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
1 pin mark of LSI
1 pin
Not data security
W86EP6548Q
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.
No.6750-4/21
Pin Assignment
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
LC86E6560
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9
P30
P31
P32
P33
P16/BUZZ
P17/PWM0
P34
P35
P36
10
P37
11
P70/INT0
12
RES
13
XT1/P74
14
XT2/P75
15
VSS1
16
CF1
17
CF2
18
VDD1
19
P80/AN0
20
P81/AN1
21
P82/AN2
22
P83/AN3
23
P84/AN4
24
P85/AN5
S24/PD0
25
P86/AN6
S23/PC7
26
P87/AN7
S22/PC6
27
P71/INT1
S21/PC5
28
P72/INT2/T0IN
S20/PC4
29
P73/INT3/T0IN
VP
51
30
S0/T0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
SANYO : QFC100S
No.6750-5/21
System Bl ock Diagram
y
p
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0 to 3
Noise Filter
SIO Automatic
transmission
RAM
128 b
tes
VFD controller
High voltage
ut
Out
Interrupt Control
Standby Control
CF
RC
X’tal
Colck
Generator
LC86E6560
Bus Interface
Port 1
Port 3
Port 7
Port 8
IR PLA
EPROM
Control
EPROM (48KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog T i mer
A15-A0
D7-D0
TA
CE
OE
DASEC
No.6750-6/21
LC86E6560
Pin Description
Pin Name I/O Function description Option
VSS1, 2 - Power pin (-) *4 - VDD1, 2, 3, 4 - Power pin (+) *4 - VP - Power pin (+) for the VFD output pull-down resist - PORT 0
P00 - P07
PORT 1
P10 - P17
PORT 3
P30 - P37
PORT 7
P70 - P73
- P75
P74
PORT 8
P80 -P83
P84 -P87
S0/T0 to
S6/T6 *6
S7/T7 to
S15/T15
*7
I/O •8-bit input/output port
Input/output in nibble units
•Input for port0 interrupt
•Input for HOLD release
•15V withstand at N-channel open drain output
I/O •8-bit input/output port
Input/output can be specified in bit unit.
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM0 output)
I/O •8-bit input/output port
Input/output in bit unit
•15V withstand at N-channel open drain output
•4-bit input/output port
Input/output in bit unit
•2-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-chan nel Tr.
I/O
output for watchdog timer
P71 : INT1 input/HOLD release input
I
P72 : INT2 input/timer0 event input
P73 : INT3 input with noise filter/timer0 event
input
: 32. 768kHz crystal oscillation terminal XT1
P74
P75 : 32.768kHz crystal oscillation terminal XT2
•Interrupt recei ved form, vector address
rising falling rising/
INT0
INT1
INT2
INT3
•4-bit input/output port
Input/output in bit unit
•4-bit input port
I
•Other function
I/O
AD input port (8 port pins)
O Output for VFD display controller segment/timing
in common
O •Output for VFD display controller segment
/timing with internal pull-down resistor in
common
•Internal pull-down resistor output
enable
enable
enable
enable
enable
enable
enable
enable
falling
disable
disable
enable
enable
H level L level Vector
enable
enable
disable
disable
•Pull-up resistor :
Provided/not provided
(each nibble)
•Output form :
CMOS/N-channel
open drain (each bit)
Output form :
CMOS/N-channel open
drain (each bit)
Output form :
CMOS/N-channel open
drain (each bit)
-
enable
enable
disable
disable
03H
0BH
13H
1BH
- -
- -
- TA (*5)
EPROM
mode
-
Data line
D0 to D7
-
EPROM
control
signal
DASEC(*1)
OE
(*2)
CE
(*3)
(Continue)
No.6750-7/21
LC86E6560
Pin Name I/O Function description Option
S16 to S31
S32 to S47
S48 to S51
RES
P74
XT1/
XT2/P75 O •Output pin for 32.768kHz crystal oscillation
CF1 I Input pin for ceramic resonator oscillation - CF2 O Output pin for ceramic resonator oscillation - -
I/O •Output for VFD display controller segment
*8
*9
*9
•Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
I/O •Output for VFD display controller segment
•Other function
S32 : High voltage input port PE0
S33 : High voltage input port PE1
S34 : High voltage input port PE2
S35 : High voltage input port PE3
S36 : High voltage input port PE4
S37 : High voltage input port PE5
S38 : High voltage input port PE6
S39 : High voltage input port PE7
S40 : High voltage input/output port PF0
S41 : High voltage input/output port PF1
S42 : High voltage input/output port PF2
S43 : High voltage input/output port PF3
S44 : High voltage input/output port PF4
S45 : High voltage input/output port PF5
S46 : High voltage input/output port PF6
S47 : High voltage input/output port PF7
I/O •Output for VFD display controller segment
•Other function
S48 : High voltage input/output port PG0
S49 : High voltage input/output port PG1
S50 : High voltage input/output port PG2
S51 : High voltage input/output port PG3
I Reset pin - I •Input pin for 32.768kHz crystal oscillation
•Other function
XT1 : Input port
In case of non use, connect to VDD1.
•Other function
XT2 : Input port P75
In case of non use, connect to VDD1 at using as
port or unconnect at using as oscillation.
P74
- Address input
- -
- -
- -
- -
EPROM
mode
A15 to A0
* All of port options (except pull-up resistor of port 0) can be specified in bit unit.
(Continue)
No.6750-8/21
LC86E6560
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 Connect like the following figure to reduce noise into a VDD1 terminal. Shorted the VSS1 terminal to the VSS2 terminal
and to make the back-up time long.
*5 TA!EPROM cont rol signal input
*6 S0/T0 to S6/T6 : not provided the pull-down resistor
*7 S7/T7 to S15/T155 : provided the pull-down resistor (fixed)
*8 S16 to S3 1 : provided the pull-down resistor (fixed)
*9 S32 to S51 : not provided the pull-down resistor
Power
Supply
Back-up capacitor
LSI
VDD1
VDD2
VDD3
VDD4
VFD
powers
VSS1 VSS2
No.6750-9/21
LC86E6560
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1, VDD2
VDD3, VDD4
Input voltage
VI(1) •Ports
P74
•Ports 80, 81,
82, 83
•Port 8
RES
•
VI(2) VP
Output voltage VO S0/T0 to
S15/T15
Input/output
voltage
VIO(1) •Port 1
•Ports 70, 71,
72, 73
•Ports 84, 85,
86, 87
•Ports 0, 3 at
CMOS output
option
VIO(2) Ports 0, 3 at
N-ch open
drain output
option
VIO(3) S16 to S51
High
level
output
current
Peak
output
current
IOPH(1) Ports 0, 1, 3 •CMOS output
IOPH(2) S0/T0 to
S15/T15
IOPH(3) S16 to S51 At each pi n. -15
∑
Total
output
current
IOAH(1) Port 0 The total all pins. -30
∑
IOAH(2) Ports 1, 3 The total all pins. -30
∑
IOAH(3) S0/T0 to
S15/T15
∑
IOAH(4) S16 to S27 The total all pins. -60
∑
IOAH(5) S28 to S39 The total all pins. -60
∑
IOAH(6) S40 to S51 The total all pins. -60
Low
level
output
current
output
current
IOPL(1) Ports 0, 1, 3 At each pin. 20 Peak
IOPL(2) •Ports 70, 71,
72, 73
•Ports 84, 85,
86, 87
∑
Total
output
current
IOAL(1) Port 0 The total all pins. 60
∑
IOAL(2) Ports 1, 3, 70 The total all pins. 50
∑
IOAL(3) •Ports 71, 72,
73
•Ports 84, 85,
86, 87
Maximum power
Pdmax QFC100S
dissipation
Operating
Topr +10 +40
temperature
range
Storage
Tstg -55 +125
temperature
range
VDD1=VDD2
=VDD3=VDD4
, 75
-0.3
-0.3
-0.3 15
•For each pin.
At each pin. -30
The total all pins. -55
At each pin. 15
The total all pins. 20
Ta=+10 to +40°C
Ratings
VDD[V]
min. typ. max.
-0.3 7.0
VDD+0.3
VDD-4.5
VDD-4.5
VDD-4.5
VDD+0.3
VDD+0.3
VDD+0.3
VDD+0.3
-10
unit
V
mA
500 mW
C
°
C
°
No.6750-10/21
LC86E6560
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Operating
supply voltage
VDD(1) VDD1=VDD2=
VDD3=VDD4
0.98µs≤t
≤
CYC
400µs
range
Hold voltage VHD VDD1=VDD2 RAMs and
registers hold
voltage at HOLD
mode.
Pull-down
VP VP 4.5 - 6.0 -35 VDD
voltage
Input high
voltage
VIH(1) Port 0 at CMOS
output option
VIH(2) Port 0 at N-ch
Output disable 4.5 - 6.0
Output disable 4.5 - 6.0
open drain output
VIH(3) •Port 1
Output disable 4.5 - 6.0
•Ports 72, 73
•Port 3 at CMOS
output option
VIH(4) Port 3 at N-ch
open drain output
VIH(5) •Port 70
Output disable
Tr. OFF
Output disable 4.5 - 6.0
Port input
/interrupt
•Port 71
•
RES
VIH(6) Port 70
Output disable 4.5 - 6.0 0.9VDD VDD
Watchdog timer
VIH(7) •Port 8
•Ports
P74
, 75
Output disable 4.5 - 6.0
VIH(8) S16 to S51 Output P- channel
Tr. OFF
Input low
voltage
VIL(1) Port 0 at
CMOS
Output disable 4.5 - 6.0 VSS 0.2VDD
output option
VIL(2) Port 0 at N-ch
Output disable 4.5 - 6.0 VSS
open drain
output
VIL(3) •Ports 1, 3
Output disable 4.5 - 6.0 VSS
•Ports 72, 73
VIL(4) •Port 70
Output disable 4.5 - 6.0 VSS
Port input
/interrupt
•Port 71
RES
•
VIL(5) Port 70
Output disable 4.5 - 6.0 VSS
Watchdog timer
VIL(6) •Port 8
P74
•Ports
, 75
Output disable 4.5 - 6.0 VSS
VIL(7) S16 to S51 Output P- channel
Tr. OFF
Operation
CYC
t
4.5 - 6.0 0.98 400
cycle time
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.0 6.0
0.33VDD
+1.0
0.75VDD
0.75VDD
4.5 - 6.0
4.5 - 6.0
0.75VDD
0.75VDD
0.75VDD
0.33VDD
+1.0
4.5 - 6.0 VP 0.2VDD
(Continue)
unit
VDD
13.5
VDD
13.5
VDD
VDD
VDD
0.25VDD
0.25VDD
0.25VDD
0.8VDD
-1.0
0.25VDD
V
V
V
µ
s
No.6750-11/21
LC86E6560
Parameter Symbol Pins Conditions
6MHz (ceramic
Oscillation
frequency
range
(Note 1)
Oscillation
stabilizing
time period
(Note 1)
FmCF(1) CF1, CF2
FmCF(2) CF1, CF2 3MHz (ceramic
FmRC RC oscillation 4.5 - 6.0 0.3 0.8 3.0
FsXtal XT1, XT2 32.768kHz
tmsCF(1) CF1, CF2 6MHz (ceramic
tmsCF(2) CF1, CF2 3MHz (ceramic
tssXtal XT1, XT2 32.768kHz
resonator oscillation)
Refer to figure 1
resonator oscillation)
Refer to figure 1
(X’tal oscillation)
Refer to figure 2
resonator oscillation)
Refer to figure 3
resonator oscillation)
Refer to figure 3
(X’tal oscillation)
Refer to figure 3
(Note 1) The oscillation constant is shown on table 1.
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 6
4.5 - 6.0 3
4.5 - 6.0 32.768 kHz
4.5 - 6.0
4.5 - 6.0
4.5 - 6.0 s
unit
MHz
ms
No.6750-12/21
LC86E6560
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Pull-up MOS
Tr. resistance
IIH(1) Ports 0, 3 of open
drain output
IIH(2) •Port 0 without
pull-up MOS Tr.
•Ports 1, 3
IIH(3) •Ports 70, 71, 72,
73
•Port 8
IIH(4)
IIH(5) Ports
IIH(6) S32 to S51
IIL(1) •Ports 1, 3
IIL(2) •Ports 70, 71, 72,
IIL(3)
IIL(4) Ports
VOH(1) IOH=-1.0mA 4.5 - 6.0 VDD-1
VOH(2)
VOH(3) IOH=-20mA 4.5 - 6.0
VOH(4)
VOH(5) IOH=-5mA 4.5 - 6.0
VOH(6)
VOL(1) IOL=10mA 4.5 - 6.0 1.5
VOL(2)
VOL(3) Port 70 IOL=1mA 4.5 - 6.0 0.4
VOL(4) •Ports 71, 72, 73
Rpu Ports 0, 1, 3 VOH=0.9VDD 4.5 - 6.0 15 40 70 kΩ
RES
VIN=VDD 4.5 - 6.0 1
P74
, 75 VIN=VDD 4.5 - 6.0 1
without pull-down
resistor
•Port 0 without
pull-up MOS Tr.
73
•Port 8
VIN=VSS 4.5 - 6.0 -1
RES
, 75 VIN=VSS 4.5 - 6.0 -1
P74
Ports 0, 1, 3 of
CMOS output
S0/T0 to
S15/T15
S16 to S51
Ports 0, 1, 3
•Ports 84, 85, 86,
87
•Output disable
•VIN=13.5V
(incl uding the off leak current of the
output Tr.)
•Output disable
•Pull-up MOS Tr.
OFF.
•VIN=VDD
(incl uding the off leak current of the
output Tr.)
•Output disable
•VIN=VDD
(incl uding the off leak current of the
output Tr.)
•Output P-channel
Tr. OFF
•VIN=VDD
•Output disable
•Pull-up MOS
Tr. OFF
•VIN=VSS
(incl uding the off leak current of the
output Tr.)
•Output disable
•VIN=VSS
(incl uding the off leak current of the
output Tr.)
IOH=-0.1mA 4.5 - 6.0
•IOH=-1mA
•The current of any
unmeasurement
pin is not over
1 mA.
The current of any
unmeasurement pin
is not over 1mA.
IOL=1.6mA 4.5 - 6.0 0.4
IOL=1.6mA 4.5 - 6.0 0.4
VDD[V] min. typ. max.
4.5 - 6.0 5
4.5 - 6.0 1
4.5 - 6.0 1
4.5 - 6.0 1
4.5 - 6.0 -1
4.5 - 6.0 -1
4.5 - 6.0 VDD-1
4.5 - 6.0 VDD-1
(Continue)
Ratings
VDD-0.5
VDD-1.8
VDD-1.8
unit
µ
V
V
A
No.6750-13/21
LC86E6560
Y
Y
Parameter Symbol Pins Conditions
IOFF(1) •Output P-ch Tr.
leakage
current
IOFF(2)
S0/T0 to S6/T6,
S32 to S51
without pull-down
resistor
OFF
•VOUT=VSS
•Output P-ch Tr.
OFF
•VOUT=VDD-40V
Resistance of
the low level
hold Tr.
Rinpd S16 to S51 •Output P-ch Tr.
OFF
•Using as input
ports
High voltage
pull-down
resistor
Rpd •S7/T7 to
S15/T15
•S16 to S31
•Output P-ch Tr.
OFF
•VOUT=3V
•Vp=-30V
VP pull-down
resistor
Hysteresis
voltage
Rvppd Vp •VSS=GND
•Vp=-30V
VHIS •Port 1
Output disable 4.5 - 6.0 0.1VDD V
•Ports 70, 71, 72,
73, 75
•
RES
Pin
capacitance
CP All pins •f=1MHz
Unmeasurement
terminals for input
are set to VSS
level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 -1 Output off-
unit
µ
4.5 - 6.0 -30
4.5 - 6.0 200
kΩ
5.0 60 100 200
5.0 60 100 200
4.5 - 6.0 10 pF
A
4. Serial Input/Output Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Cycle t
Low Level
CKCY
CKL
t
•SCK0
(1) 2
•SCK1
(1) 1
Refer to figure 5. 4.5 - 6.0
pulse width
High Level
Input clock
pulse width
Cycle t
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set up ti me
Data hold time
Serial input
CKH
t
(1)
CKCY
CKL
t
•SCK0
(2) 2
•SCK1
(2)
•Use pull-up
resistor (1kΩ)
when open drain
CKH
t
(2)
output.
•Refer to figure 5.
ICK
t
•SI0, SI1
0.1
•SB0, SB1
•Data set-up to
SCK0, 1.
•Data hold from
CKI
t
SCK0, 1.
•Refer to figure 5.
Output delay time
(Serial clock is
external clock)
Output delay time
(Serial clock is
Serial output
internal clock)
CKO(1)
t
CKO(2)
t
•SO0, SO1
4.5 - 6.0
•SB0, SB1
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0, 1.
•Refer to figure 5.
Ratings
VDD[V] min. typ. max.
1
4.5 - 6.0
1/2tCKC
1/2tCKC
4.5 - 6.0
0.1
7/12tCYC
+0.2
4.5 - 6.0
1/3tCYC
+0.2
unit
CYC
t
µ
s
No.6750-14/21
LC86E6560
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
rejection clock is
selected to 1/1.)
tPIH(3)
tPIL(3)
INT3/T0IN
(The noise
•Interrupt accept able
•Timer0-countable
rejection clock is
selected to 1/16.)
tPIH(4)
tPIL(4)
INT3/T0IN
(The noise
•Interrupt accept able
•Timer0-countable
rejection clock is
selected to 1/64.)
RES
tPIL(5)
Reset acceptable 4.5 - 6.0 200
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 1
4.5 - 6.0 2
4.5 - 6.0 32
4.5 - 6.0 128
unit
CYC
t
µ
High/low level
s
6. AD Converter Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Resolution N 4.5 - 6.0 8 bit
Absolute
ET 4.5 - 6.0 ±1.5 LSB
precision
(Note 2)
Conversion
time
tCAD
AD conversion time
=16×tCYC
(ADCR2=0)
(Note 3)
AD conversion time
=32×tCYC
(ADCR2=1)
(Note 3)
Analog input
VAIN 4.5 - 6.0 VSS VDD V
AN0 - AN7
voltage range
IAINH VAIN=VDD 4.5 - 6.0 1 Analog port
input current
IAINL
VAIN=VSS 4.5 - 6.0 -1
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 15.68
(tCYC=
µ
0.98
4.5 - 6.0 31.36
(tCYC=
µ
0.98
65.28
s)
130.56
s)
(tCYC=
4.08
(tCYC=
4.08
unit
µ
s
µ
s)
µ
s)
µ
A
(Note 2) Absolute precision does not include quantizing error (±1/2LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6750-15/21
LC86E6560
7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
Ceramic resonator
oscillation
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
CF oscillation
•1/1 divided
IDDOP(2) •FmCF=3MHz
Ceramic resonator
oscillation
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
CF oscillation
•1/2 divided
IDDOP(3) •FmCF=0Hz
(When oscillation
stops.)
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDOP(4) •FmCF=0Hz
(When oscillation
stops.)
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
X’tal oscillation
•Internal RC
oscillation stops.
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 14 33
4.5 - 6.0 6 18
4.5 - 6.0 4 13
4.5 - 6.0 3 10
(Continue)
unit
mA
No.6750-16/21
LC86E6560
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
Current dissipation
in HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
CF oscillation
•1/1 divided
IDDHALT(2) •HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
CF oscillation
•1/2 divided
IDDHALT(3) •HALT mode
•FmCF=0Hz
(When oscillation
stops.)
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDHALT(4) •HALT mode
•FmCF=0Hz
(When oscillation
stops.)
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
X’tal oscillation
•Internal RC
oscillation stops.
•1/2 divided
IDDHOLD(1) HOLD mode 4.5 - 6.0 0.05 30 µA
Ratings
VDD[V] min. typ. max.
4.5 - 6.0 5 14 mA
4.5 - 6.0 2.2 7 mA
4.5 - 6.0 400 1600
4.5 - 6.0 25 100
(Note 4) The currents of outp ut tra n sist ors and pull-up MOS transistors are ignored.
unit
µ
A
No.6750-17/21
LC86E6560
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2
oscillation
oscillation
Murata 6MHz ceramic resonator
Kyocera
Murata 3MHz ceramic resonator
Kyocera
TBD
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4 Rd Rf
32.768kHz crytal oscillation
* Both C3 and C4 must be a J rank (±5%) and CH characteristics.
(K rank (±10%), SL characteristics parts can be used for the applications which do not require oscillation accuracy.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2
XT1 XT2
Rf
Rd
CF
C2 C1
C3
X’tal
C4
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6750-18/21
LC86E6560
Power supply
RES
Reset time
VDD
VDD limit
0V
resonator oscillation
Internal RC
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction
execution mode
OCR6=1
Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
resonator oscillation
Internal RC
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stabilizing time
No.6750-19/21
LC86E6560
f
RES
R
C
VDD
RES
RES
(Note) Fix the value of C
RES
, R
RES
that is
sure to reset until 200µs, after Power
supply has been over inferior limit o
supply voltage.
Figure 4 Reset circuit
<AC timing point>
0.5VDD
SCK0
SCK1
tCKL tCKH
SI0
SI1
tCKO
SO0, SO1
SB0, SB1
tCKCY
tICK tCKI
<Timing>
VDD
1kΩ
50pF
<Test load>
Figure 5 Serial input / output test condition
tPIL tPIH
Figure 6 Pulse input timing condition
No.6750-20/21
LC86E6560
No.6750-21/21
PS
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