Ordering number : ENN*6698
CMOS IC
LC865632/28/24/20/16/12/08A
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC865632A/28A/24A/20A/16A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following
on-chip functional blocks :
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM maximum capacity : 32K bytes
- On-chip RAM capacity : 640 bytes (LC865632A/28A/24A)
: 512 bytes (LC865620A/16A/12A/08A)
- 16-bit timer/counter (or tw o 8-bit tim ers )
- 16-bit timer/ PWM (or two 8-bit timers)
- 8-channel × 8-bit AD converter
- Two 8-bit synchronous serial-in terface circuits
- 13-sour ce 10-vec tored in terrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM) : LC865632A 32512 × 8 bits
(2) Random Access Memory (RAM) : LC865632A/28A/24A 640 × 8 bits
: LC865620A/16A/12A/08A 512 × 8 bits
(3) Bus Cycle Time / Instruction Cycle Time
The LC865632A/28A/24A/20A/16A/12A/08A are constructed to read ROM twice within one instruction cycle. It has
1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcontrollers
(LC66000 series).
Bus cycle time indicates the speed to read ROM.
: LC865628A 28672 × 8 bits
: LC865624A 24576 × 8 bits
: LC865620A 20480 × 8 bits
: LC865616A 16384
: LC865612A 12288
: LC865608A 8192
Bus cycle time cycle time System clock osci llation Oscillation Frequenc y Voltage
0.5µs 1.0µs
2.0µs 4.0µs
3.75µs 7.5µs
91.5µs 183µs
Ceramic resonator oscillation 6MHz 4.5 - 6.0V
Ceramic resonator oscillation 1.5MHz 2.5 - 6.0V
RC resonator oscillation 800MHZ 2.5 - 6.0V
Crystal oscillation 32.568kHz 2.5 - 6.0V
8 bits
×
8 bits
×
8 bits
×
Ver.2.02
22599
91400 RM (IM) HK No.6698-1/20
LC865632/28/24/20/16/12/08A
(4) Ports
- Input / output ports : 6 ports (42 terminals)
Input/output port programmable in nibble units : 1 port (8 terminals)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit : 5 ports (34 terminals)
Include 15V withstand N-channel open drain output port : 3 ports (18 terminals)
- Input ports : 2 ports (13 terminals)
(5) AD converter
- 8 channels × 8-bit AD converters
(6) Serial-interface
- Two 8-bit serial-interf ace circuits
LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
(7) Timers
- Timer0
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The reso lu tion of Timer i s 1 tC YC . (tCYC : cycle time)
- Timer 1
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC.
In Mode 2 and Mode 3, the resolution of Timer and PWM selectable ; tCYC or 1/2tCYC by program
- Base timer
Every 500ms overflow system for a clock application (using 32.568kHz crystal oscillation for Base timer clock)
Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.568kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.568kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(8) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz (using 32.568kHz crystal oscillation for Base timer clock)
(9) Remote control receiver circuit (Shares with th e P73/INT3/T0IN terminal)
- Noise rejection function
- Switch polarity function
(10) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable : interrupt system, system reset
No.6698-2/20
LC865632/28/24/20/16/12/08A
(11) Interrupts system
- 13-sources 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (Lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial interface SIO0
8. Serial interface SIO1
9. AD converter
10. Port 0
- Built-in interrupt priority control register
Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can specify
a low level o r a high lev el interr upt pr iori ty from INT 2/T 0L throug h por t 0 (i .e. th e abo ve inte rrup t number f rom thr ee
through ten). It can also specify a low level or the highest level interrupt priority to INT0 and INT1.
(12) Real-time service operation
The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at acknowledging
the interrupt request.
The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt
request.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
(14) Multiplication and division
- 16 bits × 8-bit (7 instruction cycle times)
- 16 bits ÷ 8-bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit usin g for the system clock
- On-chip CR oscillation circuit using for the system clock
- On-chip crystal oscillation circuit using for the system clock and for time-base clock
XT1 terminal can be used as
P74
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This
operation mode can be released by the interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
RES
• Reset terminal (
) set to low level
• P70/INT0, P71/INT1 terminals set to assigned level (programmable)
• Input a Port 0 interrupt condition
(17) Factory shipment
• DIP64S, QFP64E delivery form
(18) Development support tools
- Evaluation (EVA) chip : LC866098
- EPROM version : LC86E5632
- One time version : LC86P5632
- Emulator : EVA86000 + ECB866600 (Evaluation chip board)
+ POD865000 (Pod for DIP64S)
+ POD865010 (Pod for QFP64E)
No.6698-3/20
Pin Assignment
•DIP64S
Package Dimension
(unit : mm)
3071
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P30
P31
P32
P33
LC865632/28/24/20/16/12/08A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
SANYO : DIP-64S(750mil)
No.6698-4/20
•QIP64E
Package Dimension
(unit : mm)
3159
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
LC865632/28/24/20/16/12/08A
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
48
47
46
45
44
43
42
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1 2 3 4 5 6 7 8 9
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
41
P30
P31
P32
P33
P07
40
P34
P06
P35
39
10
P05
38
11
P36
P04
37
12
P37
P03
36
13
P40
P02
35
14
P41
P01
34
15
P42
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P00
33
16
P43
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
SANYO : QIP-64E
No.6698-5/20
System Bl ock Diagram
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0 to 3
Noise Filtter
Real Time Service
RAM
(128 bytes)
LC865632/28/24/20/16/12/08A
Interrupt Control
Standby Control
CF
RC
X’tal
Clock
Generator
Bus Interface ACC
Port 1
Port 7
Port 8
Port 2
Port 3
Port 4
Port 5
IR
B Register
C Register
Stack Pointer
Watchdog T i mer
PLA
ROM
PC
ALU
PSW
RAR
RAM
Port 0
No.6698-6/20
LC865632/28/24/20/16/12/08A
Pin Description
Pin name I/O Function description Option
VSS - Power pin (–) VDD - Power pin (+) VDDVPP* - Power pin (+) PORT0
P00 - P07
PORT1
P10 - P17
I/O • 8-bit input/output port
• Input for port 0 interrupt
• Input/output in nibble units
• Input for HOLD release
I/O • 8-bit input/output port
• Input/output can be specified in bit unit
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Output form :
CMOS/N-channel open drain
• Other pin functi ons
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
PORT2
P20 - P27
PORT3
P30 - P37
PORT4
P40 - P47
PORT5
P50, P51
I/O • 8-bit input/output port
• Input/output in bit unit
I/O • 8-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
I/O • 8-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
I/O • 2-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
* Connect like the following figure to reduce noise into a VDD terminal.
Short-circuit the VDD ter min al to the VDDV PP terminal.
Short-circuit the VSS termina l to the VSS termin al.
VDD
LSI
Power
Supply
VDDVPP
VSS VSS
No.6698-7/20
LC865632/28/24/20/16/12/08A
Pin name I/O Function description Option
PORT7
P70
P74
P71 -
• 5-bit input port
• Other pin functi ons
P70 : INT0 input/HOLD release/N-channel
I/O
Tr. output for watchdog timer
P71 : INT1 input/HOLD release inpu t
I
• Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
P74
does not have Pull-up resistor
•
option
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
P74 : Input pin XT1 for 32.768kHz crystal
oscillation
• Interrupt received form, vector address
rising falling rising
&
high
level
low
level
vector
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
PORT8
P80 - P87
I • 8-bit input port
• Pin description
-
AD input port (8 port pins)
RES
TEST1 O • Test pin
I Reset pin -
Should be left unconnected
• Output fixed HIGH
XT1/
P74
I • Input pin for 32.768kHz crystal oscillation
-
In case of non use, connect to VDD
P74
• Other function : Input port
XT2 O • Output pin for 32.768kHz crystal oscillation
-
• In case of non use, should be left
unconnected
CF1 I Input pin for ceramic resonator oscillation CF2 O Output pin for ceramic resonator oscillation * All of port options can be specified in bit unit.
* A state of pins at res e t
Pin name Input/output mode A state of pull-up resistor specified at pull-up option
Port 0
Input Fixed pull-up resistor exist
Ports 70,71,72,73
Ports 1,2,3,4,5 Input Programmable pull-up resistor OFF
No.6698-8/20
LC865632/28/24/20/16/12/08A
V
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter Symbol Pins Conditions
Ratings
DD[V] min. typ. max.
Supply voltage VDDMAX VDD,VDDVPP VDD=VDDVPP -0.3 +7.0
Input voltage VI(1)
•Ports 71,72,73,
-0.3 VDD+0.3
74
unit
V
•Por t 8
•
RES
voltage
VIO(1) •Ports 0,1,2
•Ports 3,4,5 at
-0.3 VDD+0.3 Input/output
CMOS output
option
VIO(2) Ports 3,4,5 at N-ch
-0.3 15
open drain output
option
High
level
output
current
Peak
output
current
Total
output
IOPH(1) Ports 0,1,2,3,4,5 •CMOS output
•At each pin
ΣIOAH(1)
IOAH(2)
Σ
Ports 0,1 Total all pins -20
Ports 2,3,4,5 Total all pins -20
-4
mA
current
Low
level
output
current
dissipation
Operating
output
current
Total
output
current
IOPL(1) Ports 0,1,2,3,4,5 At each pin 20 Peak
IOPL(2) Port 70 At each pin 15
ΣIOAL(1)
Ports 0,1
Total all pins 40
Port 70
ΣIOAL(2)
IOAL(3)
Σ
Pdmax(1) DIP64S
Pdmax(2) QFP64E
Topr -30 +70
Port 2 Total all pins 40
Ports 3,4,5 T otal all pins 80
Ta=-30 to +70°C
Ta=-30 to +70°C
670 Maximum powe r
420
mW
C
°
temperature
range
Storage
Tstg -65 +150
temperature
range
No.6698-9/20
LC865632/28/24/20/16/12/08A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
supply voltage
range
VDD(1)
VDD(2)
VDD
0.98µs ≤ tCYC ≤
400µs
3.9µs ≤ tCYC ≤
400µs
Hold voltage VHD VDD RAMs and the
registers hold
voltage at HOLD
mode.
Input high
VIH(1) Port 0 (Schmitt) Output disable 2.5-6.0 0.4VDD
voltage
VIH(2) •Ports 1,2
Output disable 2.5-6.0 0.75VDD VDD
•Ports 72,73 (Schmitt)
VIH(3) •Port 70
(Port input/interrupt)
Output N-channel
Tr. OFF
•Port 71
RES
•
(Schmitt)
VIH(4) Port 70
(Watchdog timer)
VIH(5)
•Port
74
•Port 8
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disable
CMOS output
VIH(7) Ports 3,4,5 of open
Output disable
drain output
Input low
voltage
VIL(1) Po rt 0 (Schmitt) Output disable 2.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1,2,3,4,5
Output disable 2. 5-6.0 VSS 0.25VDD
•Ports 72,73 (Schmitt)
VIL(3) •Port 70
(Port input/interrupt)
N-channel
Tr. OFF
•Port 71
RES
(Schmitt)
•
VIL(4) Port 70
(Watchdog timer)
VIL(5)
•Port
74
•Port 8
N-channel
Tr. OFF
Output N-channel
Tr. OFF
tCYC
cycle time
Continue.
Ratings
VDD[V] min. typ. max.
4.5 6.0 Operating
2.5 6.0
2.0 6.0
VDD
+0.9
2.5-6.0 0.75VDD VDD
2.5-6.0 0.9VDD VDD
2.7-6.0 0.75VDD VDD
4.0-6.0 0.75VDD VDD VIH(6) Ports 3,4,5 of
2.5-4.0 0.8VDD VDD
4.0-6.0 0.75VDD 13.5
0.
2.5-4.0
8VDD 13.5
2.5-6.0 VSS 0.25VDD
2.5-6.0 VSS 0.8VDD
-1.0
2.5-6.0 VSS 0.25VDD
4.5-6.0 0.98 400 Operation
2.5-6.0 3.9 400
unit
V
µs
No.6698-10/20
LC865632/28/24/20/16/12/08A
Parameter Symbol Pins Conditions
Oscillation
frequency
range
(Note 1)
FmCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •1.5MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmRC RC oscillation 2.5-6.0 0.3 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 2
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5-6.0 6
unit
MHz
2.5-6.0 1.5
2.5-6.0 32.768 kHz
4.5-6.0
ms
4.5-6.0 tmsCF(2) CF1, CF2 •1.5MHz
2.5-6.0
4.5-6.0
s
2.5-6.0
No.6698-11/20
LC865632/28/24/20/16/12/08A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Input high
current
IIH(1) Ports 3,4,5 of open
drain output
•Out put dis a ble
•VIN=13.5V
(including the off leak current of the
output Tr.)
IIH(2) •Port 0 without
pull-up MOS T r .
•Ports 1,2,3,4,5
•Out put dis a ble
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the off leak current of the
output Tr.)
IIH(3) •Ports 70,71,72,73
•VIN=VDD 2.5-6.0 1
without pull-up
MOS Tr.
•Port 8
Input low
current
IIH(4)
RES
IIL(1) •Ports 1,2,3,4,5
•Port 0 without
pull-up MOS T r .
VIN=VDD 2.5-6.0 1
•Out put dis a ble
•Pull-up MOS
T r . OFF. VIN=VSS
(including the off leak current of the
output Tr.)
IIL(2) •Ports 70,71,72,73
•VIN=VSS 2.5-6.0 -1
without pull-up
MOS Tr.
•Port 8
voltage
Output low
voltage
IIL(3)
VOH(1) IOH=-1.0mA 4.5-6.0 VDD-1 Output high
VOH(2)
VOL(1) IOL=10mA 4.5-6.0 1.5
RES
Ports 0,1,2,3,4,5 of
CMOS output
Ports 0,1,2 , 3,4,5
VOL(2) IOL=1.6mA 4.5-6.0 0.4
VOL(3)
VIN=VSS 2.5-6.0 -1
IOH=-0.1mA 2.5-6.0 VDD-0.5
•IOL=1.0mA
•The current of any
unmeasurement pin
is not over 1 mA.
Tr. resistor
Hysteresis
voltage
VOL(4) IOL=1mA 4.5-6.0 0.4
VOL(5)
Rpu •Ports 0,1,2,3,4,5
VHIS •Ports 0,1,2,3,4,5
Port 70
•Ports 70,71,72,73
•Ports 70,71,72,73
RES
•
IOL=0.5mA 2.5-6.0 0.4
VOH=0.9VDD
Output disable 2.5-6.0 0.1VDD V
Pin capacitance CP All pins •f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
2.5-6.0 5
unit
A
µ
2.5-6.0 1
2.5-6.0 -1
V
2.5-6.0 0.4
4.5-6.0 15 40 70 Pull-up MOS
kΩ
2.5-4.5 25 70 150
2.5-6.0 10 pF
No.6698-12/20
LC865632/28/24/20/16/12/08A
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Cycle tCKCY(1) 2.7-6.0 2
Low Level
tCKL(1) 2.7-6.0 1
SCK0,
SCK1
Refer to figure 5.
pulse width
High Level
Input clock
pulse width
Cycle tCKCY(2) 2.7-6.0 2
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
tCKH(1)
SCK0,
tCKL(2) 2.7-6.0 1/2
SCK1
•Use pull-up
resistor (1kΩ)
when open drain
tCKH(2)
output.
•Refer to figure 5.
•SI0,SI1
•SB0,SB1
tCKI
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
tCKO(1)
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0,1
Output delay time
(Serial clock is
Serial output
internal clock)
tCKO(2)
•Refer to figure 5.
Ratings
VDD[V] min. typ. max.
2.7-6.0 1
tCKCY
2.7-6.0 1/2
tCKCY
4.5-6.0 0.1 Data set up time tICK
2.7-6.0 0.4
4.5-6.0 0.1
2.7-6.0 0.4
4.5-6.0 7/12
tCYC
+0.2
2.7-6.0 7/12
tCYC
+1
4.5-6.0 1/3
tCYC
+0.2
2.7-6.0 1/3
tCYC
+1
unit
tCYC
s
µ
No.6698-13/20
LC865632/28/24/20/16/12/08A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
High/low level
pulse width
tPIH(1)
tPIL(1)
•INT0, INT1
•INT2/T0IN
•Interrupt acceptable
•Timer0-countable
Ratings
VDD[V] min. typ. max.
2.7-6.0 1
unit
tCYC
•INT3
tPIH(2)
tPIL(2)
INT3/T0IN
(The noise rejection
Interrupt acceptable 2.7-6.0 2
clock is selected to
1/1.)
tPIH(3)
tPIL(3)
INT3/T0IN
(The noise rejection
Interrupt acceptable 2.7-6.0 32
clock is selected to
1/16.)
tPIL(4)
RES
Reset acceptable 4.5-6.0 200
s
µ
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=0V
Parameter Symbol Pins Conditions
Ratings
VDD[V] min. typ. max.
unit
Resolution N 4.5-6.0 8 bit
Absolute precision
ET 4.5-6.0 ±1.5 LSB
(Note 2)
Conversion time tCAD
AD conversion time =
16 × tCYC
(ADCR2=0)
4.5-6.0
68
15.
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
s
µ
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
(Note 3)
Analog input
VAIN 4.5-6.0 VSS VDD V
AN0 - AN7
voltage range
input current
IAINH VAIN=VDD 4.5-6.0 1 Analog port
IAINL
VAIN=VSS 4.5-6.0 -1
µA
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6698-14/20
LC865632/28/24/20/16/12/08A
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
VDD
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDOP(2) 4.5-6.0 3 7
IDDOP(3)
•FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDOP(4) 4.5-6.0 1.0 3.5
IDDOP(5)
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
IDDOP(6) 4.5-6.0 50 150
IDDOP(7)
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
Continue.
Ratings
VDD[V] min. typ. max.
4.5-6.0 10 20
2.7-4.5 1.5 5
2.7-4.5 0.6 3.0
2.7-4.5 25 75
unit
mA
A
µ
No.6698-15/20
LC865632/28/24/20/16/12/08A
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
IDDHALT(1) •HALT mode
VDD
•FmCF=6MHz
Ceramic resonator
Ratings
VDD[V] min. typ. max.
4.5-6.0 5 10
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDHALT(2) 4.5-6.0 2.2 4.6
IDDHALT(3)
•HALT mode
•FmCF=1.5MHz
2.7-4.5 0.8 2.5
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDHALT(4) 4.5-6.0 800 2000
IDDHALT(5)
•HALT mode
FmCF=0Hz
2.7-4.5 400 1500
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
IDDHALT(6) 4.5-6.0 35 140
IDDHALT(7)
•HALT mode
FmCF=0Hz
2.7-4.5 11 56
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
in HOLD mode
(Note 4)
IDDHOLD(1) 4.5-6.0 0.05 30 Current dissipation
IDDHOLD(2)
VDD HOLD mode
2.7-4.5 0.02 20
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
µA
No.6698-16/20
LC865632/28/24/20/16/12/08A
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2 Rf Rd
12MHz ceramic resonator
oscillation
3MHz ceramic resonator
oscillation
Murata
Murata
CSA12.0MTZ 33pF 33pF OPEN
CSA12.0MTZ 39pF 30pF OPEN
CST12.0MTW on chip OPEN
CSA3.00MG040 100pF 100pF OPEN
CST3.00MGW040 on chip OPEN
560Ω
0Ω
560Ω
1.5Ω
1.5Ω
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4
Kyocera KF-38G-13P0200 18pF 18pF 32.768kHz crystal oscillation
Seiko Epson MC-306,C-002RX,32.768kHz 4pF 4pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
CF1 CF2
XT1 XT2
Rf
Rd
C1
CF
C2
C3
X’tal
C4
Figure 1 Main-clock circuit Figure 2 Sub-clock circuit
Ceramic oscillation circuit Crystal oscillation
No.6698-17/20
LC865632/28/24/20/16/12/08A
Power supply
VDD
VDD limit
OV
RES
Reset time
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Operation mode
Unfixed Reset Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
CF1, CF2
tmsCF
tssXtal
XT1, XT2
Operation mode
HOLD Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3 Oscillation stable time
No.6698-18/20
tCKO
tC
tICK tC
tC
tCKC
V
RES
SO0, SO1
SB0, SB1
SCK0
SCK1
SI0
SI1
LC865632/28/24/20/16/12/08A
VDD
RES
R
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has be en over inferior limit o f
supply voltage.
RES
C
Figure 4 Reset circuit
0.5VDD
<AC timing point>
Y
KL
<Timing>
KH
KI
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
DD
1K
50pF
<Test load>
No.6698-19/20
memo:
LC865632/28/24/20/16/12/08A
No.6698-20/20
PS
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