Sanyo LC865020B Specifications

Ordering number: EN 5650

LC865020B/16B/12B/08B

CMOS LSI

LC865020B/16B/12B/08B

8-Bit Single-Chip Microcontroller

Overview

The LC865020B/16B/12B/08B microcontrollers are 8-bit
single-chip microcontrollers with the following on-chip
functional blocks :

• CPU : Operable at a minimum bus cycle time of 0.5 µs

(microsecond)

• On-chip ROM capacity : Up to 20K bytes

• On-chip RAM capacity : 384 bytes
(LC865020B/16B/12B/08B)

• 16-bit timer/counter (or two 8-bit timers)

• 16-bit timer/PWM (or two 8-bit timers)

• 8-channel × 8-bit A/D converter

• Two 8-bit synchronous serial-interface circuits

• 13-source 10-vectored interrupt system

All of the functions above are fabricated on a single chip.

Features

(1) Read-Only Memory (ROM) :

LC865020B 20480 × 8 bits
LC865016B 16384 × 8 bits
LC865012B 12288 × 8 bits
LC865008B 8192 × 8 bits

Package Dimensions

unit : mm

3071-DIP64S

[LC865020B/16B/12B/08B]

57.2

0.95 0.48 1.78 1.01

unit : mm

3159-QFP64E

[LC865020B/16B/12B/08B]

17.2

14.0

17.2

1.6

14.0

1.0

1.0

1.0

48

49

64

1

0.8

0.35

1.0

33

32

17

16

3364

321

4.00.51min

SANYO : DIP64S

1.6

0.15

0.8

0.1

2.7

3.0max

5.0max

3.2

19.5

16.8

0.25

(2) Random Access Memory (RAM) :

LC865020B/16B/12B/08B 384 × 8 bits

SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep.

unit : mm

3190-SQFP64

1.25 0.5 1.250.18

10.0

12.0

15.6

0.8

SANYO : QFP64E

[LC865020B/16B/12B/08B]

12.0

10.0

0.15

48

49

1.25

0.5

64

116

1.25

33

32

17

1.7max

0.1

0.5

0.5

SANYO : SQFP64

O3097HA (II)

No. 5650-1/21

LC865020B/16B/12B/08B

(3) Bus cycle time / Instruction cycle time

The LC865020B/16B/12B/08B microcontrollers are constructed to read ROM twice within one instruction cycle. This results
in 1.7 times better performance within the same instruction cycle compared to our 4-bit microcontrollers (the LC66000 series).
Bus cycle time indicates the speed to read ROM.

Bus cycle time Cycle time System clock oscillation Oscillation frequency Supply voltage

0.5 µs1 µs Ceramic resonator 12 MHz 4.5 to 6.0V
2 µs4 µs Ceramic resonator 3 MHz 2.7 to 6.0V

7.5 µs 15 µs RC oscillator 800 kHz 2.7 to 6.0V

183 µs 366 µs Crystal oscillator 32.768 kHz 2.7 to 6.0V

(4) Ports

- Input/output ports : 6 ports (42 pins)
Input/output port programmable in nibble units : 1 port (8 pins)
(However, when N-channel open-drain output is selected, bit-unit input is possible.)
Input/output port each bit programmable : 5 ports (34 pins)
Include 15 V withstand N-channel open drain output port : 3 ports (18 pins)

- Input ports : 2 ports (13 pins)

(5) A/D converter

- 8-channel × 8-bit A/D converter

(6) Serial-interface

- Two 8-bit serial-interface circuits
LSB first / MSB first functions switchable

- Internal 8-bit band-rate generator in common with two serial-interface circuits

(7) Timer

- Timer 0
16-bit timer/counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with programmable prescaler
Mode 3 : 16-bit counter

The resolution of Timer is fixed to tCYC. (tCYC : cycle time)

- Timer 1
16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9 to 16 bits)

In Mode 0 and Mode1, the resolution of Timer and PWM is fixed to tCYC.
In Mode 2 and Mode 3, the resolution of Timer and PWM can be programmed to be tCYC or 1/2 tCYC

- Base timer
Every 500 ms overflow system for clock applications (using 32.768 kHz crystal oscillator for Base timer clock)
Every 976 µs, 3.9 ms, 15.6 ms, 62.5 ms overflow system (using 32.768 kHz crystal oscillator for Base timer clock)

- Base timer clock selectable

32.768 kHz crystal oscillator, system clock, and programmable prescaler output of Timer 0

No. 5650-2/21

LC865020B/16B/12B/08B

(8) Buzzer output

- The buzzer sound frequency is selectable ; 4 kHz, 2 kHz (using 32.768 kHz crystal oscillator for base timer clock)

(9) Remote-controlled receiver circuit (shares P73/INT3/T0IN pin)

- Noise rejection function

- Polarity switching

(10) Watchdog timer

- RC external watchdog timer

- Watchdog timer operation can be selected : Interrupt/reset

(11) Interrupt system

- 13-source 10-vectored interrupts :

1. External interrupt INT0 (including watchdog timer)

2. External interrupt INT1

3. External interrupt INT2, Timer/counter T0L (lower 8 bits)

4. External interrupt INT3, base timer

5. Timer/counter T0H (upper 8-bits)

6. Timer T1L, timer T1H

7. Serial-interface SIO0

8. Serial-interface SIO1

9. A/D converter

10. Port 0

- Built-in interrupt priority control register
Microcontroller supports 3 levels of multiple interrupt; low level, high level, and highest level. For the 11 interrupt requests
from INT2 through Port 0, high/low level interrupt priority can be specified using the priority control register. Also, for
INT0 and INT1, highest/low level interrupt priority can be specified.

(12) Real-time service operation

Synchronizing with the interrupt request signals, the real-time service starts a 4-byte data transfer between which special
function registers within 1-instruction cycle after the request signal occurs, and then completes its operation within
5-instruction cycles. This operation is performed in parallel with CPU operation.

(13) Subroutine stack

- 128 levels (Max.) : The stack is located in RAM.

(14) Multiplication and division

16 bits × 8 bits (7-instruction cycles)
16 bits / 8 bits (7-instruction cycles)

(15) 3 oscillation circuits

- On-chip RC oscillator circuit for the system clock

- On-chip CF oscillator circuit for the system clock

- On-chip crystal oscillator circuit for the system clock and the time-base clock
XT1 pin can be used as P74.

No. 5650-3/21

LC865020B/16B/12B/08B

(16) Standby function

- HALT mode
HALT mode is used to reduce power dissipation. In this mode, program execution is stopped. This mode can be released by
an interrupt request signal or initial system reset request signal.

- HOLD mode
The HOLD mode is used to stop all oscillators RC (internal), CR and Crystal. This mode can be released by the following
operations

• Set Low level to Reset pin (RES).

• Set predefined level to P70/INT0, P71/INT1 pins (programmable).

• Set Low level to Port 0 pin/pins (programmable).

(17) Factory shipment

• DIP64S , QFP64E , SQFP64 delivery form

(18) Development support tools

Evaluation (EVA) chip : LC866098
EPROM version : LC86E5032
One time ROM version : LC86P5032
Emulator : EVA-86000 + ECB866600 (Evaluation chip board)

+ POD865000 (POD for DIP64S)
+ POD865010 (POD for QFP64E)

No. 5650-4/21

Pin Assignments

DIP64S

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

P16/BUZ
P17/PWM

TEST1

RES

XT1/P74

XT2
VSS

V

CF1
CF2
VDD

V

P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6

P87/AN7
P70/INT0
P71/INT1

P72/INT2/T0IN
P73/INT3/T0IN

P30
P31
P32
P33

LC865020B/16B/12B/08B

1
2
3
4
5
6
7
8

9
10
11
12
13

SS

14
15

DD

16
17
18
19
20
21
22
23

24

25

26

27

28

29

30

31

32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P07
P06
P05
P04
P03
P02

P01
P00
P27
P26
P25

P24
P23
P22
P21
P20
VDDVPP

VDDV

VSS

V

SS

P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34

PP

Top view

No. 5650-5/21

QFP64E

TEST1

RES

XT1/P74

XT2
VSS
CF1
CF2

VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5

P86/AN6
P87/AN7

LC865020B/16B/12B/08B

P00

P01

P02

P03

P04

P05

P06

P07

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

P16/BUZ

P17/PWM

48

49

46

47

50
51
52

V

V

53

SS

54
55
56

DD

57
58
59
60
61
62
63

123456789

64

45

42

43

44

39

40

41

10

38

121314

11

36

37

35

32

P27

33

34

31
30
29
28
27
26
25
24
23
22
21
20
19
18

15

17

P26
P25
P24
P23
P22
P21
P20
VDDVPP

VDDV

PP

VSS

V

SS

P51
P50
P47
P46
P45
P44

16

SQFP64

TEST1

RES
XT1/P74

XT2

VSS

V

CF1

CF2

VDD

V

P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5

P86/AN6
P87/AN7

P30

P31

P32

P33

P34

P35

P36

P37

P40

P41

P42

P43

P71/INT1

P70/INT0

Top view

P72/INT2/T0IN

P73/INT3/T0IN

P00

P01

P02

P03

P04

P05

P06

P07

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

P16/BUZ

P17/PWM

48

47

44

45

46

49
50
51
52
53

SS

54
55

DD

56
57
58
59
60
61
62
63

123456789

64

40

41

42

43

36

35

37

38

39

12

13

10

11

14

32

33

34

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

15

P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP

VDDV

PP

VSS

V

SS

P51
P50
P47
P46
P45
P44

16

P71/INT1

P70/INT0

P72/INT2/T0IN

P30

P31

P32

P33

P73/INT3/T0IN

P34

P35

P36

P37

P40

P41

P42

P43

Top view

No. 5650-6/21

System Block Diagram

LC865020B/16B/12B/08B

IR PLA

Base timer

SIO0

SIO1
Timer 0
Timer 1

Bus

Interrupt control
Stand-by control

CF
RC

Clock
generator

X tal

Bus interface

Port1
Port7
Port8
Port2

Bus

ROM

PC

ACC
B register
C register

ALU

ADC

INT0 to 3

Noise rejection

filter

Real time

service

RAM

(128 bytes)

Port3
Port4

PSW

Port5

RAR

RAM

Stack pointer

PORT 0

Watchdog timer

No. 5650-7/21