The LC863264/56/48/40A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424µs
- On-chip R O M capaci ty
Program ROM : 64K/56K/48K/40K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 640 bytes
- OSD RAM : 352 × 9 bits
- Closed-Caption TV controller and the on-screen display controller
- Closed-Caption data slicer
- Four channels × 8-bit AD Converter
- Three channels × 7-bit PWM
- Two 16-bit timer/counters, 14-bit base timer
- 8-bit synchronous serial interface circuit
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 16-sourc e 10-vect o red interrupt system
- Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function
All of the above functions are fabricated on a single chip.
CMOS IC
Ver.0.91
51299
91400 RM (IM) HS No.6694-1/20
LC863264/56/48/40A
Features
(1) Read-Only Memory (ROM) : 65024
40960
16128
8 bits / 57344
×
8 bits for program
×
8 bits for CGROM
×
8 bits / 49152
×
8 bits
×
(2) Random Access Memory (RAM) : 640 × 8 bits (including 128 bytes for ROM correction function)
352
- RAM : 352 words (9 bits per word)
Display area : 36 words × 8 lines
Control area : 8 words × 8 lines
- Characters
Up to 252 kinds of 16 × 32 dot character fonts
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts :
a 16 × 17 dot and 8 × 9 dot character font
At least 111 characters need to be divide to display the caption fonts.
- Various character attributes
Character colors : 16 colors
Character background colors : 16 colors
Fringe / shadow colors : 16 colors
Full screen colors : 16colors
Rounding
Underline
Italic character (slanting)
- Attribute can be changed without spacing
- Vertical display start line number can be set for each row independently (Rows can be overlapped)
- Horizontal display start position can be set for each row independently
- Horizontal pitch (bit 9 - 16)
*1
and vertical pitch (bit-32) can be set for each row independently
- Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode
- Input / Output Ports : 5 ports (28 terminals)
Data direction programmable in nibble units : 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually : 4 ports (20 terminals)
No.6694-2/20
LC863264/56/48/40A
(7) AD converter
- 4 channels × 8-bit AD converters
(8) Serial interfaces
- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
- Synchronous 8-bit serial interface
(9) PWM output
- 3 channels × 7-bit PWM
(10) Timer
- Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution o f timer is 1 tCYC.
- Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8- bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1,the re solution of Ti mer1/PWM is 1 tC YC
In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC
- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
(11) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switching
(12) Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
- Interrupt prior ity control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.
(15) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(16) Multiplication/division instruction
- 16 bits × 8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(17) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X’tal oscillation circuit used for base timer, system clock and PLL reference
(18) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
Pull the reset terminal (
•
Feed the selected level to either P70/INT0 or P71/INT1.
•
Input the interrupt condition to Port 0.
•
) to low level.
RES
(19) Package
- DIP42S
- QIP48E
(20) Development tools
- Flash EEPROM: 2 Flash microcontrollers are available:LC86F3264A,LC86F3248A. Flash version is different