Sanyo LC8390M Specifications
Ordering number : EN4454A
O3098HA (OT)/92194TH (OT)/92093JN B8-0036 No. 4454-1/12
LC8390M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
16-Bits A/D and D/A Converters
for Digital Audio Systems
CMOS LSI
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC8390M combines two-channel D/A and A/D
converters in a single chip.
Features
• A/D Converter Block
— Quadratic ∆Σmodulation
— 16-bits resolution
— Built-in aliasing noise prevention digital filter
— A/D converters for two channels built in
(synchronized input when standard audio output is
used)
— S/N = 80 dB, THD + N = 0.025% (typical, A-
compensation filter used)
— Digital output: MSB first, forward packed, bit clock
rates of 32, 48, and 64 Fs
— External integrator used.
• D/A Converter Block
—16×oversampling quadratic noise shaper + PWM
— 16-bits resolution
— D/A converters for two channels built in
(synchronized output)
— S/N = 85 dB, THD + N = 0.03% (typical, A-
compensation filter used)
— Digital input: MSB first, backward packed, bit clock
rates of 32, 48, and 64 Fs
— Digital oversampling filters are not built in.
• Built-in double-buffering serial I/O circuits. (These
circuits support both standard audio I/O and I/O with
arbitrary timing.)
• Sampling frequencies of 48, 44.1, and 32 kHz
• Master clock: 512 Fs (24.576 MHz when fs = 48 kHz)
or 384 Fs
Notes: Only the A/D converters operate when 384 Fs is
selected as the master clock. The D/A
converters do not operate in this mode.
Since the analog I/F and analog power supply
pins are more susceptible to damage from static
electricity than the other pins, extra care is
required.
Analog I/F pins: DZOUTL, ADL2, ADLVSS,
ADLVDD, ADL3, DZOUTR, ADR2, ADRVSS,
ADRVDD, ADR3, DALVSS, PWML, DALVDD,
DARVSS, PWMR, DARV
DD
• Package: 30-pin MFP
• Power supply: 5 V, single voltage, CMOS
Package Dimensions
unit: mm
3073A-MFP30S
[LC8390M]
SANYO: MFP30S
Pin Assignment
Block Diagram
No. 4454-2/12
LC8390M
Pin Functions
No. 4454-3/12
LC8390M
Block Pin No. Pin I/O Function
A/D block 5 ADLV
DD
— Analog left channel A/D power supply
3 ADLV
SS
— Analog left channel A/D ground
4 ADL1 I Left channel A/D audio input
2 ADL2 O Left channel A/D linear ∆Σ output
6 ADL3 O Left channel A/D quadratic ∆Σ output
11 ADRV
DD
— Analog right channel A/D power supply
9 ADRV
SS
— Analog right channel A/D ground
10 ADR1 I Right channel A/D audio input
8 ADR2 O Right channel A/D linear ∆Σ output
12 ADR3 O Right channel A/D quadratic ∆Σ output
26 ADLRCK I A/D left and right channel clock input
25 ADBCK I A/D bit clock input
24 ADDATA O A/D data output
1 DZOUTL O A/D dithering clock output
7 DZOUTR O A/D dithering clock output
D/A block 15 DALV
DD
— Analog left channel D/A power supply
13 DALV
SS
— Analog left channel D/A ground
14 PWML O Left channel D/A PWM output
18 DARV
DD
— Analog right channel D/A power supply
16 DARV
SS
— Analog right channel D/A ground
17 PWMR O Right channel D/A PWM output
21 DALRCK I D/A left and right channel clock input
20 DABCK I D/A bit clock input
22 DADATA I D/A data input
Control and other pins 30 DV
DD
— Digital system power supply
19 DV
SS
— Digital system ground
23 CLKIN I Master clock input
28 CLKCTL I Master clock selection (high: 512 Fs, low: 384 Fs)
27 RESET I Reset input
29 TEST I Test input. (This pin must be connected to DV
DD
during normal operation.)
Pin Types
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
No. 4454-4/12
LC8390M
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max –0.3 to +7.0 V
Maximum output voltage V
O
max –0.3 to VDD+ 0.3 V
Maximum input voltage V
IN
max –0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max Ta = –30 to +70°C 200 mW
Operating temperature Topr –30 to +70 °C
Storage temperature Tstg –40 to +125 °C
Specification Circuit Pin
TTL output ADDATA
Analog output PWML, PWMR
ADL2, ADL3, DZOUTL, ADR2, ADR3, DZOUTR
Schmitt input TEST, CLKCTL, ADLRCK, ADBCK, CLKIN,
DADATA, DALRCK, DABCK
Analog input ADL1, ADR1
Built-in pull-up resistor input RESET
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