Sanyo LC82C55 Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

Programmable Peripheral Interface

Ordering number:ENN2721

LC82C55

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC82C55 Programmable Peripheral Interface IC is a
pin-compatible CMOS version of the industry-standard
8255 device.
The 24 input/output pins may be programmed to operate in
3 different modes. Basic input/output, strobed input/out­put, and bi-directional input/output modes are available.
All inputs and outputs are fully TTL compatible, and the
device is easily interfaced to standard microprocessors.
The LC82C55 is fabricated using a Si-gate CMOS process
for low operating and standby power consumption.
The LC82C55 operates on a single 5V power supply and is
available in standard 40-pin plastic DIP packages.

Features

• 24 programmable input/output pins.

• Flexible input/output modes.

• Individual bit set/reset capability.

• Compatible with standard microprocessors.

• Zero wait-state operation with an 8MHz CPU. (TRD =
120ns)

• Fully TTL compatible IOL = 2.5mA.

• Low-power CMOS process.

• Single 5V power supply.

Package Dimensions

unit:mm

3013A-DIP40

[LC82C55]

40

1

2.47 2.54

Pin Assignment (Top view)

53.2

0.5

1.2

21

13.8

15.24

20

4.25

5.2max

4.1

0.51min

SANYO : DIP40

0.25

91001TN (KT)/4058TA,TS No.2721–1/16

LC82C55

Specifications

Absolute Maximum Ratings at VSS = 0V

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DC Recommended Operating Conditions at Ta = –20 to +75˚C, VSS = 0V

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Electrical Characteristics(1)
DC Characteristics at Ta = –20 to +75˚C, VDD = 5V ± 10%, VSS = 0V

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DD

NI

DD

V

LI

V

HI

I

LO

LO

IHO=– Aµ0044.2V

HO

VNIV=

LI

V

LFO

1 01Am

DD

2 01Aµ

DD

NI

f

c

O/I

%01±V5=–8.0+ot3.0V

DD

%01±V5=ot0.2VDD3.0+V

DD

Am5.2= 54.0V

V0ot01±Aµ

DD

V=

TUO

V0ot01±Aµ

DD

–ot3.0VDD3.0+V

˚C
˚C

5.5ot5.4V

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02Fp

Electrical Characteristics(2)
AC Characteristics at Ta = –20 to +75˚C, VDD = 5V ± 10%, VSS = 0V

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DRerofebdilavataD ↓ t

DRretfadilavataD ↑ t

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RWerofebelbatssserddA ↓ t

RWretfaelbatssserddA ↑ t

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RWerofebdilavataD ↑ t

RWretfadilavataD ↑ t

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RWretfatuptuO ↑ t

DRerofebdilavatadtroP ↓ t

DRretfadilavatadtroP ↑ t

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BTSerofebdilavatadtroP ↓ t

BTSretfadilavatadtroP ↑ t

KCAretfatuptuO ↓ t

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RA
AR

RR

C

DR
FD

t

VR

WA

AW

WW

WD

DW

t

VR

BW

RI

RH
KA
TS
SP
HP
DA
DK

Fp051= 021sn

L

C

C

C
C

R,Fp02=

L

L

L
L

k2= Ω 0158sn

L

Fp051= 053sn

Fp051= 003sn

R,Fp02=

k2= Ω 02052sn

L

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0sn
0sn

061sn

002sn

0sn
0sn

021sn
001sn

0sn
002sn

0sn
0sn
003sn
053sn
0sn
051sn

Continued on next page.

tinU

No.2721–2/16

Continued from preceding page.

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RWretfa0=FBO ↑ t

KCAretfa1=FBO ↓ t

BTSretfa1=FBI ↓ t

DRretfa0=FBI ↑ t

DRretfa0=RTNI ↓ t

BTSretfa1=RTNI ↑ t

KCAretfa1=RTNI ↑ t

RWretfa0=RTNI ↓ t

AC Test Input Waveform

Input/Output Waveforms
Mode 0 (Basic Input Mode)

LC82C55

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BOW

BOA

BIS

BIR
TIR
TIS
TIA

TIW

Fp051= 003sn

L

C

Fp051= 053sn

L

C

Fp051= 003sn

L

C

Fp051= 003sn

L

C

Fp051= 004sn

L

C

Fp051= 003sn

L

C

Fp051= 053sn

L

C

Fp051= 054sn

L

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Mode 0 (Basic Output Mode)

Mode 1 (Strobed Input Mode)

No.2721–3/16

Mode 1 (Strobed Output Mode)

Mode 2 (Bi-directional Bus Mode)

LC82C55

Note

INTR = IBF · MASK · STB · RD + OBF · MASK · ACK · WR

No.2721–4/16

Block Diagram

LC82C55

Description of Operation

RD (read control input)

When Low, data or status word is transferred from the LC82C55 to the CPU via the data bus.

WR (write control input)

When Low, a data or control word is written from the CPU to the LC82C55.

A0, A1 (port address inputs)

Used to select Ports A, B and C, and the control register. Normally, the least significant 2 bits of the address bus are
connected to these pins.

RESET input

A High level on this input clears the control register. All ports are set to the input mode (high-impedance state).

CS (chip select input)

A Low level on this input enables communication between the LC82C55 and CPU . W hen High, the data b us remains in
the high-impedance state and control signals from the CPU are ignored.

Read/write control logic

This block performs the transfer of data and control words between the CPU and the internal circuitry. It receives data
via the CPU interface signals and data bus, and issues commands to the port control logic.

Data bus buffer

This 8-bit, tri-state, bi-directional bus buffer interfaces the external 8-bit data bus to the LC82C55. Data control, and
status information is transferred under the control of the CPU.

Group A/Group B control

Ports A, B and C are divided into the control Groups A and B, each with its own control circuitry. Group A consists of
Port A and the upper 4 bits of Port C; Group B consists of port B and the lower 4-bits of Port C.
The control register is write-only.

Ports A, B and C

The operating mode of each 8-bit port is set by the CPU system software. Port A has an output latch/b uffer and an input
latch.
Port B has an input/output latch/buffer and an input buffer.
Port C has an output latch buffer and input buffer, and can be divided into two 4-bit ports using mode control. Each 4­bit port can be used as status and control signals for Ports A and B.

No.2721–5/16