Sanyo LC8213 Specifications
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CMOS IC
Image Data Compression/Expansion Processor
Ordering number:ENN*4605
LC8213
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Overview
The LC8213 is an IC that compresses (codes) and expands
(decodes) binary image data used for facsimiles, etc. This
LC8213 can be used in office automation equipment such
as G3/G4 facsimiles, image file systems, digital photocopiers, and workstations.
The coding method is based on the MH (Modified
Huffman), MR (Modified Relative Element Address Designate), and MMR (Modified MR) coding methods regulated by CCITT T.4 and T.6.
Features
• CCITT T.4 and T.6 MH, MR, MMR coding methods.
• Compatible with G3 and G4 facsimiles.
• No. of main scanning direction pixels Max. 64k bits.
• Line skip mode.
• 8/16 bit image memory bus, 8-bit CPU bus.
• Transfer of data between CPU bus and image memory
bus.
• DMA transfer function between image memory and I/O
device.
• System clock Max. 20MHz.
• CMOS low power dissipation.
Package Dimensions
unit:mm
3174-QIP80E
[LC8213]
23.2
0.35
20.0
21.6
17.2
0.8 0.8
1.0
64
65
0.8
14.0
80
1.6
124
1.6
0.15
41
40
25
3.0max
2.7
0.8
SANYO : QIP80E
15.6
0.8
Specifications
Absolute Maximum Ratings at Ta = 25˚C, VSS = 0V
retemaraPlobmySsnoitidnoCsgnitaRtinU
egatlovylppusmumixaMV
egatlovtuptuo/tupnIV
noitapissidrewopelbawollAxamdPaT ≤ 07°C 053Wm
erutarepmetgnitarepOrpoT –07+ot03
erutarepmetegarotSgtsT –521+ot55
tsniagaecnatsiseR
taehredlos
redloslaunaMsdnoces3 053
wolfeRsdnoces01 532
xam –0.7+ot3.0V
DD
IV,O
80101TN (KT)/82093JN (KOTO) No.4605–1/10
–Vot3.0
3.0+V
DD
˚C
˚C
˚C
˚C
LC8213
Allowable Operating Ranges at Ta = –30 to +70˚C, VSS = 0V
retemaraPlobmySsnoitidnoC
egatlovylppuSV
egnaregatlovtupnIV
DC Characteristics at Ta = –30 to +70˚C, VSS = 0V, VDD = 4.5 to 5.5V
retemaraPlobmySsnoitidnoC
egatlovlevel-hgihtupnIV
egatlovlevel-woltupnIV
tnerrucegakaeltupnII
egatlovlevel-hgihtuptuOV
egatlovlevel-woltuptuOV
tnerrucegakaeltuptuOI
ycneuqerfnoitallicsOf
tnerrucylppuSI
AC Characteristics Clock Reset Timing
retemaraPlobmySsnoitidnoC
emitelcyckcolCKLCt05sn
htdiwlevel-wolkcolCLKCt51sn
htdiwlevel-hgihkcolCHKCt51sn
htdiweslupteseRWTSRtKLCt6sn
DD
NI
HI
LI
VNIV=SSV,
L
IHO=– Am34.2V
HO
I
LO
LO
ZO
DD
KLC 02zHM
CSO
elbitapmocLTT2.2V
elbitapmocLTT 8.0V
DD
Am3= 4.0V
sgnitaR
nimpytxam
5.40.55.5V
0V
sgnitaR
nimpytxam
–5252+Aµ
tuptuoecnadepmihgihgniruD–001001+Aµ
5103Am
sgnitaR
nimpytxam
DD
tinU
V
tinU
tinU
CPU Interface
emitdlohKCADHADt01sn
retemaraPlobmySsnoitidnoC
emitputessserddASAt02sn
emitdlohsserddAHAt01sn
htdiweslupdaeRWRt001sn
emityaledataddaeRDRt 001sn
emitdlohataddaeRHRt01sn
htdiweslupetirWWWt001sn
emitputesatadetirWSDt02sn
emitdlohatadetirWHWt01sn
emitputesKCADSADt02sn
emityaledQERDQRDt
nimpytxam
sgnitaR
07+KLCt2
tinU
sn
No.4605–2/10
LC8213
Image Memory Interface
retemaraPlobmySsnoitidnoC
NEA ↓ emityaledLEAt 07sn
NEA ↑ emityaledHEAt 07sn
TSA ↑ emityaledHSAt 07sn
TSA ↓ emityaledLSAt 07sn
emityaleddilavlangislortnoCVWRt 07sn
emityaleddilavnilangislortnoCHWRt 07sn
DROI,DRM ↓ emityaledLDRt 07sn
DROI,DRM ↑ emityaledHDRt 07sn
RWOI,RWM ↓ emityaledLRWt 07sn
RWOI,RWM ↑ emityaledHRWt 07sn
EDL,EDU ↓ emityaledLEDt 07sn
EDL,EDU ↑ emityaledHEDt 07sn
NEDM ↓ emityaledLDMt 07sn
NEDM ↑ emityaledHDMt 07sn
emityaleddilavsserddAVAMt 001sn
emitdlohsserddAHAMt52sn
emitputesataddaeRRSDt01sn
emitdlohataddaeRRHDt0sn
emityaledatadetirWWDDt 08sn
emitdlohatadetirWWHDt01sn
QERB ↑ QERDIrof(emityaled ↑ )HRBt
QERB ↓ emityaledLRBt
KCADI ↓ KCABrof(emityaled ↓ )DCADt
KCADI ↓ KLCrof(emityaled ↑ )LCADt 07sn
KCADI ↑ emityaledHCADt 07sn
CTD ↑ emityaledHCTDt 07sn
CTD ↓ emityaledLCTDt 07sn
emitputesYDAERSYDRt03sn
emitdlohYDAERHYDRt03sn
nimpytxam
02+KLCt207+KLCt4
02+KLCt3
sgnitaR
tinU
sn
07
sn
07+KLCt31
sn
Block Diagram
No.4605–3/10
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