The LC7986C is a low-power CMOS IC that incorporates
dot-matrix character generator, display controller and
driver functions in a single device, and realizes ideal for
use in portable equipment containing LCD displays.
Also, the CMOS process realizes easy expansion to control displays of up to 80 characters by adding LC7930N or
LC7931D display drivers.
Pad Layout
Chip size: 5.69 × 3.45mm
2
Features
• Controller and driver for dot-matrix LCD displays
• 5 × 7-pixel and 5 × 10-pixel character fonts
• 160, 5 × 7-pixel characters and 32, 5 × 10-pixel characters in character generator ROM
• Eight, 5 × 7-pixel characters or four, 5 × 10-pixel characters in character generator RAM
• 80-character display data RAM
• Built-in drivers for 1-line × 16-character and 2-line ×
16-character displays
• Easy expansion to 1-line × 80-character or 2-line × 40character displays by adding LC7930Ns or LC7931Ds
• 4-bit or 8-bit microcontroller interface
• 11 microcontroller instructions
• Built-in reset circuit
• Built-in oscillator
• 5V supply
• 128-pad dice
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
70197HA (ID) / D082JN No. 4101—1/32
−
Pad Coordinates
The coordinate origin is in the center of the chip.
Using Rf = 56kΩ ± 3%220320420
Using built-in Vf–320–
Ratings
RC oscillator built-in resistanceVfOSCO to OSCR–56–k
V
LCD display voltage
Voltage divider step resistanceV
Note: *1. V
Note: *2. V
is the voltage from VDD, V1, V4 and V5 to the LCD common drive pins OC1 to OC16.
COM
is the voltage from VDD, V2, V3 and V5 to the LCD segment drive pins OS1 to OS80.
SEG
LCD1
V
LCD2
R
Switching Characteristics at Ta = −20 to +75°C, V
ParameterSymbolConditions
E cycle timet
E high-level pulsewidtht
E rise timet
E fall timet
RS and R/W to E setup timet
E to RS and R/W address hold timet
DB0 to DB7 to E data setup timet
Write cycle E to DB0 to DB7 data hold
time
Read cycle E to data valid delay timet
Read cycle E to DB0 to DB7 data hold
time
CP low-level pulsewidtht
CP high-level pulsewidtht
CP to LOAD setup timet
D to CP data setup timet
CP to D data hold timet
LOAD to M delay timet
ECYC
EW
ER
EF
SU
AH
DSU
t
DHW
DD
t
DHR
WL
WH
CSU
DSU
DH
DM
VDD − V5 (1/5 bias)4.6–6V
VDD − V5 (1/4 bias)3.0–6V
Between V(n) and V(n+1)–2.2–k
= 0V, VDD = 5V ± 10%
SS
Ratings
mintypmax
1000––ns
450––ns
––25ns
––25ns
140––ns
10––ns
195––ns
10––ns
See measurement circuit.––320ns
20––ns
800––ns
800––ns
500––ns
300––ns
300––ns
−
1000–1000ns
Unit
kHz
Ω
Ω
Unit
Reset characteristics at Ta = −20 to +75°C
ParameterSymbolConditions
VDD rise timet
VDD off timet
DDR
DDOFF
Ratings
mintypmax
1–100
Unit
µ
s
1––ms
No. 4101—5/32
LC7986C
Clock Generator
The internal oscillator that generates the clock for the internal circuit requires an external feedback resistor, connection of
the internal feedback resistor or an external clock input as shown in the following sections.
External clock
The input duty cycle should be between 45 and 55% as shown in the following figure.
External feedback resistor
Internal feedback resistor
Measurement Circuit
T
h
Note.
Note. The resistor should be mounted as close as possible to OSCI and OSCO.
Duty
-----------------
ThT1+
×=
100%
Note. R
= 2.4kΩ, C = 130pF, R = 11k
L
Ω
No. 4101—6/32
Read/write cycle timing
LC7986C
LC7930N interface timing
Power Supply
No. 4101—7/32
LC7986C
Pin Description
NameNumI/OConnect toFunctions
RS1IMPUData register or instruction register select input. Data register when "1" and instruction register when "0".
R/W1IMPURead or write select input. Read when "1" and write when "0".
E1IMPUExecution start input
DB7 to DB44I/OMPU
DB3 to DB04I/OMPU
LOAD1OLC7930ND serial data shift latch output
CP1OLC7930ND serial data shift clock output
M1OLC7930NDisplay expansion drive signal inversion control signal output
D1OLC7930NDisplay expansion serial data output. Nonselected when "0" and selected when "1".
OC1 to OC1616OLCD
OS1 to OS8080OLCDLCD segment driver outputs
V1 to V55sourceLCD driver reference voltage inputs
, GND2sourceVDD : +5V, GND : 0V
V
DD
OSCI2Oscillator feedback resistor connection and external clock input
OSCO2Oscillator external feedback resistor connection
OSCR1OSCOInternal feedback resistor connection. Connect to OSCI or leave open.
SHL1I
A/B1IM output signal type select input. A-type when "1" and B-type when "0".
V1’ to V5’5IVDD to V4LCD drive voltage internal voltage divider outputs. Leave open if the the voltage divider is not used.
4-bit microcontroller interface data bus and 8-bit microcontroller interface high-order four bits data bus
connections. DB7 can also be used as busy flag.
8-bit microcontroller interface low-order four bits data bus connections. No connection when 4-bit interface
size is selected.
LCD common driver outputs. OC9 to OC16 and OC12 to OC16 are unselected in 1/8 duty and 1/11 duty
respectively.
Segment output shift direction select input. Shift right (OS1 to OS80) when"1", and shift left (OS80 to OS1)
when "0".
No. 4101—8/32
Functional Description
Registers
LC7986C
The LC7986C has two 8-bit registers—instruction register
(IR) and data register (DR)—that are selected as shown in
the following table.
RSR/WOperation
00IR write, instruction execution
01Busy flag (DB7) and address counter (DB0 to DB6) output
10DR write, internal DR to DD RAM or CG RAM data transfer
11DR read, internal DD RAM or CG RAM to DR data transfer
The instruction register is write-only. It contains instruction codes or DD RAM and CG RAM addresses written
by the microcontroller.
Busy Flag
When busy flag is 1, the previous instruction is executing,
and when 0, the instruction has completed. The next
instruction cannot be received until BF is 0. The microcontroller should, therefore, confirm that BF is 0 before writing the next instruction.
Display Data RAM (DD RAM)
The data register holds data read from or written to either
DD RAM or CG RAM. Data written to the data register by
the microcontroller is automatically transferred to the current DD RAM or CG RAM address. Data read from
DD RAM or CG RAM is buffered in the data register.
When the microcontroller writes a DD RAM or CG RAM
address to the instruction register, the data at that address
is copied into the data register. The microcontroller then
reads the data in the data register to complete the transfer.
Once that data is read, the data from the next DD RAM or
CG RAM address is copied into the data register in preparation for the next data read.
Address Counter
The address counter is used for both the DD RAM and the
CG RAM. The address output on DB0 to DB7 is the
counter value before the currently executing instruction
began.
The display data RAM stores 80, 8-bit character codes, and the LC7986C can display a maximum of 80 characters. The
address counter contains the location for the next display memory read or write operation as shown in the following figure.
Display data addresses are in hexadecimal. For example, the address counter contents for location 4E are shown in the
following figure.
To prevent undesirable effects such as display flicker during DD RAM accesses, the internal memory and the microprocessor interface have separate timing signals.
Single-line display mode (N = 0)
The DD RAM addresses and their corresponding display positions for an 80-character display are shown in the following
figure.
No. 4101—9/32
LC7986C
A single LC7986C, however, can drive 16 characters. The display positions and DD RAM addresses for an unshifted 16character display are shown in the following figure.
The DD RAM addresses following left and right display shifts are shown in the following figure. Note that the displayed
characters wrap around from addresses 4FH to 00H.
An LC7986C and a single LC7930N can drive a 16-character display. The display positions and DD RAM addresses for
an unshifted display are shown in the following figure.
The DD RAM addresses following left and right display shifts are shown in the following figure.
The number of displayed characters can be increased by adding more LC7930Ns. An LC7986C and eight LC7930Ns can
drive an 80-character display as shown in the following figure.
No. 4101—10/32
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