The LC7940YC and LC7941YC are segment driver ICs
for driving large, dot–matrix LCD displays. They read 4
bit parallel or serial input, display data from a controller
into an 80–bit latch, and then generate LCD drive signals
corresponding to that data.
The LC7940YC and LC7941YC feature mirror–image pin
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YC common driver to drive large LCD panels.
CMOS IC
LC7940YC,7941YC
Dot-matrix LCD Drivers
–
Features
• 80 built–in LCD display drive circuits
• 1/8 to l/128 display duty cycle
• Serial or 4–bit parallel data input
• Chip disable for low power dissipation for large–sized
panels
• Bias supply voltags can be supplied externally
• Operating supply voltage and ambient temperature
- 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C
- 8 to 20V LCD supply (V
–
VEE ) at Ta = –20 to
DD
+85 °C
• CMOS process
Specifications
The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package.
Absolute Maximum Ratings at Ta = 25 ± 2°C, V
ParameterSymbolRatingsUnit
Logic supply voltgeVDD max–0.3 to +7.0
LCD supply voltage, See Note below. VDD – VEE max0 to 22
Input voltageVI max –0.3 to VDD + 03
SS
= 0 V
V
V
°C
■ Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
■ SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63099RM (ID) No. 6157—1/13
ParameterSymbolRatingsUnit
Operating temperature range
Storage temperature range
Note
V
≥ V1 > V3 > V4 > V
DD
EE
LC7940YC, LC7941YC
T
opr
T
stg
–20 to +85
–40 to +125
°C
°C
Recommended Operating Condltions at Ta =
ParameterSymbolConditions
Logic supply voltageV
LCD supply voltageVDD – V
HIGH–level input voltage V
LOW–level inpvt voltageV
CP shift clock frequencyf
CP pulsewidtht
LOAD pulsewidtht
DIn and SDI to CP setup timet
DIn and SDI to CP hold timet
CP to LOAD time
LOAD to CP timet
CP rise timet
CP fall timet
LOAD rise timet
LOAD fall timet
DD
IH
IL
CP
WC
WL
SETUP
HOLD
t
CL1
t
CL2
LC
R
F
RL
FL
EE
See Notes 1 and 2.8–20
CP, CDl, DI1 to DI3, M,
SDl, P/S, DISPOFF and
LOAD
CP, CDI, Dl1 to DI3, M,
SDl, P/S,DISPOFF and
LOAD
–
20 to + 85°C, V
= 0V
SS
Ratings
mintypmax
2.7–5.5
Unit
V
V
0.8V
DD
––0.2V
100––
100––
80––
80––
0––
100––
100––
––50
––50
––50
––50
––
DD
–3.3
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1. V
≥ Vl > V3 > V4 > V
DD
EE
2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.
Electrlcai Characterfstlcs at Ta = 25 ± 2°C,V
ParameterSymbolConditions
HIGH–level input currentI
LOW–level input currentI
CDO HIGH–level output voltage V
CDO LOW–levef output voltageV
O1 to O80 driver ON resistanceRON
IH
IL
OH
OL
= 0V, VDD = 2.7 to 5.5 V
SS
Ratings
mintypmax
VIN =VDD; LOAD, CP, CDI,
P/S, DI1 to DI3, SDl, M,
––1
and DISPOFF
VIN = VSS; LOAD, CP,
CDl, P/S, DI1 to DI3, SDI,
–––1
M, and DISPOFF
IOH = –400 µAVDD – 0.4––
IOL = 400 µA ––0.4
VDD – VEE = 18 V,
|VDE – VO|= 0.25 V.
–24
See note
Unit
µA
µA
V
V
kΩ
No. 6157—2/13
LC7940YC, LC7941YC
ParameterSymbolConditions
CDI = VDD,
VDD to VSS standby supply currentI
ST
VDD – VEE = 18 V,
fCP = 3.3 MHz,
no output load ; V
SS
VDD – VEE = 18 V,
VDD to Vss operating supply currentI
SS
fCP = 3.3 MHz,
I
= 5.156 kHz,
LOAD
fM = 52 Hz ;VSS
VDD – VEE = 18V,
VDD to VEE operating supply currentI
CP input capacitanceC
EE
I
fCP = 3.3 MHz,
f
= 5,156 kHz,
LOAD
= 52 Hz ; V
f
M
EE
fCP = 3.3 MHz ; CP–5–
Note
V
= V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE)
l0081CPIDisplay data Input clock (falling–edge trigger).
9982CDII
9883LOADI
9784SDIISerial data input.
9685DI3
9586DI2
9487D11
SymbolI/OFunction
DD
SS
EE
Supply
1
3
4
Supply
V
– VSS is the logic supply.
DD
VDD – VEE is the LCD supply.
LCD panel drive voltage supplies
V1 and VEE are selected levels.
V3 and V4 are not–selected levels.
Chip disable.
Data is read in when LOW, and not road in when HIGH.
Display data latch clock (falling–edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
4–bit parallel data input pins.
Data inputLCD driver outputs
SDIO4O8
I
DI3O3O7O79
DI2O2O6O78
DI1O1O5O77
O80
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
No. 6157—7/13
LC7940YC, LC7941YC
Pin No.
LC7940YCLC7941YC
SymbolI/OFunction
9388MILCD panel drive voltage output alternation control signal.
8596P/SIData input mode select. 4–bit parallel input when HIGH, and serial input when LOW
8299CDOO
Cascade connection pin for extension segment drivers. Data is read out when HIGH.
Goes LOW after data is read out. Connected to the CDI input of the next chip.
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISP OFF
input as shown below.
MQDISP OFFOutput
LOWLOWHIGHV
1 to 8080 to 1Ol to O80O
LOWHIGHHIGHV
HIGHLOWHIGHV
HIGHHIGHHIGHV
××
LOWV
Note
x = don’t care (tied HIGH or LOW)
8497DISPOFF
I
O1 to O80 output control input pin.
When LOW, V1 is output on the O1 to 080 outputs, See the truth table.
8191NC
–No connection.8398NC
90100 NC
3
1
4
EE
1
No. 6157—8/13
Application Notes
LCD Panel 1
4
CP
SDI
LOAD
V3V1M
CP
LOAD
OD1 ED1
2
CP
SDI
LOAD
V3V1M
CP
SDI
LOAD
V3V1M
CP
SDI
LOAD
V3V1M
LC7940YC, LC7941YC
CP
SDI
LOAD
CDI
EE
V
VEE
V3
V4
V1
V4
LC7941YC
VEE
V4
VEE
V4
VEE
V4
(LC7940YC)
CDOCDI
LC7941YC
(LC7940YC)
CDOCDI
LC7941YC
(LC7940YC)
CDOCDI
LC7941YC
(LC7940YC)
M
EE
V
V3
V4
V1
M
EE
V
V3
V4
V1
M
EE
V
V3
V4
V1
M
1
2
159
160
161
162
319
320
321
322
LCD panel (640 × 200 pixels)
479
480
481
482
639
640
100
641
642
799
800
801
802
959
960
961
962
1119
1120
1121
1122
1279
1280
LC7940YC
LC7940YC
LC7940YC
LC7940YC
(LC7941YC)
M
(LC7941YC)
M
(LC7941YC)
M
(LC7941YC)
M
EE
V3
V
V1
V4
LC7941YC
EE
V3
V
V1
V4
LC7941YC
EE
V3
V
V1
V4
LC7941YC
EE
V3
V
V1
V4
LC7941YC
4
CP
LOAD
OD2 ED2
M
EE
V
4
V1 V3
V4
OD1
ED1
FLM
01
DI01
M
M
controller
064CP
DI064
LC7942YC
CL1
V2
V1
CL2
01
036CP
DI01
EE
4
V
V5
ED2
OD2
LC7942YC
M
VDD
EE
V2
V
V1
V5
V146V2
LA5311M
R
4
V3
V4
V5
+
–
+
+
–
+
–
R
–
R7RR
VEE
–11 to –13V
No. 6157—9/13
LCD Panel 2
LC7940YC, LC7941YC
42
4
24
EE
V4 V
MV1 V3
CP
LOAD
4bit Data
CDI
08001
CDO
CDICDO
08001
4bit Data
CP LOAD
LC7941YC-#1
EE
V3
V
V1
V4
M
24244
LC7941YC-#2LC7941YC-#1
24
LC7941YC-#2
24
LCD panel (640 × 200 pixels)
2
LC7941YC-#8
24
LC7941YC-#8
4bit Data
100
DI01
01
M
036CP
LC7942YC-#2
VDD
EE
V2
V
V1
V5
V146V2
LA5311M
R
V3
–
–
+
+
R
100
01
064CP
4
4bit Data
FLM
DI01
M
M
controller
LC7942YC-#1
CP
LOAD
EE
4
V
V1 V3
V4
EE
V
4
–11 to –13V
4
V4
V5
–
–
+
+
R
R
7R
No. 6157—10/13
LC7940YC, LC7941YC
100 x 240-pixel LCD Panel Application
A 100 × 240
pixel LCD panel requires the following
–
drivers.
• 3 x LC7940YC (or LC7941YC) drivers
• 2 x LC7942YC drivers
An example using l/l00 duty cycle is shown below.
Frame Signal
1,2
DI01 01
RS/LS 02
LC7942YC
#1
CP
M
063
DI064 064
DI01 01
RS/LS 02
LC7942YC
#2
CP
M
036
DI064
O37 to O64
are open.
1,1
2,1
--- ---
63,2
63,1
64,2
64,1
65,2
65,1
66,2
66,1
100,2
100,1
01
---
2,2
--- ---
---
---
---
02
LCD Panel (100 × 240 pixels)
100,79
1,79
1,80
64,80
65,80
100,80
079#1080
1,79
1,81
64,81
65,81
100,81
0102
(m,n) : pixel address
Segment line (n)
Common line (m)
1,82
---
---
---
100,82
---
1,160
64,160
65,160
100,160
080
1,
161
--- ---
64,161
65,161
1,240
---
2,240
--- ---
---
64,240
65,240
---
100,161
---
100,240
01
080
Data latch clock
Alternating signal
Serial Data
Data Shift
clock
P/S
LC7940YC
(LC7941YC)
DI1
DI2
DI3
SDICPLOAD
CDOCDI
1. The LC7942YC chips are cascaded by connecting
DIO64 on chip I to DIO1 on chip 2. For a 100
bit shift
–
register, O37 to O64 on chip 2 are left open.
2. The LC7940YC (or LC7941YC) chips are cascaded by
connecting CDO on chip I to CDI on chip 2, and CDO
on chip 2 to CDI on chip 3. CDI on chip I is tied to
GND, and CDO on chip 3 is not used. This
configuration allows the input of 240
If this timing data is sent, data elements (m, 229), (m,
230), (m+1, 229), (m+1. 230)... will not appear in the
output (O69 and O70 on chip 3). This is because the
LC7940YC (or LC7941YC) converts serial/parallel data
LOAD
SDI
m,1m,2,228m,229m,230m,231m,232
---
In this case, (m, 231) is output on O71 on chip 3, and (m,
232) on O72 on chip 3. However, these outputs are not
connected to the panel and are, therefore, invalid.
---
01070
LC7940YC
#3
in 4–bit units, which also decreases power dissipation . For
data that is not a multiple of 4, like 230, the following
scheme is used.
Dummy dataValid display data
Multiple of 4
■
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
■
semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.
■
In the event that any or all SANYO products(including technical data,services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the author ities concerned in accordance
with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
■
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
■
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.
■
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual proper ty rights or
other rights of third parties.
This catalog provides information as of June, 1999. Specifications and information herein are subject to
change without notice.
No. 6157—13/13
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