Sanyo LC7935AN Specifications

Ordering number:ENN3183A

CMOS IC

LC7935AN

General-Purpose 32-Bit Shift Register

Latch Driver

Features

•High-speed, high-voltage silicon gate CMOS device.

•Contains high-speed shiftable (5MHz max) 32-bit shift register, 32-bit latch, output driver on/off control circuit, 32-bit N-channel open drain output driver.

•Serial shift data is shifted on the positive transition of the clock (CLOCK).

•32-bit latch data is changed on the negative transition of the LATCH pad and is held on the positive transition.

•The STROBE pad, BEO pad can be used to exercise on/ off control of the output driver.

•Complete separation of logic circuit GND (1 pad) and thermal driver GND (4 pads).

•Maximum ratings of driver output: VO = 28V, IOL = 30mA.

•Logic unit operating voltage: VDD = 4.5 to 5.5V.

Package Dimensions

unit:mm

3057-QIP64A

[LC7935AN]

20.0

14.03.0

			1.0	0.8	0.35	1.0	0.15
	3.0	1.0	48			33
			49
							32
20.0	14.0	0.35
		0.8

			17
1.0	64
			2.45max
	1	16		2.15
	16.6		1.7	SANYO : QIP64A

Specifications

Absolute Maximum Ratings at Ta = 25˚C

	Parameter	Symbol	Conditions	Ratings	Unit
	Maximum supply voltage	VDD		– 0.3 to +7.0	V
	Input voltage	VI		– 0.3 to VDD +0.3	V
	Output voltage	VO1	SOUT output	– 0.3 to VDD +0.3	V
		VO2	D1 to D32 output, output Tr off	28	V
	Output current	IO	D1 to D32 output, per output	30	mA
	Allowable power dissipation	Pd max	Ta=70°C	450	mW
	Operating temperature	Topr		– 10 to +70	˚C
	Storage temperature	Tstg		– 35 to +125	˚C

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

71901TN (KT)/62695TS/7049TA, TS 8-6023 No.3183–1/5

LC7935AN

Allowable Operating Conditions at Ta = –10 to +70˚C

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply voltage

VDD

VDD

4.5

5.5

V

H-level input voltage

VIH

SIN, CLOCK,

BEO,

0.8VDD

VDD

V

LATCH,

STROBE

L-level input voltage

VIL

SIN, CLOCK,

BEO,

VSS(L)

0.2VDD

V

LATCH,

STROBE

Clock frequency

fCLK

CLOCK: Duty: 50%

5.0

MHz

Clock pulse width

tWΦ

CLOCK

75

ns

Clock rise/fall time

tr, tf

CLOCK

200

ns

Data setup time

tDS

SIN, CLOCK

100

ns

Data hold time

tDH

SIN, CLOCK

50

ns

Latch pulse width

tWL

100

ns

LATCH

Electrical Characteristics at Ta = 25˚C

Parameter	Symbol				Conditions			Ratings		Unit
							min	typ	max
	IIH1	SIN, CLOCK,							10	µA
H-level input current					LATCH
	IIH2	BEO					12		72	µA
	IIL1	SIN, CLOCK,					– 10			µA
L-level input current					LATCH
	IIL2	STROBE					– 72		– 12	µA
H-level output voltage	VOH	SOUT: VDD=5V, IOH=– 0.5mA					VDD– 0.5			V
L-level output voltage	VOL1	SOUT: VDD=5V, IOL=0.5mA							0.5	V
	VOL2	D1 to D32: VDD=5V, IOL=30mA							0.5	V
Output OFF-state leakage current	IOFF	D1 to D32: VO=24V							20	µA
Input capacitance	CIN	CLOCK						5.0		pF
Operating current drain	IDD	VDD: VDD=5V, fCLK=5MHz, All outputs : no							5	mA
		load

Switching Characteristics at Ta = 25˚C

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Clock latch delay width

tCL

CLOCK,

VDD=5V

100

ns

LATCH:

Latch clock delay width

tLC

CLOCK,

VDD=5V

0

ns

LATCH:

tPLH1

LATCH, D1 to D32: VDD=5V, Dn: RL=1.0kΩ,

400

ns

CL=15pF

H-level output propagation delay time

BEO,

VDD=5V, Dn: RL=1.0kΩ,

tPLH2

STROBE:

300

ns

CL=15pF

tPLH3

CLOCK, SOUT: VDD=5V, SOUT: CL=15pF

200

ns

D1 to D32: VDD=5V, Dn: RL=1.0kΩ,

tPHL1

LATCH,

200

ns

CL=15pF

L-level output propagation delay time

BEO,

D1 to D32: VDD=5V, Dn:

tPHL2

STROBE,

100

ns

RL=1.0kΩ, CL=15pF

tPHL3

CLOCK, SOUT: VDD=5V, SOUT: CL=15pF

200

ns

Driver ON/OFF Truth Table

Latch Data (Q)	BEO	STROBE			Driver
0	0	0			OFF
1	0	0			OFF
0	1	0			OFF
1	1	0			ON Driver on
0	0	1			OFF
1	0	1			OFF
0	1	1			OFF
1	1	1			OFF

No.3183–2/5