Sanyo LC73101C Specifications

Ordering number : ENN*6853

11901RM (OT) No. 6853-1/34

Overview

The LC73101C is a dot matrix LCD driver IC that includes an on-chip display data RAM with a one-to-one correspondence between bits in RAM and display pixels on the LCD panel. The LC73101C provides display data RAM that can store 80 × 132 bits of data and can implement a large-screen display system with a single chip.

The LC73101C provides 80 common output circuits and 132 segment output circuits, and can display up to 80 × 132 dots (8 characters × 4 lines of kanji text using a 16 × 16-dot kanji font) with a single chip. The LC73101C also provides a master/slave function that allows two LC73101C chips to be combined to implement twice the display area: 160 × 132 dots.

The LC73101C provides a partial display function that allows the number of lines displayed to be set to 8, 16, 24, 32, 40, 48, 56, 64, 72, or 80 lines by commands sent from the system microcontroller. This allows the current drain to be reduced significantly when only a smaller number of lines needs to be displayed.

This device includes built-in voltage step-up circuits with factors of 3×, 4×, 5×, and 6× to provide high-quality display even when a high duty cycle is required. The number of step-up circuit stages used can be set by commands from the system microcontroller.

Since the display RAM read and write operations do not require the external operating clock, the LC73101C can operate at low power. Furthermore, since the LC73101C provides built-in LCD drive power supply, LCD drive

power supply voltage adjustment, temperaturecompensated reference voltage, and display contrast adjustment electronic potentiometers circuits, the LC73101C can implement portable display systems with low power consumption and a minimal number of external components.

Features

• 132 × 80-dot display

• Microcontroller interface (for both Intel and Motorola microcontrollers)

• On-chip display RAM (80 × 132 = 10,560 bits)

• Low power

• Low-voltage operation: VDD= 1.8 to 3.6 V

• High-precision reference voltage circuit (Variable temperature compensation coefficients)

• LCD drive 6× voltage step-up circuit (3×, 4×, 5×, or 6× can be selected by commands from the microcontroller.)

• Built-in high-precision RC oscillator circuit

• Contrast adjustment electronic potentiometer circuit

• Partial display function (Allows 8, 16, 24, 32, 40, 48, 56, 64, 72, or 80 lines to be displayed under the control of commands sent from the microcontroller.)

• Supports synchronous operation using master/slave connection.

Preliminary

LC73101C

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

LCD Driver IC

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Block Diagram

No. 6853-2/34

LC73101C

RES

P/S

WR(R/W)

RD(E)

CS2

CS1

D7(SI)

D6(SCL)

MPU interface

Command decoder Status register

Display data RAM

132 x 80

Column address circuit

Display data latch circuit

Line address circuit

I/O buffer

Page address circuit

Power supply

circuit

SEG Drivers

SEG0

SEG131

COM Drivers

COM output status select

circuit

Display timing generation circuit

CAP1+

CAP1-

CAP2+

CAP2-

CAP3+

CAP3-

CAP4+

VOUT

SS2

IRS

Bus holder

Oscillator

circuit

CLS

FRS

FR CL

M/S

HPM

DOF

COM0

COM79

CAP4-

CAP5+

CAP5-

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LC73101C

Pin Functions

Power supply

Pin I/O Function Number of pins

Power supply Microcontroller power supply. The same power supply system must be used for VCC. Undetermined

Power supply Connect to the system ground. These pins are 0 V pins. Undetermined

SS2

Power supply LCD drive step-up voltage circuit reference voltage Undetermined

Power supply

LCD power supply voltage adjustment circuit external input V

REG

power supply.

Undetermined

When the internally generated V

REG

is used, this pin outputs that V

REG

voltage.

Multi-level power supply system used as the LCD power supply. The voltages stipulated for each LCD cell are created by resistor divider circuits or by operational amplifier based impedance conversion. The potentials are

, V2, determined referenced to VSS, and must obey the following inequalities.

, V4, Power supply V1≥ V2≥ V3≥ V4≥ V5≥ V

Undetermined

When the built-in power supply circuit that operates in master mode is turned on, the voltage determined by the voltage adjustment circuit is applied to V

, and the voltages determined by LCD Bias Set commands are

applied to V

through V5.

LCD Power Supply Circuit Pins

Pin I/O Function Number of pins

CAP1+ O

Step-up circuit capacitor positive connection

Undetermined

Insert a capacitor between this pin and the CAP1– pin.

CAP1– O

Step-up circuit capacitor negative connection

Undetermined

Insert a capacitor between this pin and the CAP1+ pin.

CAP2+ O

Step-up circuit capacitor positive connection

Undetermined

Insert a capacitor between this pin and the CAP2– pin.

CAP2– O

Step-up circuit capacitor negative connection

Undetermined

Insert a capacitor between this pin and the CAP2+ pin.

CAP3+ O

Step-up circuit capacitor positive connection

Undetermined

Insert a capacitor between this pin and the CAP3– pin.

CAP3– O

Step-up circuit capacitor negative connection

Undetermined

Insert a capacitor between this pin and the CAP3+ pin.

CAP4+ O

Step-up circuit capacitor positive connection

Undetermined

Insert a capacitor between this pin and the CAP4– pin.

CAP4– O

Step-up circuit capacitor negative connection

Undetermined

Insert a capacitor between this pin and the CAP4+ pin.

CAP5+ O

Step-up circuit capacitor positive connection

Undetermined

Insert a capacitor between this pin and the CAP5– pin.

CAP5– O

Step-up circuit capacitor negative connection

Undetermined

Insert a capacitor between this pin and the CAP5+ pin.

OUT

O Post-step-up circuit voltage output. Insert a capacitor between this pin and VSS. Undetermined

Voltage adjustment. Apply a voltage in the range V

to VSSby using a resistor divider circuit.

I Use of this pin is only valid when the built-in V1voltage adjustment resistor is not used (IRS = low). Undetermined

Do not use this pin if the built-in V

voltage adjustment resistor is used (IRS = high).

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LC73101C

System Bus Connection Pins

Pin I/O Function Number of pins

Bidirectional 8-bit data bus connected to the microcontroller data bus. When the serial interface is selected (P/S is low):

D0 to D7 I/O

D7: Serial data input (SI)

D6: Serial clock input (SCL) In this mode, D0 to D5 go to the high-impedance state. When the chip select line is inactive, D0 to D7 go to the high-impedance state.

A0 is normally connected to the low order bit of the microcontroller address bus and discriminates between data

A0 I

and commands.

A0 = high: Indicates that D0 to D7 are used for data display.

A0 = low: Indicates that D0 to D7 are used for control data.

RES I

The LC73101C is initialized when RES is set low.

The reset operation is performed by the RES signal level.

CS1

Chip select signals. The LC73101C becomes active when CS1 is low and CS2 is high. Input and output of data

CS2 and commands is possible in this state.

This pin is active-low when an Intel-type microcontroller is used.

RD I

The Intel-type microcontroller RD signal should be connected to this pin. The LC73101C data bus goes to the

(E)

output state when this signal is low. This pin is active-high when a Motorola-type microcontroller is used.

This pin functions as the enable clock input pin when a Motorola-type microcontroller is used. This pin is active-low when an Intel-type microcontroller is used.

The Intel-type microcontroller WR signal should be connected to this pin. The data bus signals are latched on the

rising edge of the WR signal.

(R/W) When a Motorola-type microcontroller is used:

This pin functions as the read/write control signal input.

R/W = high: Read, R/W = low: Write. C86 is the Microcontroller interface switching input.

C86 I C86 = high: Motorola-type interface 1

C86 = low: Intel-type interface Parallel/serial data input mode switch

P/S = high: Parallel input

P/S = low: Serial input The table below lists the effects of this pin.

P/S I 1

When P/S is low, D0 to D5 go to the high-impedance state. D0 to D5 may be left high, low, or open in this mode. RD (E) and WR (R/W) must be held either high or low. In serial data input mode, the RAM display data and the device status cannot be read.

Selects enabled/disabled for the internal oscillator circuit for display clock 1

CLS I

CLS = high: Internal oscillator circuit enabled.

CLS = low: Internal oscillator circuit disabled. (External input) If CLS is low, input the display clock signal to the CL pin. Selects master or slave mode operation for the LC73101C itself.

In slave mode operation, synchronization with the display system is acquired by input of the timing signals required for LCD display.

M/S = high: Master operation

M/S = low: Slave operation

M/S I The M/S and CLS pins determine the operating state as shown in the table below.

P/S Data/command Data Read/write Serial clock

“H” A0 D0 to D7 RD, WR — “L” A0 SI (D7) Write only SCL (D6)

M/S CLS Oscillator circuit Power supply circuit CL FR DOF

“H”

“H” Enabled Enabled Output Output Output

“L” Disabled Enabled Input Output Output

“L”

“H” Disabled Disabled Input Input Input

“L” Disabled Disabled Input Input Input

Pin I/O Function Number of pins

LCD segment drive outputs. One of the V

, V3, V4, and VSSlevels is selected by the combination of the contents of display RAM and the

FR signal.

SEG0 to

O 132

SEG131

LCD common drive outputs. One of the V

, V2, V5, and VSSlevels is selected by the combination of the scan data and the FR signal.

COM0 to

O 80

COM80

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LC73101C

Pin I/O Function Number of pins

Display clock input or output. The M/S and CLS pins determine the operating state as shown in the table below.

CL I/O 1

When two LC73101C chips are used together in master/slave mode, their CL pins must be connected together. LCD alternation signal input or output.

FR I/O

M/S = high: Output

M/S = Low: Input When two LC73101C chips are used together in master/slave mode, their FR pins must be connected together. Indicates the on/off state of the LCD display.

M/S = high: Output

DOF I/O M/S = Low: Input 1

When two LC73101C chips are used together in master/slave mode, their DOF pins must be connected together.

V1 voltage adjustment resistor selection.

IRS = high: Internal resistor used.

IRS I IRS = low: Internal resistor not used. In this case, the V

voltage is adjusted by the VR pin and the external 1

divider resistor circuit. This pin is only valid in master mode. This pin must be held either low or high for slave mode operation. LCD drive power supply circuit power control.

HPM I

HPM = high: Normal mode

HPM = low: High power mode

This pin is only valid in master mode. This pin must be held either low or high for slave mode operation.

Continued from preceding page.

M/S CLS CL

“H”

“H” Output “L” Input

“L”

“H” Input “L” Input

RAM data FR

Output voltage

Display positive level Display inverted level

HHV

HLV

LHV

LLV

Power saving mode — V

Scan data FR Output voltage

HHV

HLV

LHV

LLV

Power saving mode — V

LCD Drive Pins

Pin I/O Function Number of pins

TEST0

O IC test pins. These pins must be left open. 8

to 7

TEST8 I IC test pin. This pin must be left open. 1

Test Pins

Functional Description

Microcontroller Interface

• Interface type selection The LC73101C transfers data over either an 8-bit bidirectional data bus (D0 to D7) or a serial data input system (SI). Applications can select either 8-bit parallel data input or serial data input as shown in table 1 by setting the P/S pin either high or low.

• Parallel interface When the parallel interface is selected (P/S = high), the bus of either an Intel-type or a Motorola-type microcontroller can be directly connected to the LC73101C parallel interface by setting the C86 pin either high or low as shown in table 2.

• Serial interface When the serial interface is selected (P/S = low), data can be written to the LC73101C using the serial input (SI) and serial clock (SCL) pins with the chip in the active state (CS1 = low, CS2 = high). The serial interface consists of an 8bit shift register and a 3-bit counter. Serial data is acquired from the serial data input pin in the order D7 to D0 on the rising edge of the serial clock signal. The serial data is converted to 8 bits of parallel data on the eighth rising edge of the serial clock and processed by the LC73101C.

Whether the serial data input is display data or a command is determined by the state of the A0 input. When A0 is high, the data is display data, and when A0 is low, it is taken to be a command. The A0 input is acquired and interpreted once every eight rising edges (that is, on the 8×th rising edge) of the serial clock signal after the chip goes to the active state.

Figure 1 shows the timing chart for the serial interface.

When the chip is in a non-active state due to the CS1 and CS2 inputs, the shift register and the counter are reset. The serial interface does not support readout. Be sure to prevent termination reflections and noise from appearing on the SCL signal. We recommend testing in an actual end product.

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LC73101C

Table 1

P/S CS1 CS2 A0 RD WR C86 D7 D6 D5 to D0 High: Parallel input CS1 CS2 A0 RD WR C86 D7 D6 D5 to D0 Low: Serial input CS1 CS2 A0 — — — SI SCL High impedance

Table 2

C86 CS1 CS2 A0 RD WR D7 to D0 High: Mptorola-type MPU bus CS1 CS2 A0 E R/W D7 to D0 Low: Intel-type MPU bus CS1 CS2 A0 RD WR D7 to D0

Figure 1

P/S

CS1

CS2

SCL(D6)

SI(D7)

ParallelData (InternalDataBus)

XXH

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

Data or

Command

D7:000H

00H

• Chip select The LC73101C has two chip select inputs: CS1 and CS2. The microcontroller and the serial interface can only be used when CS1 is low and CS2 is high. When the chip select inputs select a non-active state, the D0 to D7 pins go to the high-impedance state and the A0, RD, and WR inputs are disabled. The serial interface shift register and counter are reset.

• Access to display data RAM and internal registers The LC73101C supports high-speed data transfers that require no wait time as long as the LC73101C access cycle time constraints are met by the microcontroller. The LC73101C uses an internal “bus holder” circuit on its internal data bus to receive or send data during data transfers with the microcontroller.

For example, when the microcontroller writes to LC73101C display data RAM, the data is temporarily held by the bus holder and written to the display data RAM before the next write cycle. When the microcontroller reads out the contents of the display data RAM, data read out on the first (dummy) read cycle is stored in the bus holder, and then that data is read out onto the system bus on the next data read cycle. When reading display data RAM, after setting the address, the immediately following read instruction does not read out the data at the address specified, but rather reads out the data from the address specified by the second preceding data read operation. Thus care is required when using this function. This means that one dummy read operation is always required after setting the address or after a write cycle. Figure 2 (a) and figure 2 (b) show this timing.

• Busy flag When the busy flag is high, it indicates that an LC73101C internal operation is in progress.

The busy flag is output from the D7 pin by a Status Read command. If the cycle time (t

CYC

) conditions are met, there is no need to check this flag before each command. This can significantly increase the available processing power of the microcontroller.

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LC73101C

(a) Read

WR RD

DATA

Address N N+1 N+2

Address Preset Read Signal

Column Address Bus Holder

MPUInternal timing

Unknown Data N Data N+1

Address Set

Dummy Read

Data Read

N+1

Data Read

WR DATA

N+1 N+2 N+3

N N+1 N+2 N+3

BUS Holder RAM Write Signal

MPU

Internal

timing

(a) Write

Latch

Data Write Complete

Display Data RAM

• Display data RAM

The display data RAM holds the dot data to be displayed, and has an 80 (10-page × 8-bit) × 132-bit organization. This memory is accessed by specifying a page address and a column address to access data in 8-bit units. Since the display data D7 to D0 from the microcontroller corresponds to the direction of the LCD common pins as shown in figure 3, when two LC73101C chips are used together, there are few constraints or limitations when transferring data, and highly flexible display structures can be implemented easily. Read and write operations to this display data RAM are performed through an I/O buffer, and thus these operations are independent of signal reads for LCD drive. This means that flicker and other problems do not occur when the display RAM is accessed asynchronously during display on the LCD panel.

Figure 3 Noninverting LCD Display

• Page address circuit The display data RAM page address shown in figure 4 is specified using the Page Address Set command. The page address must be specified again to access a different page.

• Column address circuit The display data RAM column address shown in figure 4 is specified using the Column Address Set command. Since the specified column address is incremented each time a display data read or write command is input, the microcontroller can access the display data consecutively. Note that this column address incrementing stops when the column address reaches 83H. Since the column address and the page address are mutually independent, the column address and the page address must both be specified again to access a different column on a different page. Additionally, the correspondence between the display data RAM column address and segment output can be inverted with the CSS command (Column Address/Segment Output Correspondence Selection command) as shown in table 3. This reduces constraints on IC positioning when assembling LCD modules.

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LC73101C

D0 0 1 0 1 0 COM0 D1 1 0 1 0 1 COM1 D2 1 1 0 0 0 COM2 D3 0 0 1 1 1 COM3 D4 1 1 0 0 0 COM4

Display data RAM LCD display

Table 3

CSS setting (D0) Column address Segment output

0H → SEG0

83H → SEG131

0H → SEG131

83H → SEG0

• Line address circuit The line address circuit specifies the line address corresponding to the COM output when the contents of display data RAM are displayed as shown in figure 4. Normally, the Display Start Line Address Set command specifies the uppermost line of the display (which depends on the common output state: in normal mode: COM0 output; in the inverted state: COM79 output). The maximum display area is 80 lines in the direction of increasing line address values from the specified display start line address.

The data for the line address set by the Display Start Line Address Set command is passed to the common output driver specified by the Common Output State Selection command and the address set by the Display Start Common Address Set command in the common address circuit.

Operations such as scrolling the screen and switching pages can be implemented by changing display start line address with this Display Start Line Address Set command.

• Common address circuit The line address circuit passes the display data for the line address determined by the line address circuit to the common output driver offset by the number of lines set by the Display Start Common Address Set command. Additionally, at this time the correspondence (figure 4) between the common output driver and the common address specified by the Common Output State Selection command is take into consideration.

During partial display, the display position on the screen can be changed by changing this address without rewriting the contents of display RAM.

• Display data latch circuit The display data latch circuit is a latch that temporarily holds the display data output to the LCD drive circuit from data display RAM. Since the display normal/inverted and display on/off commands control this latched data, the data in display data RAM is not changed by these functions.

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Figure 4 Display RAM Address Map

No. 6853-10/34

LC73101C

00H

01H

02H

03H

04H

05H

06H

07H

7CH

7DH

7EH

7FH

80H

81H

82H

83H

01H 02H 03H 04H 05H 06H 07H 08H

09H 0AH 0BH 0CH 0DH 0EH 0FH

00H

11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH

10H

21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH

31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH

41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH

20H

30H

40H

01H 02H 03H 04H 05H 06H 07H 08H

09H 0AH 0BH 0CH 0DH 0EH 0FH

00H

11H

12H

13H

14H

15H

16H

17H

18H

19H 1AH 1BH 1CH 1DH 1EH 1FH

10H

21H

22H

23H

24H

25H

26H

27H

28H

29H 2AH 2BH 2CH 2DH 2EH 2FH

31H

32H

33H

34H

35H

36H

37H

38H

39H 3AH 3BH 3CH 3DH 3EH 3FH

41H

42H

43H

44H

45H

46H

47H

48H

49H 4AH 4BH 4CH 4DH 4EH 4FH

20H

30H

40H

Page0

Page2

Page1

Page3

Page4

Page5

Page6

Page7

Page8

Page9

Data

D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

0000

1000

0100

1100

0010

0110

1010

1110

0001

1001

D0D1D2D3

Page

Address

Line

Address

Column

Address

Common

Address

COM0

Start

COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8

COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79

00H

01H

02H

03H

04H

05H

06H

07H

7CH

7DH

7EH

7FH

80H

81H

82H

CSS

Command

(D0)

83H

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

Common Output

Select(D3)

0 1

Common Output

Partial Display Function

• Partial display function The LC73101C provides commands that control the following settings: the LCD drive duty setting, the LCD drive bias selection, the number of stages of voltage step-up, the display start line address, and the display start common address. These settings can be used to only display part of the screen.

The number of lines displayed by the partial display function can be selected to be 8, 16, 24, 32, 40, 48, 56, 64, 72, or 80 lines. This is set by setting the LCD duty. The start of the frame is the display start line, and by setting this line to be the display start common address, it is possible to select any of the COM0 to COM79 lines.

In general, as the LCD drive duty is reduced, the optimal values of the LCD drive voltage and LCD drive bias also become smaller. Since this allows the number of step-up stages in the voltage step-up circuit to be reduced, power consumption can be reduced significantly.

• Duty and frame frequency Table 4 shows the relationship between the duty setting, the number of lines, the display clock frequency fCL, and the frame frequency fFR.

Oscillator Circuit

This circuit is an RC circuit that generates the display clock. The oscillator circuit is only enabled when M/S is high and CLS is high. When CLS is low, the oscillator circuit is stopped and the display clock is input to the CL pin.

No. 6853-11/34

LC73101C

Table 4

Duty

Number of lines

fCL[kHz] fFR[Hz]

displayed 80 80 6.40 80.0 72 72 5.12 71.1 64 64 5.12 80.0 56 56 4.27 76.2 48 48 3.66 76.2 40 40 3.20 80.0 32 32 2.56 80.0 24 24 1.97 82.1 16 16 1.28 80.0

8 8 0.640 80.0

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