Sanyo LC72E32 Specifications

Overview

The LC72E32 microcontroller is an on-chip UVEPROM
version of the LC7232N single-chip microcontroller plus
PLL product. The LC72E32 has the same functions and
pin assignment as the LC7232N mask ROM version. Its
on-chip EPROM has an 8-Kbyte capacity and a 4-Kword
by 16-bit organization. Since programs can be rewritten
multiple times, the LC72E32 is optimal for program
development.

Features

• Options can be switched with EPROM data
The LC7232N option functions can be specified with
EPROM data. This allows the actual mass production
printed circuit board to be used for test product
evaluation.

• 8 Kbytes (with a 4-Kword by 16-bit organization) of
UVEPROM on chip
The LC72E32 includes 8 Kbytes of UVEPROM
(ultraviolet erasable EPROM) on chip.

• The pin arrangement is identical to that of the LC7232N
mask ROM version, i.e., pin compatibility is
maintained.

Package Dimensions

unit: mm

3152A-QFP80

Ordering number : EN*4741

83098HA (OT) / 83194 TH (OT) No. 4741-1/15

Preliminary

LC72E32

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Single Chip Microcontroller Plus PLL LSI

with On-Chip UVEPROM

CMOS LSI

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

[LC72E32]

SANYO: QIP80

Allowable Operating Ranges at Ta = 10 to 40°C, VDD= 3.5 to 5.5 V

No. 4741-2/15

LC72E32

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

DD

1 CPU and PLL operating 4.5 5.5 V

Supply voltage V

DD

2 CPU operating 3.5 5.5 V

V

DD

3 Memory retention voltage 1.3 5.5 V

V

IH

1 G port 0.7 V

DD

8.0 V

V

IH

2 RES, INT, HOLD 0.8 V

DD

8.0 V

Input high level voltage

V

IH

3 SNS 2.5 8.0 V

V

IH

4 A port 0.6 V

DD

V

DD

V

V

IH

5 E and F ports 0.7 V

DD

V

DD

V

V

IH

6 LCTR (period measurement), VDD1 0.8 V

DD

V

DD

V

V

IL

1 G port 0 0.3 V

DD

V

V

IL

2 RES, INT 0 0.2 V

DD

V

V

IL

3 SNS 0 1.3 V

Input low level voltage V

IL

4 A port 0 0.2 V

DD

V

V

IL

5 E and F ports 0 0.3 V

DD

V

V

IL

6 LCTR (period measurement), VDD1 0 0.2 V

DD

V

V

IL

7 HOLD 0 0.4 V

DD

V

f

IN

1 XIN 4.0 4.5 5.0 MHz

f

IN

2 FMIN, VIN2, VDD1 10 130 MHz

f

IN

3 FMIN, VIN3, VDD1 10 150 MHz

Input frequency

f

IN

4 AMIN (L), VIN4, VDD1 0.5 10 MHz

f

IN

5 AMIN (H), VIN5, VDD1 2.0 40 MHz

f

IN

6 HCTR, VIN6, VDD1 0.4 12 MHz

f

IN

7 LCTR (frequency), VIN7, VDD1 100 500 kHz

f

IN

8 LCTR (period), VIH6, VIL6, VDD1 1 20 × 10

3

Hz

V

IN

1 XIN 0.50 1.5 Vrms

V

IN

2 FMIN 0.10 1.5 Vrms

Input amplitude V

IN

3 FMIN 0.15 1.5 Vrms

V

IN

4, 5 AMIN 0.10 1.5 Vrms

V

IN

6, 7 LCTR, HCTR 0.10 1.5 Vrms

Input voltage range V

IN

8 ADI 0 V

DD

V

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Note: There are circuits in this IC with reduced resistance to damage from static electricity. Thus special care is required when handling this product.

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max –0.3 to +6.5 V

Input voltage

V

IN

1 HOLD, INT, RES, ADI, SNS, and the G port –0.3 to +13 V

V

IN

2 Inputs other than VIN1 –0.3 to VDD+ 0.3 V

Output voltage

V

OUT

1 H port –0.3 to +15 V

V

OUT

2 Outputs other than V

OUT

1 –0.3 to VDD+ 0.3 V

I

OUT

1 All D and H port pins 0 to 5 mA

Output current

I

OUT

2 All E and F port pins 0 to 3 mA

I

OUT

3 All B and C port pins 0 to 1 mA

I

OUT

4 S1 to S28 and all I port pins 0 to 1 mA
Allowable power dissipation Pd max Topg = 10 to 40°C 400 mW
Operating temperature Topr 10 to 40 °C
Storage temperature Tstg –45 to +125 °C

Electrical Characteristics for the Allowable Operating Ranges

No. 4741-3/15

LC72E32

Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

H

LCTR (period), RES, INT 0.1 V

DD

V

Rejected pulse width P

REJ

SNS 50 µs

Power-down detection voltage V

DET

3.0 3.5 4.0 V

I

IH

1

INT, HOLD, RES, ADI, SNS,

3.0 µA

and G port: V

I

= 5.5 V

I

IH

2

A, E, and F ports: E and F ports with

3.0 µA

Input high level current

outputs off, A port with no R

PD

, VI= V

DD

IIH3 XIN: VI= VDD= 5.0 V 2.0 5.0 15 µA
I

IH

4

FMIN, AMIN, HCTR, LCTR:

4.0 10 30 µA

V

I

= VDD= 5.0 V

I

IH

5 A port: With an RPD, VI= VDD= 5.0 V 50 µA

I

IL

1

INT, HOLD, RES, ADI, SNS,

3.0 µA

and G port: V

I

= V

SS

Input low level current

I

IL

2

A, E, and F ports: E and F ports with

3.0 µA

outputs off, A port with no R

PD

, VI= V

SS

IIL3 XIN: VIN= V

SS

2.0 5.0 15 µA

I

IL

4 FMIN, AMIN, HCTR, LCTR: VI= V

SS

4.0 10 30 µA

Input floating voltage V

IF

A port: With an R

PD

0.05 V

DD

V

Pull-down resistance R

PD

A port: With an RPD, VDD= 5.0 V 75 100 200 kΩ

I

OFFH

1 EO1, EO2: VO= V

DD

0.01 10 nA

Output high level off leakage current I

OFFH

2 B, C, D, E, F, and I ports: VO= V

DD

3.0 µA

I

OFFH

3 H port: VO= 13 V 5.0 µA

Output low level off leakage current

I

OFFL

1 EO1, EO2: VO= V

SS

0.01 10 nA

I

OFFL

2 B, C, D, E, F, and I ports: VO= V

DD

3.0 µA

V

OH

1 B and C ports: IO= 1 mA VDD– 2.0 VDD– 1.0 VDD– 0.5 V

V

OH

2 E and F ports: IO= 1 mA VDD– 1.0 V

V

OH

3 EO1, EO2: IO= 500 µA VDD– 1.0 V

Output high level voltage V

OH

4 XOUT: IO= 200 µA VDD– 1.0 V

V

OH

5 S1 to S28 and I port: IO= –0.1 mA VDD– 1.0 V

V

OH

6 D port: IO= 5 mA VDD– 1.0 V

V

OH

7 COM1 and COM2: IO= 25 µA VDD– 0.75 VDD– 0.5 VDD– 0.3 V

V

OL

1 B and C ports: IO= 50 µA 0.5 1.0 2.0 V

V

OL

2 E and F ports: IO= 1 mA 1.0 V

V

OL

3 EO1, EO2: IO= 500 µA 1.0 V

Output low level voltage

V

OL

4 XOUT: IO= 200 µA 1.0 V

V

OL

5 S1 to S28 and I port: IO= 0.1 mA 1.0 V

V

OL

6 D port: IO= 5 mA 1.0 V

V

OL

7 COM1, COM2: IO= 25 µA 0.3 0.5 0.75 V

V

OL

8 H port: IO= 5 mA (150 Ω) 0.75 (400 Ω) 2.0 V

Output middle level voltage V

M

1 COM1, COM2: VDD= 5.0 V, IO= 20 µA 2.0 2.5 3.0 V

A/D conversion error ADI: V

DD

1 –1/2 1/2 LSB

I

DD

1VDD1, fIN2 = 130 MHz 15 20 mA

I

DD

2

V

DD

= 5.0 V, PLL stopped, CT = 2.67 µs

2.7 mA

(HOLD mode, Figure 1)

I

DD

3

V

DD

= 5.0 V, PLL stopped, CT = 13.33 µs

1.7 mA

(HOLD mode, Figure 1)

Current drain

I

DD

4

V

DD

= 5.0 V, PLL stopped, CT = 40.00 µs

1.5 mA

(HOLD mode, Figure 1)
V

DD

= 5.5 V, oscillator stopped, Ta = 25°C

5µA

I

DD

5

(BACK UP mode, Figure 2)
V

DD

= 2.5 V, oscillator stopped, Ta = 25°C

1µA

(BACK UP mode, Figure 2)

Test Circuits

Note: PB to PF, PH, and PI are all open. However, PE and PF are output-selected.

Figure 1 IDD2 to IDD4 in HOLD Mode

Note: PA to PI, S1 to S24, COM1, and COM2 are all open.

Figure 2 IDD5 in BACK UP Mode

No. 4741-4/15

LC72E32

Pin Functions

No. 4741-5/15

LC72E32

Pin Pin No. Function I/O I/O circuit type

EPROM mode
function

PA0
PA1
PA2
PA3

PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3

PD0
PD1
PD2
PD3

PE0
PE1
PE2
PE3

PF0
PF1
PF2
PF3

PG0
PG1

PG2
PG3

35
34
33
32

30
29
28
27
26
25
24
23

22
21
20
19

18
17
16
15

14
13
12
11

6
5

4
3

Low threshold type dedicated input port
These pins can be used, for example, for key data acquisition.
Built-in pull-down resistors can be specified as an option. This

option is in 4-pin units, and cannot be specified for individual
pins.

Input through these pins is disabled in BACKUP mode.

Dedicated output ports
Since the output transistor impedances are unbalanced

CMOS, these pins can be effectively used for functions such
as key scan timing. These pins go to the output high
impedance state in BACKUP mode.

These pins go to the low level during a reset, i.e., when the
RES pin is low.

Dedicated output port
These are normal CMOS outputs. These pins go to the output

high impedance state in BACKUP mode.
These pins go to the low level during a reset, i.e., when the

RES pin is low.

I/O port
These pins are switched between input and output as follows.

Once an input instruction (IN, TPT, or TPF) is executed, these
pins latch in the input mode. Once an output instruction (OUT,
SPB, or RPB) is executed, they latch in the output mode.

These pins go to the input mode during a reset, i.e., when the
RES pin is low.

In BACKUP mode these pins go to the input mode with input
disabled.

I/O port
These pins are switched between input and output by the

FPC instruction.
The I/O states of this port can be specified for individual pins.
These pins go to the input mode during a reset, i.e., when the

RES pin is low.
In BACKUP mode these pins go to the input mode with input

disabled.

Dedicated input port
Input through these pins is disabled in BACKUP mode.

Input

Output

I/O

Input

Data I/O
PE0: D0

PE1: D1
PE2: D2
PE3: D3

PF0: D4
PF1: D5
PF2: D6
PF3: D7

EPROM control
signal inputs

PG0: CE
PG1: OE

Continued on next page.