SANYO LC72366, LC72362N, LC72358N Datasheet

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CMOS LSI

Ordering number : EN5065A

63096HA (OT)/62295TH (OT) No. 5065-1/13

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

Single-Chip PLL Microcontrollers

LC72358N, 72362N, 72366

Overview

The LC72358N, LC72362N, and LC72366 are 1.33 µs instruction execution time single-chip microcontrollers for electronic tuning applications. These products incorporate a high-speed locking circuit and a high-performance direct PLL circuit that can control the local oscillator C/N characteristics. These products have 256 or 512 bytes of RAM and 16K, 24K or 32K bytes of program ROM on chip, and incorporate a three-channel serial I/O interface, a six-channel A/D converter and other interfaces.

Features

• ROM

— LC72358N: 8K steps (8191 × 16 bits) — LC72362N: 12K steps (12287 × 16 bits) — LC72366: 16K steps (16383 × 16 bits)

The subroutine area in both products is 4K steps (4095 × 16 bits).

• RAM

— LC72358N, 72362N: 512 × 4 bits (banks 0 to 7) — LC72366: 1K × 4 bits (banks 0 to F)

• Stack: Eight levels

• Serial I/O: Three channels (8-bit 3-wire format) There are three internal serial clocks: 12.5 kHz,

37.5 kHz and 187.5 kHz.

• External interrupts:

Two channels (the INT0 and INT1 pins) Switching between rising and falling edge detection is supported.

• Internal interrupts:

Three channels — Two internal timer interrupt channels

The timers provide eight interrupt periods: 100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms.

— One serial I/O interrupt channel

• Multiple interrupt levels:

Four levels Hardware priority order INT0 pin > INT1 pin > SI/O pin > internal timer 0 > internal timer 1

• A/D converter: Six channels (6-bit successive approx-

imation type)

• General-purpose ports

— Input ports: 10

— Output ports: 28 — I/O ports: 25 (These pins can be switched between

input and output in bit units.)

• PLL block — Built-in sub-charge pump for high-speed locking — Support for dead zone control — Built-in unlock detection circuit — Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,

10, 12.5, 25, 30, 50 and 100 kHz

• Universal counter: 20 bits

Supports frequency and period measurement with counting periods of 1, 4, 8 and 32 ms.

• Timers: Timer interrupt periods

100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms

• Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,

3.0 kHz, 3.75 kHz, 4.17 kHz.

• Reset: Built-in voltage detection type reset circuit

• Cycle time: 1.33 µs (all instructions execute in one

cycle)

• Halt mode: The microcontroller operating clock is

stopped in halt mode. There are four types of event that clear halt mode: interrupt requests, timer FF overflows, key inputs, and hold pin inputs.

• Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V

when only the controller block operates)

• Package: QFP80E (QIP80E)

• OTP version: LC72P366

• Development tools: Emulator.................RE32N

Evaluation chip.......LC72EV350

Evaluation chip board

................................EB-72EV350

This LSI can easily use CCB that is SANYO’s original bus format.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Pin Assignment

No. 5065-2/13

LC72358N, 72362N, 72366

Package Dimensions

unit: mm

3174-QFP80E

SANYO: QIP80E

[

LC72358N, 72362N, 72366

]

Block Diagram

No. 5065-3/13

LC72358N, 72362N, 72366

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Allowable Operating Ranges at Ta = –40 to +85°C, VDD= 3.5 to 5.5 V

No. 5065-4/13

LC72358N, 72362N, 72366

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max –0.3 to +6.5 V

Input voltage V

All input pins –0.3 to VDD+ 0.3 V

Output voltage

OUT

(1) J port –0.3 to +15 V

OUT

(2) All output ports other than V

OUT

(1) –0.3 to VDD+ 0.3 V

OUT

(1) J port 0 to 5 mA

Output current I

OUT

(2)

D, E, F, G, K, L, M, N, O, P and Q ports,

0 to 3 mA

EO1, EO2, EO3, SUBPD

OUT

(3) B and C ports 0 to 1 mA Allowable power dissipation Pd max Ta = –40 to +85°C 400 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –45 to +125 °C

Parameter Symbol Conditions min typ max Unit

(1) CPU and PLL operating 4.5 5.0 5.5 V

Supply voltage V

(2) CPU operating 3.5 5.5 V

(3) Memory retention 1.3 5.5 V

(1)

E, H, I, L, M and Q ports, HCTR and LCTR

0.7 V

(when selected for input)

Input high level voltage

(2)

F, G and K ports, LCTR (period measurement mode),

0.8 V

HOLD

(3) SNS 2.5 V

(4) A port 0.6 V

(1)

E, H, I, L, M and Q ports, HCTR and LCTR

0 0.3 V

(when selected for input)

Input low level voltage

(2) A, F, G and K ports, LCTR (period measurement mode) 0 0.2 V

(3) SNS 0 1.3 V

(4) HOLD 0 0.4 V

(1) XIN 4.0 4.5 5.0 MHz

(2) FMIN: VIN(2), VDD(1) 10 150 MHz

(3) FMIN: VIN(3), VDD(1) 10 130 MHz

Input frequency

(4) AMIN (H): VIN(3), VDD(1) 2.0 40 MHz

(5) AMIN (L): VIN(3), VDD(1) 0.5 10 MHz

(6) HCTR: VIN(3), VDD(1) 0.4 12 MHz

(7) LCTR: VIN(3), VDD(1) 100 500 kHz

(8) LCTR (period measurement): VIH(2), VIL(2), VDD(1) 1 20 × 10

(1) XIN 0.5 1.5 Vrms

Input amplitude V

(2) FMIN 0.10 1.5 Vrms

(3) FMIN, AMIN, HCTR, LCTR 0.07 1.5 Vrms

Input voltage range V

(4) ADI0 to ADI5 0 V

Electrical Characteristics for the Allowable Operating Ranges

Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped.

( ) Value: LC72366

Test Circuit

No. 5065-5/13

LC72358N, 72362N, 72366

Parameter Symbol Conditions min typ max Unit

(1) XIN: VI= VDD= 5.0 V 2.0 5.0 15 µA

(2) FMIN, AMIN, HCTR, LCTR: VI= VDD= 5.0 V 4.0 10 30 µA

A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,

Input high level current

(3)

HCTR, LCTR, with no pull-down resistor on A port.

3.0 µA

= VDD= 5.0 V,

with the E, F, G, K, L, M and Q ports selected for input. IIH(4) A port: pull-down resistor present, VI= VDD= 5.0 V 50 µA I

(1) XIN: VI= V

2.0 5.0 15 µA

(2) FMIN, AMIN, HCTR, LCTR: VI= V

4.0 10 30 µA

Input low level current

A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD, I

(3)

HCTR, LCTR, with no pull-down resistor on A port.

3.0 µA

= VSS,

with the E, F, G, K, L, M and Q ports selected for input.

Input floating voltage V

A port: pull-down resistor present 0.05 V

Pull-down resistance R

(1) A port: pull-down resistor present, VDD= 5 V 75 100 200 kΩ

Hysteresis V

F, G and K ports, LCTR (period measurement mode) 0.1 V

0.2 V

(1) B and C ports: IO= –1 mA VDD– 2.0 VDD– 1.0 V

Output high level voltage

(2) D, E, F, G, K, L, M, N, O, P and Q ports: IO= –1 mA VDD– 1.0 V

(3) EO1, EO2, EO3, SUBPD: IO= –500 µA VDD– 1.0 V

(4) XOUT: IO= –200 µA VDD– 1.0 V

(1) B and C ports: IO= 50 µA 1.0 2.0 V

(2) D, E, F, G, K, L, M, N, O, P and Q ports: IO= 1 mA 1.0 V

Output low level voltage V

(3) EO1, EO2, EO3, SUBPD: IO= 500 µA 1.0 V

(4) XOUT: IO= 200 µA 1.5 V

(5) J port: IO= 5 mA 2.0 V

OFF

(1) B, C, D, E, F, G, K, L, M, N, O, P and Q ports –3.0 +3.0 µA

Output off leakage current I

OFF

(2) EO1, EO2, EO3, SUBPD –100 +100 nA

OFF

(3) J port –5.0 +5.0 µA

A/D conversion error ADI0 to ADI5: V

(1) –1/2 +1/2 LSB

Reject pulse width P

REJ

SNS 50 µs

Power-down detection voltage V

DET

2.7 3.0 3.3 V

Pull-down resistance R

(2) TEST1, TEST2 10 kΩ

(1) VDD(1): fIN(2) = 130 MHz, Ta = 25°C 12 24 mA

Current drain

(2) VDD(2): Halt mode*, Ta = 25°C (Figure 1) 0.45 (0.9) mA

(3) VDD= 5.5 V, oscillator stopped, Ta = 25°C (Figure 2) 5 µA

(4) VDD= 2.5 V, oscillator stopped, Ta = 25°C (Figure 2) 1 µA

Note: All of the pins PB to PG and PJ to PQ must be left open.

Here, the pins PE to PG, PK to PM, and PQ are selected for output.

Figure 1: IDD(2) in Halt Mode

Note: All of the pins PA to PQ must be left open.

Figure 2. IDD(3) and IDD(4) in Backup Mode

Pin Functions

No. 5065-6/13

LC72358N, 72362N, 72366

Pin No. Symbol I/O I/O type Function

30 29 28 27

26 25 24 23 22 21 20 19

18 17 16 15

14 13 12 11 10

9 8 7 6 5 4 3

78 77

PA0 PA1 PA2 PA3

PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3

PD0 PD1 PD2 PD3

PE0

PE1/SCK2

PE2/SO2

PE3/SI2

PF0

PF1/SCK1

PF2/SO1

PF3/SI1

PG0

PG1/SCK0

PG2/SO0

PG3/SI0

XIN

XOUT

EO1 EO2

I/O

Pull-down resistor included Input

Unbalanced CMOS push-pull

CMOS push-pull

—

CMOS tristate

Key return signal input-only ports. The threshold voltage is set to a relatively low value. When a key matrix is formed in combination with the PB and PC ports, up to three simultaneous key presses can be detected. The pull-down resistors are set by the IOS instruction with PWn = 2 for all four pins at the same time and cannot be set on an individual pin basis. Input is disabled in clock stop mode.

Key source signal output-only ports. Since the output transistor circuit is an unbalanced CMOS structure, diodes to prevent shorting due to multiple key presses are not required. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed.

Output-only ports. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed.

General-purpose I/O port/serial I/O pin shared-function ports. The F and G port inputs are Schmitt inputs. The E ports is a normal input. The IOS instruction switches these ports between general-purpose I/O ports and serial I/O ports, and between input and output for general-purpose I/O ports.

• When used as general-purpose I/O ports these pins: Can be set for input or output in bit units (bit I/O), and are set for use as general-purpose I/O ports by the IOS instruction with PWn = 0.

b0 = SI/O 0 0 ...................general-purpose port

b1 = SI/O 1 1 ...................SI/O port

b2 = SI/O 2 are set for input or output by the IOS instruction in bit units.

PE..............PWn = 4 0...................Input

PF..............PWn = 5 1 ...................Output

PG.............PWn = 6

• When used as serial I/O ports these pins: Are set for serial I/O port use by the IOS instruction with PWn = 0, and are accessed by reading and writing the serial I/O data buffer with the INR and OUTR instructions. Note: Pin setup states when used as serial I/O ports:

PE0, PF0, PG0......General-purpose I/O

PE1, PF1, PG1......SCK output in internal clock mode

SCK input in external clock mode

PE2, PF2, PG2......SO output

PE3, PF3, PG3......SI input

In clock stop mode, input is disabled and these pins go to the high-impedance state. During the power-on reset, these pins become general-purpose input ports.

Connections for a 4.5 MHz crystal oscillator

Main charge pump outputs These pins output a high level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a low level when that frequency is lower. These pins go to the high-impedance state when the frequencies match. These pins go to the high-impedance state when the HOLD pin is set low in the hold enable state. In clock stop mode, during the power-on reset and in the PLL stop state, these pins go to the high-impedance state.

Continued on next page.

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No. 5065-7/13

LC72358N, 72362N, 72366

Continued on next page.

Pin No. Symbol I/O I/O type Function

76 73 31

FMIN

AMIN

SUBPD

EO3

—

Input

CMOS tristate

Power supply connections

FM VCO (local oscillator) input This pin is selected by the PLL instruction CW1 (b1, b0 are ignored). Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state.

AM VCO (local oscillator) input This pin is selected and the band set by the PLL instruction CW1 (b1, b0).

Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state.

Sub-charge pump output This pin, in combination with the main charge pump, allows the construction of a highspeed locking circuit. The DZC instruction controls the sub-charge pump.

This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state.

This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state.

Second PLL charge pump output This pin outputs a low level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a high level when that frequency is lower. This pin goes to the high-impedance state when the frequencies match. (Note that this pin’s output logic is the opposite of that of the EO1 and EO2 pins.) This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state.

b1 b0 Band

1 0 2 to 40 MHz (SW) 1 1 0.5 to 10 MHz (MW, LW)

b3 b2 Operation

0 0 High impedance 0 1 Only operates in the unlocked state (450 kHz) 1 0 Only operates in the unlocked state (900 kHz) 1 1 Normal operation

Continued from preceding page.

No. 5065-8/13

LC72358N, 72362N, 72366

Continued on next page.

Pin No. Symbol I/O I/O type Function

HCTR

LCTR

SNS

Input

Universal counter/general-purpose input shared-function input port The IOS instruction b3 with PWn = 3 switches the pin function between universal counter input and general-purpose input.

• Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b3 = 0. HCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 and b2 = 0, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled.

• General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3 and b3 = 1. An internal register (address: 0EH) input instruction INR (b0) is used to acquire data from this pin.

Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function is selected.

Universal counter (frequency and period measurement)/general-purpose input sharedfunction input port The IOS instruction b2 with PWn = 3 switches the pin function between universal counter input and general-purpose input.

• Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b2 = 0. LCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 b2 = 1, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled.

• Period measurement With the universal counter function selected, set up period measurement mode with a UCS instruction with b3 = 1 and b2 = 0, and start the count with a UCC instruction after selecting the count time. The CNTEND flag will be set when the count completes. In this mode, the signal must be input with DC coupling to turn off the bias feedback resistor.

• General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3, b2 = 1. An internal register (address: 0EH) input instruction INR (b1) is used to acquire data from this pin.

Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function (in HCTR frequency measurement mode) is selected.

Voltage sense/general-purpose input pin shared-function port This circuit is designed for a relatively low input threshold voltage.

• Voltage sense pin usage This input pin is used to determine whether or not a power failure occurred after recovery from backup (clock stop) mode. An internal sense F/F is used for this determination. The sense F/F is tested with a TUL instruction (b2).

• General-purpose input port usage When used as a general-purpose input port, the state is sensed by using a TUL instruction (b3).

Since, unlike other input ports, input is not disabled in clock stop mode and during the power-on reset, special care is required with respect to through currents.

Continued from preceding page.

No. 5065-9/13

LC72358N, 72362N, 72366

Pin No. Symbol I/O I/O type Function

66 65 64 63 62 61

60 59 58 57

56 55 54 53

52 to

HOLD

PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3

PI0/ADI4 PI1/ADI5

PJ0 PJ1 PJ2 PJ3

PK0/INT0 PK1/INT1

PK2 PK3

PL0 to PL3

PM0 to PM3

I/O

Input

N-channel open drain

CMOS push-pull

PLL control and clock stop mode control Setting this pin low in the hold enabled state disables input to the FMIN and AMIN pins and sets the EO pin to the high-impedance state. To enter clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP instruction. To clear clock stop mode, set this pin high.

General-purpose input port/A/D converter shared-function pins The IOS instruction with PWn = 7 or 8 switches the pin function between general-purpose input ports and A/D converter inputs.

• General-purpose input port usage Specify general-purpose input port usage with the IOS instruction with PWn = 7 or 8 in bit units.

• A/D converter usage Specify A/D converter usage with the IOS instruction with PWn = 7 or 8 in bit units. Specify the pin to convert with the IOS instruction with PWn = 1. Start a conversion with the UCC instruction (b2). The ADCE flag will be set when the conversion competes. Note: Executing an input instruction for a port specified for ADI usage will always return

low since input is disabled. These pins must be set up for general-purpose input

port usage before an input instruction is executed. Input is disabled in clock stop mode. During the power-on reset, these pins go to the general-purpose input port function.

General-purpose output ports An external pull-up resistor is required since these pins are open-drain circuits. In clock stop mode, these pins go to the transistor off state (high level output). During the power-on reset, these pins are set up as general-purpose output ports and go to the transistor off state (high level output).

General-purpose I/O/external interrupt shared-function ports There is no instruction that switches the function of these ports between general-purpose ports and external interrupt ports. These pins function as external interrupt pins at the point that the external interrupt enable flag is set.

• General-purpose I/O port usage

These pins can be set for input or output in bit units (bit I/O). The IOS instruction is used to specify input or output in bit units.

• External interrupt pin usage

This function can be used by setting the external interrupt enable flags (INT0EN and INT1EN) in status register 2. The corresponding pin must be set up for input. To enable interrupt operation, the interrupt enable flag (INTEN) in status register 1 also must be set. The IOS instruction with PWn = 3, b1 = INT1, and b0 = INT0 is used to select rising or

falling edge detection. In clock stop mode, input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports.

General-purpose I/O ports The IOS instruction is used to specify input or output. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports.

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No. 5065-10/13

LC72358N, 72362N, 72366

Pin No. Symbol I/O I/O type Function

44 43 42 41

40 to

PN0/BEEP

PN1 PN2 PN3

PO0 to PO3

PP0 to PP3

PQ0

TEST1 TEST2

I/O

CMOS push-pull

General-purpose output port/BEEP tone shared-function output pins The BEEP instruction switches between the general-purpose output port and BEEP tone functions.

• General-purpose output port usage

The BEEP instruction with b3 = 0 sets up the general-purpose output port function.

Pins PN1 to PN3 are general-purpose output-only pins.

• BEEP output usage

The BEEP instruction with b3 = 1 sets up BEEP output.

The BEEP instruction bits b0, b1 and b2 sets the frequency.

When set up as the BEEP port, executing an output instruction will set the internal latch

data but has no influence on the output. These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed.

Output-only ports These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed.

General-purpose I/O ports The IOS instruction is used to specify input or output. The OUTR and INR instructions are used for output and input. The bit set, reset and test instruction cannot be used. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports.

LSI test pins These pins must be either left open or connected to ground.

No. 5065-11/13

LC72358N, 72362N, 72366

Continued on next page.

LC72358N, LC72362N and LC72366 Instruction Table

Abbreviations: ADDR: Program memory address b: Borrow C: Carry DH: Data memory address high (row address): 2 bits DL: Data memory address low (column address):4 bits I: Immediate data:4 bits M: Data memory address N: Bit position Pn: Port number:4 bits PWn: Port control word number: 4 bits r: General register (one of banks 00 to 0FH) Rn: Register number:4 bits ( ): Contents of register or memory ( )N: Contents of bit N of register or memory

Mnemonic

Operand

Function Operation

Machine code

1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0

AD r M Add M to r r ← (r) + (M) 0 1 0 0 0 0 D

ADS r M

Add M to r, r ← (r) + (M)

0 1 0 0 0 1 D

then skip if carry skip if carry

AC r M Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 D

ACS r M

Add M to r with carry, r ← (r) + (M) + C

0 1 0 0 1 1 D

then skip if carry skip if carry

AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 D

AIS M I

Add I to M, M ← (M) + I

0 1 0 1 0 1 D

DL I

then skip if carry skip if carry

AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 D

AICS M I

Add I to M with carry, M ← (M) + I + C

0 1 0 1 1 1 D

then skip if carry skip if carry

SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 D

SUS r M

Subtract M from r, r ← (r) – (M)

0 1 1 0 0 1 D

then skip if borrow skip if borrow

SB r M

Subtract M from r with

r ← (r) – (M) – b 0 1 1 0 1 0 D

borrow Subtract M from r with

r ← (r) – (M) – b

SBS r M borrow,

skip if borrow

0 1 1 0 1 1 D

then skip if borrow

SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 D

SIS M I

Subtract I from M, M ← (M) – I

0 1 1 1 0 1 D

then skip if borrow skip if borrow

SIB M I

Subtract I from M with

M ← (M) – I – b 0 1 1 1 1 0 D

borrow Subtract I from M with

M ← (M) – I – b

SIBS M I borrow,

skip if borrow

0 1 1 1 1 1 D

then skip if borrow

SEQ r M Skip if r equal to M

(r) – M

0 0 0 1 0 0 D

skip if zero

SEQI M I Skip if M equal to I

(M) – I

0 0 0 1 0 1 D

skip if zero

SNEI M I Skip if M not equal to I

(M) – I

0 0 0 0 0 1 D

skip if not zero

Skip if r is greater (r) – M

SGE r M

than or equal to M skip if not borrow

0 0 0 0 1 1 D

Skip if M is greater (M) – I

SGEI M I

than or equal to I skip if not borrow

0 0 0 1 1 1 D

SLEI M I Skip if M is less than I

(M) – I

0 0 0 0 1 1 D

skip if zero

Comparison instructions

Instruction

Group

Addition instructionsSubtraction instructions

No. 5065-12/13

LC72358N, 72362N, 72366

Continued from preceding page.

Mnemonic

Operand

Function Operation

Machine code

1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0

AND r M AND M with r r ← (r) AND (M) 0 0 1 0 0 0 D

ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 1 D

OR r M OR M with r r ← (r) OR (M) 0 0 1 0 1 0 D

ORI M I OR I with M M ← (M) ORI 0 0 1 0 1 1 D

EXL r M Exclusive OR M with r r ← (r) XOR (M) 0 0 1 1 0 0 D

EXLI M I Exclusive OR I with M M ← (M) XOR I 0 0 1 1 0 1 D

SHR r

Shift r right with Carry

0 0 0 0 0 0 0 0 1 1 1 0 r

carry (r)

LD r M Load M to r r ← (M) 1 1 0 1 0 0 D

ST M r Store r to M M ←(r) 1 1 0 1 0 1 D

Move M to destination

MVRD r M M referring to r in [DH, rn] ← (M) 1 1 0 1 1 0 D

the same row Move source M

MVRS M r referring to r to M in M ← [D

, rn] 1 1 0 1 1 1 D

the same row

MVSR M1 M2

Move M to M in

, DL1] ← [DH, DL2] 1 1 1 0 0 0 D

DL1 DL2

the same row

MVI M I Move I to M M ← I 1 1 1 0 0 1 D

Test M bits, then skip

if M (N) = all 1,

TMT M N if all bits specified

then skip

1 1 1 1 0 0 D

are true Test M bits, then skip

if M (N) = all 0,

TMF M N if all bits specified

then skip

1 1 1 1 0 1 D

are false

JMP ADDR Jump to the address PC ← ADDR 1 0 ADDR (14 bits)

CAL ADDR Call subroutine Stack ← (PC) + 1 1 1 0 0 ADDR (12 bits)

RT Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0

RTS

Return from subroutine

PC ← Stack + 1 0 0 0 0 0 0 0 0 1 0 1 0

and skip

RTB

Return from subroutine PC ←Stack

1 1 1 1 1 1 1 1 1 1 0 0

with bank data BANK ← Stack

RTBS

Return from subroutine PC ←Stack + 1

1 1 1 1 1 1 1 1 1 1 0 1

with bank data and skip BANK ← Stack

PC ← Stack

RTI Return from interrupt BANK ← Stack 0 0 0 0 0 0 0 0 1 0 0 1

Carry ← Stack

SS I N Set status register

(Status reg I)

1 1 1 1 1 1 1 1 0 0 0 I N

N ← 1

RS I N Reset status register

(Status reg I)

1 1 1 1 1 1 1 1 0 0 1 I N

N ← 0

TST I N Test status register true

if (Status reg I) N =

1 1 1 1 1 1 1 1 0 1 I N

all 1, then skip

TSF I N Test status register false

if (Status reg I) N =

1 1 1 1 1 1 1 1 1 0 I N

all 0, then skip

Instruction

Group

Logical operation instructionsTransfer instructions

Bit test

instructions

Jump and subroutine call instructions

Status register instructions

No. 5065-13/13

LC72358N, 72362N, 72366

This catalog provides information as of August, 1996. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Continued from preceding page.

Mnemonic

Operand

Function Operation

Machine code

1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0

Test unlock F/F if unlock FF (N) =

TUL N then skip if it has 0, then skip 0 0 0 0 0 0 0 0 1 1 0 1 N

not been set

PLL M r Load M to PLL registers PLL reg ← PLL data 1 1 1 1 1 0 D

INR M Rn

Input register/port

M ← (Rn reg) 0 0 1 1 1 0 D

data to M

OUTR M Rn

Output contents of M

Rn reg ← (M) 0 0 1 1 1 1 D

to register/port SIO I1 I2 Serial I/o control SIO reg ← I1, I2 0 0 0 0 0 0 0 1 I1 I2 UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 0 0 0 0 1 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 0 0 0 0 1 0 I BEEP I Beep control Beep reg ← I 0 0 0 0 0 0 0 0 0 1 1 0 I DZC I Data zone control DZC reg ← I 0 0 0 0 0 0 0 0 1 0 1 1 I TMS N Set timer register Timer reg ← I 0 0 0 0 0 0 0 0 1 1 0 0 N IOS PWn N Set port control word IOS reg PWn ← N 1 1 1 1 1 1 1 0 PWn N IN M Pn Input port data to M M ← (Pn) 1 1 1 0 1 0 D

OUT M Pn Output contents of M to port Pn ← M 1 1 1 0 1 1 D

Pn SPB Pn N Set port bits (Pn) N ← 1 0 0 0 0 0 0 1 0 Pn N RPB Pn N Reset port bits (Pn) N ← 0 0 0 0 0 0 0 1 1 Pn N

Test port bits, if (Pn) N = all 1,

TPT Pn N then skip if all bits then skip 1 1 1 1 1 1 0 0 Pn N

specified are true Test port bits, if (Pn)) N = all 0,

TPF Pn N then skip if all bits then skip 1 1 1 1 1 1 0 1 Pn N

specified are false

BANK I Select bank BANK ← I 0 0 0 0 0 0 0 0 0 1 1 1 I

HALT I Halt mode control

HALT reg ← I, then CPU clock stop

0 0 0 0 0 0 0 0 0 1 0 0 I

CKSTP Clock stop

Stop Xtal OSC if HOLD = 0

0 0 0 0 0 0 0 0 0 1 0 1

NOP No operation No operation 0 0 0 0 0 0 0 0 0 0 0 0

Other

instruc-tions

Instruction

Group

I/O instructions

F/F test

instructions

Internal register

transfer instructions

Bank switching

instructions

Hardware control

instructions

SANYO LC72366, LC72362N, LC72358N Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual