Sanyo LC7233 Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

Single-Chip PLL and Microcontroller

with LCD Driver

Ordering number:ENN3802A

LC7233

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC7233 is a single-chip microcontroller that incorpo­rates a phase-locked loop (PLL), which can operate up to
150MHz, and a liquid-crystal display (LCD) driver, mak­ing it ideal for digital tuners. It has a large number of input/
output ports and a frequency measurement circuit.
The LC7233 freatures on-chip RAM and ROM, a program­mable high-speed divider, a 6-bit analog-to-digital con v erter
and a low-voltage detection reset circuit.
The LC7233 operates from a single 5V supply and is avail­able in 64-pin QIPs.

Features

• 150 MHz phase-locked loop.

• LCD driver.

• 6-bit analog-to-digital converter.

• Two 8-bit PWM digital-to-analog converters.

• Two 4-bit input ports.

• Two 4-bit input/output ports.

• 6-bit keypad matrix scan output.

• 2-bit open-drain high-voltage output.

• 23 mask-selectable output drivers.

• 20-bit universal counter.

• 4096 × 16-bit program ROM (000H to FFFH user-ad-

dressable memory).

• 256 × 4-bit data RAM.

• Low-voltage detection reset circuit.

• Programmable high-speed divider.

• Single-word instructions.

• Four-level stack.

• PLL-unlocked flip-flop.

• Timer flip-flop.

• Programmable watchdog interrupt address.

• Standby mode.

• CPU operates down to 3.5V, with data retention down to

1.3V.

• Single 5V supply.

• 64-pin QIP.

Package Dimensions

unit:mm

3159-QIP64E

[LC7233]

17.2

14.0

0.8

0.35

15.6

17.2

1.6

14.0

1.0

48

1.0

49

0.8

64

1.0

1

Pin Assignment

1.6

1.0

33

32

17

16

0.8

0.15

0.1

3.0max

2.7

SANYO : QIP64E

Top view

71901TN (KT)/6291JN/1201JN No.3802–1/12

Block Diagram

LC7233

No.3802–2/12

Pin Description

rebmuNemaNtiucrictnelaviuqEnoitpircseD

1NIX

46TUOX

LC7233

snoitcennocrotallicsolatsyrC

22TSET

361TSET

6ot30GPot3GPGtroptupnI

8,70HP,1HPHtroptuptuO

21ot90FPot3FP Ftroptuptuo/tupnI

61ot310EPot3EP Etroptuptuo/tupnI

sniptseT

81,710CP,1CPCtroptuptuO

22ot910BPot3BPBtroptuptuO

62ot320APot3APAtroptupnI

94ot721Sot32S stuptuotnemgesDCL

Continued on next page.

No.3802–3/12

Continued from preceding page.

rebmuNemaNtiucrictnelaviuqEnoitpircseD

15,051MOC,2MOC stuptuorevirdnommocDCL

25DLOH tupnilortnocedom-dloH

55SNStcetedliaf-rewoP

35IDAtupniretrevnocD/A

LC7233

45RTCH tupniretnuoclasravinU

65V

75NIMFtupniOCVMF

85NIMAtupniOCVMA

95V

06OE tuptuorotarapmocesahP

16NIAtupnigolanA

DD

SS

ylppusV5

dnuorG

26TUOAtuptuogolanA

No.3802–4/12

LC7233

Specifications

Absolute Maximum Ratings

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppuSV

egatlovtupniSNSdnaIDA,DLOH,GtroPV

)stupnirehto(egatlovtupnIV

egatlovtuptuoTUOAdnaHtroPV

)stuptuorehtolla(egatlovtuptuOV

tnerructuptuoHtroPI

tnerructuptuoFdnaEstroPI

tnerructuptuoCdnaBtsroPI

tnerructuptuoTUOAI

noitapissidrewopelbawollAxamdP 004Wm

erutarepmetgnitarepOrpoT –58+ot04

erutarepmetegarotSgtsT –521+ot54

Reommended Operating Conditions at Ta = 25˚C

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppuSV

)UPCdnaLLP(egnaregatlovylppuSV

)UPC(egnaregatlovylppuSV

noitneteratadrofegnaregatlovylppuSV

xam –5.6+ot3.0V

DD

1NI

2NI

1TUO

2TUO
1TUO
2TUO
3TUO
4TUO

DD

1DD
2DD
3DD

–31+ot3.0V

–Vot3.0

–51+ot3.0V

–Vot3.0

3.0+

DD

DD

V

3.0+

V

5ot0

Am

3ot0

Am

1ot0

Am

2ot0

Am

˚C
˚C

5V

5.5ot5.4V

5.5ot5.3V

5.5ot3.1V

Electrical Characteristics at Ta = –40 to +85˚C, VDD = 3.5 to 5.5V, unless otherwise noted

retemaraPlobmySsnoitidnoC
egatlovtupnilevel-hgihGtroPV

egatlovtupnilevel-hgihSNSV

egatlovtupnilevel-hgihAtroPV

egatlovtupnilevel-hgihFdnaEstroPV

egatlovtupnilevel-hgihDLOHV

egatlovtupnilevel-wolGtroPV

egatlovtupnilevel-wolDLOHV

egatlovtupnilevel-wolSNSV

egatlovtupnilevel-wolAtroPV

egatlovtupnilevel-wolFdnaEstroPV

ycneuqerftupniNIXf

ycneuqerftupniNIMFf

)egnarwol(ycneuqerftupniNIMAf

)egnarhgih(ycneuqerftupniNIMAf

ycneuqerftupniRTCHf

edutilpmatupnismrNIXV

edutilpmatupnismrNIMFV

edutilpmatupnismrNIMAV

edutilpmatupnismrRTCHV

egnaregatlovtupniIDAV

htdiwesluptcejerSNSP

egatlovdlohserhtybdnatSV

tnerruc

tnerructupnilevel-hgihNIXI

tnerructupnilevel-hgihAtroPI

tnerructupnilevel-hgihNIAI

tnerruc

tupnilevel-hgihGtropdnaSNS,IDA,DLOH

tnerructupnilevel-hgihFdnaE,AstroPI

tnerructupnilevel-hgihRTCHdnaNIMA,NIMFI

tupnilevel-wolGtropdnaSNS,IDA,DLOH

tnerructupnilevel-wolFdnaE,AstroPI

1HI
2HI
3HI
4HI
5HI

1LI
2LI
3LI
4LI
5LI

VNI=V5.1ot5.00.45.40.5zHM

1NI

VNI=,V5.1ot1.0V

2NI

VNI=,V5.1ot51.0V
VNI=,V5.1ot1.0V

3NI

VNI=,V5.1ot1.0V

4NI

VNI=,V5.1ot1.0V

5NI

1NI
2NI
3NI
4NI
5NI

jer

TED

I

V

1HI

2HI
3HI

4HI
5HI
6HI

I

1LI

2LI

V5.5= 0.3Aµ

NI

Ron

DPV,NIV=DD

VNIV=

DD

VNIV=

DD

VNIV=

DD

VNIV=

DD

VNIV=

SS

Ron

DPV,NIV=SS

=V5.5ot5.401031

DD

=V5.5ot5.401051

DD

=V5.5ot5.45.001zHM

DD

=V5.5ot5.40.204zHM

DD

=V5.5ot5.44.021zHM

DD

V0.5= 2551Aµ
V0.5=40103Aµ

RsahAtroP,V0.5=

DP

nimpytxam

V7.0

V6.0
V7.0
V8.0

sahAtroP,ecnadepmihgiheraFdnaEstroP

sahAtroP,ecnadepmihgiheraFdnaEstroP

sgnitaR

DD

5.20.8V

DD
DD
DD

0V3.0
0V4.0

03.1V
0V2.0
0V3.0

5.05.1V

1.05.1V

1.05.1V

1.05.1V

0V

7.20.33.3V

V
V

05Aµ

10.00.01An

tinU

0.8V

V

DD

V

DD

0.8V
V

DD

V

DD

V

DD

V

DD

zHM

V

DD

05sµ

0.3Aµ

0.3Aµ

0.3Aµ

Continued on next page.

No.3802–5/12

Continued from preceding page.

retemaraPlobmySsnoitidnoC

tnerructupnilevel-wolNIXI

tnerructupnilevel-wolNIAI

egatlovtupniAtroPV

ecnatsisernwod-llupAtroPR

tnerrucegakaeltuptuoOEI

tnerrucegakaeltuptuoHtroPI
tnerrucegakaeltuptuoTUOAI

tnerrucegakaeltuptuoOEI

egatlovtuptuolevel-hgihOEV

egatlovtuptuolevel-wolOEV

egatlovtuptuolevel-wolTUOXV

egatlovtuptuolevel-wolTUOAV

egatlovtuptuolevel-wolHtroPV

rorreretrevnocD/A

tnerrucylppuSI

tnerrucylppusedom-dloHI

tnerrucylppusedom-ybdnatSI

LC7233

VNIV=

tnerructupnilevel-wolRTCHdnaNIMA,NIMFI

tnerrucegakaeltuptuoFdnaE,C,BstroPI

tnerrucegakaeltuptuoFdnaE,C,BstroPI
egatlovtuptuolevel-hgihCdnaBstroPV
egatlovtuptuolevel-hgihFdnaEstroPV

egatlovtuptuolevel-hgihTUOXV

egatlovtuptuolevel-hgih32Sot1SV

egatlovtuptuolevel-hgih2MOCdna1MOCV

egatlovtuptuolevel-wolCdnaBstroPV

egatlovtuptuolevel-wolFdnaEstroPV

egatlovtuptuolevel-wol32Sot1SV

egatlovtuptuolevel-wol2MOCdna1MOCV

egatlovtuptuolevel-dim2MOCdna1MOCV

3LI
4LI
5LI

FI

DP

1HFFO
2HFFO
3HFFO
4HFFO
1LFFO
2LFFO

1HO
2HO
3HO
4HO
5HO
6HO
1LO

2LO
3LO
4LO
5LO
6LO
7LO
8LO

1M

ε

1DD

2DD

3DD

SS

VNIV=

SS

VNIV=

SS

VDDV5=
VOV=

DD

VOV=

DD

VOV31= 0.5Aµ
VOV31= 0.1Aµ
VOV=

SS

VOV=

SS

I=O1Am
I

Am1

=O

I

Aµ005=

O

I

Aµ002=

O

IO=– Am1.0
I

Aµ52=

O

I

Aµ05=5.00.1

O

I

Am1=

O

I

Aµ005=

O

I

Aµ002=

O

I

Am1.0=

O

I

O

I

Aµ52=3.05.0

O

IOAm5=57.00.2V
V
V
f

VDD=5.5V, oscillator halted, Ta=25˚C
VDD=5.5V, oscillator halted, Ta=25˚C

I,V5=

DD

O

DD

ni

V,zHM031=

t,detlahLLP

cyc
cyc

t,detlahLLP

cyc

.ecnadepmihgihsiAtroP

V3.1=NIA,Am5=

Aµ02=0.25.2

V5.5ot5.4=

DD

V5.5ot5.4=5102Am

sµ76.2=5.1

V,sµ33.31=

DD

V,sµ00.04=

DD

nimpytxam

25
40103Aµ

57

VDD–0.2VDD–0.1VDD–5.0
VDD–0.1
VDD–0.1
VDD–0.1
VDD–0.1

VDD–57.0

–2/1

V5.5ot5.3=0.1
V5.5ot5.3=7.0

sgnitaR

51

10.0

001002kΩ

10.00.01An

10.00.01Aµ

0.01

V50.0

DD

0.3

0.3

0.2

0.1

0.1

0.1

0.1

5.0

57.0

0.3

2/1+bsl

5

1

tinU

Aµ

An

V

Aµ

Aµ
V
V
V
V
V
V
V
V
V
V
V
V
V

V

Amt,detlahLLP

Aµ

Test Circuits

Hold Mode

Notes

1. Ports E and F are selected as output ports.

2. Ports A to H, S1 to S23, COM1 and COM2 are open.

No.3802–6/12

LC7233

Standby Mode

Note

Ports A to H, S1 to S23, COM1 and COM2 are open.

Functional Description

LCD Driver

The LC7233 can drive LCD segments. The LCP and LCD instructions transfer data to the LCD outputs. The LCD
instruction transfers data directly to the LCD outputs. The LCP instruction converts data to 7-segment format before
transfer to the outputs.
S1 to S23 are the driver outputs. The LCD frame rate is 100Hz with a 50% duty cycle. After reset or power-up, a blank
signal is present on all outputs. In standby mode, all outputs are LOW. They can be used as general-purpose outputs if
the appropriate mask option is selected.
COM1 and COM2 are the LCD common driver outputs. Output drive is 50% duty with 50% bias. Upon reset or after
power-up, the normal drive signals are present on these outputs. In standby mode, all outputs are LOW.

Frequency Counter

Frequency measurement is performed at the HCTR input by the 20-bit universal counter. The input frequency range is

0.4 to 12MHz, which is used for measuring AM and FM IF frequencies. Capacitive coupling should be used.

Phase-Locked Loop

The FMIN or AMIN input signal is divided down by a programmable divider, and then compared with the crystal
frequency, which is also divided down using 14 selectable ratios. The phase difference between the two signals is
measured using a phase detector and output on EO.
FMIN is the input pin for the FM VCO input signal. The input frequency range is 10 to 130MHz. Capacitive coupling
should be used.
AMIN is the AM VCO input. The bandwidth is adjustable in two ranges by using the PLL instruction-HIGH (2 to
40MHz) for the SW band, and LOW (0.5 to 10MHz), for the LW and MW bands. Capacitive coupling should be used.

Input/Output Ports
Port A

This input port has a low switching threshold, which is used for keypad matrix inputs. Pull-down resistors for all pins
are available as a mask option. Note that either all or none of the pins should have pull-down resistors. In standby
mode, inputs are ignored.

Ports B and C

These output ports have unbalanced CMOS outputs which are used as keypad matrix scan outputs. Upon reset, outputs
are set LOW, and in standby mode, outputs are high impedance. The outputs can be short-circuited.

Port E

The transfer direction of this input/output port is selected automatically under software control. When an input instruc­tion (IN, TPT, or TPF) is executed, port E is configured for input operation, and an output instruction (OUT, SPB or
RPB), for output operation. Upon reset, all pins become inputs. In standby mode, the output drivers are high imped­ance and the input signals are ignored. All bits should either be inputs or outputs.

No.3802–7/12

LC7233

Port F

The transfer direction of this input/output port is selected by the FPC instruction. Each pin of this port can be set
independently to be an input or an output. Upon reset, all pins become inputs. In standby mode, the output drivers are
high impedance and the input signals are ignored.

Port G

This is an input port only. In standby mode, inputs are ignored.

Port H

These output ports are high-voltage, n-channel open-drain drivers, which are used for switching power supplies. Upon
reset and in standby mode, outputs are high impedance. Port H can also be configured as the output of DACI and
DAC2.

A/D Converter

The A/D converter is a 6-bit successive approximation type. The conversion cycle time is 1.28 ms. Full-scale output
data is 3FH for an input of VDD × (63/96).

Power-Fail Detection

When connected to the supply, SNS is used as a power-fail detector. SNS can also be used as a standard input port.

Crystal Oscillator

The master crystal oscillator, which has a feedback resistor on-chip, requires only the connection of a 4.5 MHz crystal.

Low-Power Modes
Hold Mode

When the hold-mode control pin, HOLD, is driven LOW and the HOLDEN (hold enable) flip-flop has previously been
set by an SS instruction, the LC7233 enters hold mode.
HOLD has a high-voltage input (VIH(max) = 8.0V) which can be connected directly to the power supply.

Standby Mode

When the LC7233 is in hold mode and HOLD is LOW, standby mode can be set by the CKSTP instruction.

Test Pins

Two device test pins are provided-TEST1 and TEST2. These should either be tied to VSS or left open.

Instruction Set

ADDR Program memory address [12 bits]
b Borrow
B Bank number [2 bits]
C Carry
DH Data memory address high-order bits (row address) [2 bits]
DL Data memory address low-order bits (column address) [4 bits]
I Immediate data [4 bits]
M Data memory address
N Bit position [4 bits]
Pn Port number [4 bits]
r General register (Bank 00H to 0FH)
Rn Register number [4 bits]
( ) Contents of register or memory
( )n Contents of bit N of register or memory

No.3802–8/12

LC7233

cinomenM

dnarepO

noitarepO

tamrofnoitcurtsnI

noitatoNnoitpircseD

pikS

noitidnoc

ts1dn2

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

ddAsnoitcurtsni

DArM

.rotMddA

010000 HDLDnRr← )M(+)r(

ehtserotsdnarfostnetnocehtotMfostnetnocehtsddA

.rnitluser

SDArM

fipiksdnarotMddA

.yrrac

010001 HDLDnR

r ← ,)M(+)r(

yrracfipiks

ehtserotsdnarfostnetnocehtotMfostnetnocehtsddA

.detarenegsiyrracafispikS.rnitluser

yrraC

CArM

.yrrachtiwrotMddA

010010 HDLDnRr← C+)M(+)r(

dnaCdnarfostnetnocehtotMfostnetnocehtsddA

.rnitluserehtserots

SCArM

yrrachtiwrotMddA

.yrracfipiksdna

010011 HDLDnR

r ← ,C+)M(+)r(

yrracfipiks

dnaCdnarfostnetnocehtotMfostnetnocehtsddA

.detarenegsiyrracafispikS.rnitluserehtserots

yrraC

IAMI

.MotIddA

010100 HDLDIM← I+)M(

serotsdnaMfostnetnocehtotatadetaidemmiehtsddA

.Mnitlusereht

SIAMI

fipiksdnaMotIddA

.yrrac

010101 HDLDI

M ← ,I+)M(

yrracfipiks

serotsdnaMfostnetnocehtotatadetaidemmiehtsddA

.detarenegsiyrracafispikS.Mnitlusereht

yrraC

CIAMI

.yrrachtiwMotIddA

010110 HDLDIM← C+I+)M(

dnaCdnaMfostnetnocehtotatadetaidemmiehtsddA

.Mnitluserehtserots

SCIAMI

yrrachtiwMotIddA

.yrracfipiksdna

010111 HDLDI

M ← ,C+I+)M(

yrracfipiks

dnaCdnaMfostnetnocehtotatadetaidemmiehtsddA

.detarenegsiyrracafispikS.Mnitluserehtserots

yrraC

tcartbuSsnoitcurtsni

USrM

.rmorfMtcartbuS

011000 HDLDnRr← )M(–)r(

dnarfostnetnocehtmorfMfostnetnocehtstcartbuS

.rnitluserehtserots

SUSrM

dnarmorfMtcartbuS

.worrobfipiks

011001 HDLDnR

r ← ,)M(–)r(

worrobfipiks

dnarfostnetnocehtmorfMfostnetnocehtstcartbuS

.detarenegsiworrobafispikS.rnitluserehtserots

worroB

BSrM

htiwrmorfMtcartbuS

.worrob

0 110 10 HDLDnRr← b–)M(–)r(

htiwrfostnetnocehtmorfMfostnetnocehtstcartbuS

.rnitluserehtserotsdnaworrob

SBSrM

htiwrmorfMtcartbuS

fipiksdnaworrob

.worrob

011011 HDLDnR

r ← ,b–)M(–)r(

worrobfipiks

htiwrfostnetnocehtmorfMfostnetnocehtstcartbuS

siworrobafispikS.rnitluserehtserotsdnaworrob

.detareneg

worroB

ISMI

.MmorfItcartbuS

011100 HDLDIM← I–)M(

dnaMfostnetnocehtmorfatadetaidemmiehtstcartbuS

.Mnitluserehtserots

SISMI

dnaMmorfItcartbuS

.worrobfipiks

011101 HDLDI

M ← ,I–)M(

worrobfipiks

dnaMfostnetnocehtmorfatadetaidemmiehtstcartbuS

.detarenegsiworrobafispikS.Mnitluserehtserots

worroB

BISMI

htiwMmorfItcartbuS

.worrob

011110 HDLDIM← b–I–)M(

htiwMfostnetnocehtmorfatadetaidemmiehtstcartbuS

.Mnitluserehtserotsdnaworrob

SBISMI

htiwMmorfItcartbuS

fipiksdnaworrob

.worrob

011111 HDLDI

M ← ,b–I–)M(

worrobfipiks

htiwMfostnetnocehtmorfatadetaidemmiehtstcartbuS

siworrobafispikS.Mnitluserehtserotsdnaworrob

.detareneg

worroB

erapmoCsnoitcurtsni

QESrM

.MslauqerfipikS

000001 HDLDnR

fipiks,)M(–)r(

orez

erayehtfispiksdnaMdnarfostnetnocehtserapmoC

.lauqe

)M(=)r(

EGSrM

nahtretaergsirfipikS

.Motlauqero

000011 HDLDnR

tonfipiks,)M(–)r(

)r(worrob ≥ )M(

retaergsirfispiksdnaMdnarfostnetnocehtserapmoC

.Motlauqeronaht

)M()r(

IQESMI

.IslauqeMfipikS

001101 HDLDI orezfipiks,I–)M(

dnaMfostnetnocehtotatadetaidemmiehtserapmoC

.lauqeerayehtfispiks

0=I–)M(

IEGSMI

retaergsiMfipikS

.Iotlauqeronaht

001111 HDLDI

tonfipiks,I–)M(

)M(worrob ≥ I

dnaatadetaidemmiehthtiwMfostnetnocehtserapmoC

.IotlauqeronahtretaergsiMfispiks

I)M(

Continued on next page.

No.3802–9/12

LC7233

cinomenM

dnarepO

noitarepO

tamrofnoitcurtsnI

noitatoNnoitpircseD

pikS

noitidnoc

ts1dn2

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

citemhtiracigoLsnoitcurtsni

DNAMI

.MhtiwIDNA

001100 HDLDIM← )M( ⋅ I

ehtdnaatadetaidemmiehtfoDNA-cigolehtsetaluclaC

.MnitluserehtserotsdnaMfostnetnoc

ROMI

.MhtiwIRO

001110 HDLDIM← I+)M(

ehtdnaatadetaidemmiehtfoRO-cigolehtsetaluclaC

.MnitluserehtserotsdnaMfostnetnoc

LXErM

.rhtiwMRO-evisulcxE

001000 HDLDnRr← )M(+)r(

dna,MdnarfostnetnocehtfoROX-cigolehtsetaluclaC

.rnitluserehtserots

erotsdnadaoLsnoitcurtsni

DLrM

.rotniMdaoL

100000 HDLDnRr← )M(

.rotMfostnetnocehtsevoM

TSMr

.MnirerotS

100001 HDLDnRM← )r(

.MotrfostnetnocehtsevoM

DRVMrM

MotMevoM

.nRybdesserdda

100010 HDLDnR]nR,HD[ ← )M(

HDybdecnerefersserddaehtotMfostnetnocehtsevoM

.nRdna

SRVMMr

ybdesserddaMevoM

.MotnR

100011 HDLDnRM← ]nR,HD[

ybdecnerefernoitacolyromemehtfostnetnocehtsevoM

.MotnRdnaHD

RSVMM

1

M

2

.MotMevoM

100100 HDLD

1

LD

2

LD.HD[

1

] ← LD.HD[

2

]

yromemot2noitacolyromemfostnetnocehtsevoM

.1noitacol

IVMMI

.MotIevoM

100101 HDLDIM← I

.MotatadetaidemmiehtsevoM

LLPMr

LLPotMdaoL

.sretsiger

100110 HDLDnRrLLP ← ATADLLP

.sretsigerLLPehtotMfostnetnocehtsevoM

tsettiBsnoitcurtsni

TMTMN

piksdnaMfostibtseT

erutfi

10 100 1 HDLDN 1lla=)N(Mfipiks

fispikS.NybdeificepsMnoitacolyromemfostibehtstseT

.1cigolerastiblla

stibllA

1=deificeps

FMTMN

piksdnaMfostibtseT

eslaffi

10 10 11 HDLDN 0lla=)N(Mfipiks

fispikS.NybdeificepsMnoitacolyromemfostibehtstseT

.0cigolerastiblla

stibllA

0=deificeps

enituorbusdnapmuJsnoitcurtsni

PMJRDDA

sserddaotpmuJ

10 11 )stib21(RDDACP ← RDDA

.RDDAybdeificepssserddaehtotspmuJ

LACRDDA

enituorbusllaC

1100 )stib21(RDDAkcatS ← 1+)CP(

.RDDAybdeificepsenituorbusehtotspmuJ

TR

enituorbusmorfnruteR

1101010000000000CP ← kcats

.enituorbusamorfsnruteR

tsetgalFsnoitcurtsni

MTTN

polf-pilfremittseT

110101100000 N 0=F/FremitfipikS

.orezfispiksdnapolf-pilfremitehtstseT 0=F/FremiT

LUTN

polf-pilfLLPtseT

110101110000 N 0=F/FLLPfipikS

.orezfispiksdnapolf-pilfdekcolnu-LLPehtstseT 0=F/FLLP

tesdnatsetretsigersutatSsnoitcurtsni

SSN

stibretsigersutatsteS

110111000000 N

N)1retsigersutatS( ← 1

.NybdeificepsretsigersutatsehtfostibehtsteS

SRN

retsigersutatsteseR

stib

110111010000 N

N)1retsigersutatS( ← 0

.NybdeificepsretsigersutatsehtfostibehtsteseR

TSTN

retsigersutatstseT

eurtfipiksdnastib

110111100000 N

)2retsigersutatS(fipikS

1lla=N

llafispikS.Nybdeificeps2retsigersutatsfostibehtstseT

.1erastib

stibllA

1=deificeps

FSTN

retsigersutatstseT

eslaffipiksdnastib

110111110000 N

)2retsigersutatS(fipikS

0lla=N

llafispikS.Nybdeificeps2retsigersutatsfostibehtstseT

.0erastib

stibllA

0=deificeps

tcelesknaBnoitcurtsni

KNABB

knabtceleS

110100 B 00000000

KNAB ← B

.sknabyromemruoffoenostceleS

Continued on next page.

Continued from preceding page.

No.3802–10/12

LC7233

cinomenM

dnarepO

noitarepO

tamrofnoitcurtsnI

noitatoNnoitpircseD

pikS

noitidnoc

ts1dn2

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

tuptuo/tupnIsnoitcurtsni

DCLMI

DCLotatadevoM

.stnemges

111000 HDLDTIGID

)TIGID(DCL ← M.revirdDCLehtotyltceridatadetaidemmiehtsdaoL

PCLMI

atadtnemges-7evoM

.DCLot

111001 HDLDTIGID

)TIGID(DCL ← ALP ←

M

agnisutamroftnemges-7otatadetaidemmiehtstrevnoC

.revirdDCLehtottisrefsnartnehtALP

NIMnP

.MotatadtropevoM

111010 HDLDP

M ← ))nP(trop(.MotnPtroptupnimorfatadehtsevoM

TUOMnP

.tropotatadevoM

111011 HDLDP

))nP(trop( ← M.nPtropotMnoitacolyromemfostnetnocehtsevoM

BPSnPN

.stibtropteS

11110000 P N

N))nP(trop( ← 1.1cigolot,Nybdeificeps,nPtropfostibehtsteS

BPRnPN

.stibtropteseR

11110101 P N

N))nP(trop( ← 0.0cigolot,Nybdeificeps,nPtropfostibehtsteS

TPTnPN

dnatropfostibtseT

.eurtfipiks

11111010 P N

1lla=N))nP(trop(fipikS

erastibllafispikS.NybdeificepsnPtropfostibehtstseT

.1cigol

stibllA

1=deificeps

FPTnPN

dnatropfostibtseT

.eslaffipiks

11111111 P N

0lla=N))nP(trop(fipikS

erastibllafispikS.NybdeificepsnPtropfostibehtstseT

.0cigol

stibllA

0=deificeps

retnuoclasrevinUsnoitcurtsni

SCUI

.1WCCUteS

000000010000 I

1WCCU ← I.1galfretnuoclasrevinuehtsteS

CCUI

.2WCCUteS

000000110000 I

2WCCU ← I.2galfretnuoclasrevinuehtsteS

suoenallecsiMsnoitcurtsni

CPFN

.lortnocnoitceridFtroP

000100000000 N

hctalCPF ← N

nitibafI.FtropfosniplaudividnifonoitceridehtsenifeD

eht,CPFybtessiretsigernoitceridFtropeht

.tuptuonasemocebFtropfonipgnidnopserroc

PTSKC

.kcolcpotS

0001000100000000

0=DLOHfikcolcpotS0=DLOHfikcolcrossecorpehtspotS

CADI

CADotatadevoM

sretsiger

000000100000 I

CAD

r

← ATADCAD.sretsigerCADehtotatadetaidemmiehtsdaoL

PON

noitarepooN

000000000000

noitarepooN

Continued from preceding page.

No.3802–11/12

LC7233

Mask Option

retemaraP snoitpO

)TDW(remitgodhctaW

)troptupnixirtamdapyekeht(Atropnosrotsisernwod-lluP

emitelcycnoitcurtsnI

noitarugifnoc32Sot1S

Development System

The LC7223 development environment is shown in figure 1. It uses an LC72EV32 evaluation chip mounted on a TB­72EV32 target board and a multifunctional emulator (RE32), which is controlled by a personal computer, to provide
full debugging facilities.

seY

oN

seY

oN

sµ76.2

sµ33.31
sµ00.04

troptuptuorevirdDCL

troptuptuoesoprup-lareneG

Figure 1. Development system

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of July, 2001. Specifications and information herein are subject to
change without notice.

PS No.3802–12/12