Sanyo LC72319 Specifications

Ordering number : ENN7022

60401TN (OT) No. 7022-1/14

Overview

The LC72317, 72318 and 72319 are low-voltage electronic tuning radio microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs include an on-chip DC-DC converter, making it is easy to create the supply voltages required for tuning and allowing cost reductions in end products. These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver.

Function

• Program memory (ROM):

— 6144 × 16 bits (12K bytes) LC72317 — 8192 × 16 bits (16K bytes) LC72318/319

• Data memory (RAM):

— 256 × 4 bits LC72317/318 — 512 × 4 bits LC72319

• Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation

• Stack: 8 levels

• LCD driver: 48 to 112 segments (1/4 duty, 1/2 bias

drive)

• Interrupts: Two external interrupts

Timer interrupts (1, 5, 10, and 50 ms)

• A/D converter: Three input channels

(5-bit successive approximation conversion)

• Input ports: 9 ports (of which three can be switched for use as A/D converter inputs)

• Output ports: 6 ports (of which 1 can be switched for use

as the beep tone output and 2 are opendrain ports)

Continued on next page.

Package Dimensions

unit: mm

3220-SQFP80

14.0

12.0

1.25 1.25

0.5

14.0

12.0

1.25

0.5

120

21

40

41

60

61

80

0.1

0.5

1.6max

1.4

0.5

0.2

0.135

SANYO: SQFP80

[LC72317, 72318, 72319]

LC72317, 72318, 72319

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Low-Voltage ETR-Controller

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

No. 7022-2/14

LC72317, 72318, 72319

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max VDD –0.3 to +4.0 V

Input voltage V

IN

All input pins –0.3 to VDD+0.3 V

Output voltage

V

OUT

(1) AOUT, PE –0.3 to +15 V

V

OUT

(2) All output pins except V

OUT

(1) –0.3 to VDD+ 0.3 V

I

OUT

(1) PC, PD, PG, PH, PI, PJ, PK, PL, EO 0 to 3 mA

I

OUT

(2) PB 0 to 1 mA

Output current I

OUT

(3) AOUT, PE 0 to 2 mA

I

OUT

(4) S1 to S28 300 µA

I

OUT

(5) COM1 to COM4 3 mA Allowable power dissipation Pdmax Ta = –20 to +70°C 300 mW Operating temperature Topr –20 to +70 °C Storage temperature Tstg –45 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Continued from preceding page.

I/O ports: 29 pins (Of these 16 can be switched over to

function as LCD ports as a mask options, and 3 ports can be switched over for use with serial I/O.)

• Serial I/O: One system

• Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz

• Input frequencies: FM band: 10 to 250 MHz

AM band: 0.5 to 20 MHz

• Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher

frequency)

AM band: 35 mVrms

• IF counting: Using the HCTR input pin for 0.4 to

12 MHz signals

• External reset input: During CPU and PLL operations,

instruction execution is started from location 0.

• Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied.

• Halt mode: The controller-operating clock is stopped.

• Backup mode: The crystal oscillator is stopped.

• Static power-on function: Backup state is cleared with the PF port

• Beep tone: 1.5 and 3.1 kHz

• Built-in tuner voltage generating circuit:

Cost reduced in tuner-use power supply circuit

• Memory retention voltage: 0.9 V at least

• VDDvoltage

— PLL: 1.8 to 3.6 V — CPU and ADC: 1.6 to 3.6 V

• Optional function switches:

— PH0 to PH3 (open-drain output/general-purpose

input and output/S13 to S16)

— PG0 to PG3 (open-drain output/general-purpose

input and output/S17 to S20)

— PI0 to PI3 (open-drain output/general-purpose input

and output/S21 to S24)

— PJ0 to PJ3 (open-drain output/general-purpose input

and output/S25 to S28) — VSENSE circuit (provided/not provided) — FM DC/DC clock (1/256, 75 kHz)

• Package: SQFP-80 (0.5-mm pitch)

No. 7022-3/14

LC72317, 72318, 72319

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

DD

(1) PLL operating voltage 1.8 3.0 3.6

Supply voltage

V

DD

(2) Memory retention voltage 1.0

V

DD

(3) CPU operating voltage 1.4 3.0 3.6

V

DD

(4) A/D converter operating voltage 1.6 3.0 3.6

V

IH

(1)

Input ports other than V

IH

(2), VIH(3), AMIN,

0.7 V

DD

V

DD

V

Input high-level voltage

FMIN, HCTR, and XIN

V

IH

(2) BRES port 0.8 V

DD

V

DD

V

IH

(3) Port PF 0.6 V

DD

V

DD

V

IL

(1)

Input ports other than V

IL

(2), VIL(3), AMIN,

0 0.3 V

DD

V

Input low-level voltage

FMIN, HCTR, and XIN

V

IL

(2) BRES port 0 0.2 V

DD

V

IL

(3) Port PF 0 0.2 V

DD

V

IN

(1) XIN 0.5 0.6 Vrms

Input amplitude

V

IN

(2) FMIN, AMIN 0.035 0.35 Vrms

V

IN

(3) FMIN 0.05 0.35 Vrms

V

IN

(4) HCTR 0.035 0.35 Vrms

Input voltage range V

IN

(5) ADIO, ADI1, ADI3 0 V

DD

V

F

IN

(1) XIN: CI ≤ 35 kΩ 70 75 80 kHz

F

IN

(2) FMIN: VIN(2), VDD(1) 10 130 MHz

Input frequency

F

IN

(3) FMIN: VIN(3), VDD(1) 130 250 MHz

F

IN

(4) AMIN(H): VIN(3), VDD(1) 2 40 MHz

F

IN

(5) AMIN(L): VIN(3), VDD(1) 0.5 10 MHz

F

IN

(6) HCTR: VIN(3), VDD(1) 0.4 12 MHz

Allowable Operating Ranges at Ta = –20 to +70°C, VDD= 1.8 to 3.6 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

I

IH

(1) XIN: VI= VDD= 3.0 V 3 µA

Input high-level current

I

IH

(2) FMIN, AMIN, HCTR: VI= VDD= 3.0 V 3 8 20 µA

PA/PF (without pull-down resistors), the PC,

IIH(3) PD, PG, PH, PI, PJ, PK, and PL ports, 3 µA

and BRES: V

I

= VDD= 3.0 V

I

IL

(1) XIN: V

DD(1)

= V

SS

–3 µA

Input low-level current

I

IL

(2) FMIN, AMIN, HCTR: VI= VDD= V

SS

–3 –8 –20 µA

PA/PF (without pull-down resistors), the PC,

IIL(3) PD, PG, PH, PI, PJ, PK, and PL ports, –3 µA

and BRES: V

I

= VDD= V

SS

Input floating voltage V

IF

PA/PF (with pull-down resistors) 0.05 V

DD

V

Pull-down resistor values

R

PD

(1) PA/PF (with pull-down resistors), VDD= 3.0 V 75 100 200 kΩ

R

PD

(2) TEST1, TEST2 (with pull-down resistors) 10 kΩ

Hysteresis V

H

BRES 0.1 V

DD

0.2 V

DD

V

Voltage doubler reference voltage

DBR4

Referenced to V

DD

, C(3) = 0.47 µF,

1.3 1.5 1.7 V

Ta = 25°C *

1

Voltage doubler step-up voltage DBR1, 2, 3

C(1) = 0.47 µF

2.7 3.0 3.3 V

C(2) = 0.47 µF, without loading, Ta = 25°C *

1

VOH(1) PB: IO= –1 mA

V

DD

– VDD– V

0.7 V

DD

0.3 V

DD

VOH(2) PC, PD, PG, PH, PI, PJ, PK, PL: IO= –1 mA

V

DD

–

V

0.3 V

DD

VOH(3) EO: IO= –500 µA

V

DD

–

V

Output high-level voltage 0.3 V

DD

VOH(4) XOUT: IO= –1 µA

V

DD

–

V

0.3 V

DD

VOH(5) S1 to S28: IO= –20 µA *

1

2.0 V

V

OH

(6)

COM1, COM2, COM3, COM4:

2.0 V

I

O

= –100 µA *

1

Electrical Characteristics within the allowable operating ranges

Continued on next page.

No. 7022-4/14

LC72317, 72318, 72319

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

OL

(1) PB: IO= –1 mA 0.3 V

DD

0.7 V

DD

V

OL

(2)

PC, PD, PG, PH, PI, PJ, PK, PL: IO= –1 mA

0.3 V

DD

V

OL

(3) EO: IO= –500 µA 0.3 V

DD

V

OL

(4) XOUT: IO= –1 µA 0.3 V

DD

V

Output low-level voltage V

OL

(5) S1 to S28: IO= –20 µA *

1

1.0 V

V

OL

(6)

COM1, COM2, COM3, COM4:

1.0 V

I

O

= –100 µA *

1

VOL(7) PE: IO= 2 mA 1.0 V V

OL

(8)

AOUT, TU: IO= 1 mA, AIN = 1.3 V (AOUT), VDD= 3 V

0.5 V

Output off leakage current

I

OFF

(1)

Ports PB, PC, PD, PG, PH, PI, PJ, PK, PL, and EO

–3 +3 µA

I

OFF

(2) AOUT, TU and port PE –100 +100 nA A/D converter error ADI0, ADI1, ADI3 –1/2 +1/2 LSB Supply voltage drop detection voltage V

SENSE

(1) Ta = 25°C *

2

1.6 1.75 1.9 V

Supply voltage rise detection voltage V

SENSE

(2) Ta = 25°C *

2

(1)min (1)max

V

+0.1 +0.2

I

DD

(1) VDD(1): FIN(2) 130 MHz, Ta = 25°C 5 15 mA

I

DD

(2) VDD(1): In HALT mode, Ta = 25°C *

3

0.1 mA

Current drain I

DD

(3)

V

DD

= 3.6 V, with the oscillator stopped,

0.1 mA

Ta = 25°C *

4

IDD(4)

V

DD

= 1.8 V, with the oscillator stopped,

1 µA

Ta = 25°C *

4

Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.

Continued from preceding page.

Pin Assignment

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

COM4S1S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13/PH0

S14/PH1

S15/PH2

S16/PH3

S17/PG0

S18/PG1

S19/PG2

XOUT

I

O

I / O I / O

I / O

I / OI / OI / OI / O

I / O

O (OD)

TEST2

PA3

PA2

PA1

PA0

PB3

PB2

PB1

PB0

PC3

PC2

PC1

PC0

PL2

PL1

PL0

PD3

PD2

INT1/PD1

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

INT0/PD0

SI1/PK3

SO1/PK2

SCK1/PK1

PK0

PE1

BEEP/PE0

ADI3/PF2

ADI1/PF1

ADI0/ PF0

VSS

S28/PJ3

S27/PJ2

S26/PJ1

S25/PJ0

S24/PI3

S23/PI2

S22/PI1

S21/PI0

S20/PG3

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

XIN

TEST1

AGND

AOUT

AIN

EO

VSS

AMIN

FMIN

VDD

HCTR

TU

BRES

DBR1

DBR2

DBR3

DBR4

COM1

COM2

COM3

Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.

No. 7022-5/14

LC72317, 72318, 72319

DBR1 DBR2 DBR3

0.1 to 1 µF

C(C1)

C(C2)

DBR4

C(C3)

Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.

*2. V

SENSE

When the VDDvoltage drops, the V

SENSE

flag is set when that voltage is 1.75 V (typical). Applications can

check the V

SENSE

flag using the TST instruction. Battery or other power source depletion can be easily measured by monitoring this flag. Note that the voltage for V

SENSE

detection differs for the falling and rising directions. Thus, after the V

SENSE

flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.

V

DD

t

1.9 V

1.6 V → SETRESET←

V

DD

t

2.1 V

1.7 V →RESETSET←

A A

7 pF 7 pF

FMIN

XIN

AMIN

TEST1, 2

HCTR

XOUT

VDD

DBR2

DBR1

0.1 µF

DBR3 DBR4

RESRES

VSS

PA, PF, PL

AGND

AIN

FMIN

XIN

AMIN

TEST1, 2

HCTR

XOUT VDD

VSS

AGND

AIN

7pF

75 kHz 75 kHz

7pF

DBR2 DBR3

DBR4

V

SENSE

(1)

For a falling voltage

*3. Halt mode current measurement circuit *4. Backup mode current measurement circuit

With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S28 selected.

V

SENSE

(2)

For a rising voltage