Sanyo LC72319 Specifications

Ordering number : ENN7022

CMOS IC

LC72317, 72318, 72319

Low-Voltage ETR-Controller

Overview

The LC72317, 72318 and 72319 are low-voltage electronic tuning radio microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs include an on-chip DC-DC converter, making it is easy to create the supply voltages required for tuning and allowing cost reductions in end products.

These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver.

Function

• Program memory (ROM):
— 6144 × 16 bits (12K bytes)		LC72317
— 8192 × 16 bits (16K bytes)		LC72318/319
• Data memory (RAM):
— 256 × 4 bits	LC72317/318
— 512 × 4 bits	LC72319

• Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation

•Stack: 8 levels

•LCD driver: 48 to 112 segments (1/4 duty, 1/2 bias drive)

•Interrupts: Two external interrupts

Timer interrupts (1, 5, 10, and 50 ms)

• A/D converter: Three input channels

(5-bit successive approximation conversion)

• Input ports: 9 ports (of which three can be switched for use as A/D converter inputs)

• Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports)

Continued on next page.

Package Dimensions

unit: mm

3220-SQFP80

[LC72317, 72318, 72319]

14.0

12.00.135

1.25	0.5	1.25
60		41

61

40

		1.25
14.0	12.0	0.5
		1.25

80		21
			1.6max
1		1.4
	0.2	20
		0.1

0.5 0.5

SANYO: SQFP80

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

60401TN (OT) No. 7022-1/14

LC72317, 72318, 72319

Continued from preceding page.

I/O ports: 29 pins (Of these 16 can be switched over to function as LCD ports as a mask options, and 3 ports can be switched over for use with serial I/O.)

•Serial I/O: One system

•Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz

•Input frequencies: FM band: 10 to 250 MHz

AM band: 0.5 to 20 MHz

•Input sensitivity:

FM band: 35 mVrms (50 mVrms at 130 MHz or higher frequency)

AM band: 35 mVrms

•IF counting: Using the HCTR input pin for 0.4 to

12 MHz signals

• External reset input: During CPU and PLL operations, instruction execution is started from location 0.

•Built-in power-on reset circuit:

The CPU starts execution from location 0 when power is first applied.

•Halt mode: The controller-operating clock is stopped.

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

•Backup mode: The crystal oscillator is stopped.

•Static power-on function: Backup state is cleared with

the PF port

•Beep tone: 1.5 and 3.1 kHz

•Built-in tuner voltage generating circuit:

Cost reduced in tuner-use power supply circuit

•Memory retention voltage: 0.9 V at least

•VDD voltage

—PLL: 1.8 to 3.6 V

—CPU and ADC: 1.6 to 3.6 V

•Optional function switches:

—PH0 to PH3 (open-drain output/general-purpose input and output/S13 to S16)

—PG0 to PG3 (open-drain output/general-purpose input and output/S17 to S20)

—PI0 to PI3 (open-drain output/general-purpose input and output/S21 to S24)

—PJ0 to PJ3 (open-drain output/general-purpose input and output/S25 to S28)

—VSENSE circuit (provided/not provided)

—FM DC/DC clock (1/256, 75 kHz)

•Package: SQFP-80 (0.5-mm pitch)

	Parameter	Symbol	Conditions	Ratings	Unit
	Maximum supply voltage	VDD max	VDD	–0.3 to +4.0	V
	Input voltage	VIN	All input pins	–0.3 to VDD +0.3	V
	Output voltage	VOUT(1)	AOUT, PE	–0.3 to +15	V
		VOUT(2)	All output pins except VOUT(1)	–0.3 to VDD + 0.3	V
		IOUT(1)	PC, PD, PG, PH, PI, PJ, PK, PL, EO	0 to 3	mA
		IOUT(2)	PB	0 to 1	mA
	Output current	IOUT(3)	AOUT, PE	0 to 2	mA
		IOUT(4)	S1 to S28	300	µA
		IOUT(5)	COM1 to COM4	3	mA
	Allowable power dissipation	Pdmax	Ta = –20 to +70°C	300	mW
	Operating temperature	Topr		–20 to +70	°C
	Storage temperature	Tstg		–45 to +125	°C

No. 7022-2/14

LC72317, 72318, 72319

Allowable Operating Ranges at Ta = –20 to +70°C, VDD = 1.8 to 3.6 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
		VDD(1)	PLL operating voltage	1.8	3.0	3.6
	Supply voltage	VDD(2)	Memory retention voltage	1.0			V
		VDD(3)	CPU operating voltage	1.4	3.0	3.6
		VDD(4)	A/D converter operating voltage	1.6	3.0	3.6
		VIH(1)	Input ports other than VIH(2), VIH(3), AMIN,	0.7 VDD		VDD	V
	Input high-level voltage		FMIN, HCTR, and XIN
		VIH(2)	BRES port	0.8 VDD		VDD	V
		VIH(3)	Port PF	0.6 VDD		VDD	V
		VIL(1)	Input ports other than VIL(2), VIL(3), AMIN,	0		0.3 VDD	V
	Input low-level voltage		FMIN, HCTR, and XIN
		VIL(2)	BRES port	0		0.2 VDD	V
		VIL(3)	Port PF	0		0.2 VDD	V
		VIN(1)	XIN	0.5		0.6	Vrms
	Input amplitude	VIN(2)	FMIN, AMIN	0.035		0.35	Vrms
		VIN(3)	FMIN	0.05		0.35	Vrms
		VIN(4)	HCTR	0.035		0.35	Vrms
	Input voltage range	VIN(5)	ADIO, ADI1, ADI3	0		VDD	V
		FIN(1)	XIN: CI ≤ 35 kΩ	70	75	80	kHz
		FIN(2)	FMIN: VIN(2), VDD(1)	10		130	MHz
	Input frequency	FIN(3)	FMIN: VIN(3), VDD(1)	130		250	MHz
		FIN(4)	AMIN(H): VIN(3), VDD(1)	2		40	MHz
		FIN(5)	AMIN(L): VIN(3), VDD(1)	0.5		10	MHz
		FIN(6)	HCTR: VIN(3), VDD(1)	0.4		12	MHz

Electrical Characteristics within the allowable operating ranges

	Parameter	Symbol			Conditions		Ratings		Unit
						min	typ	max
		IIH(1)	XIN: VI = VDD = 3.0 V					3	µA
	Input high-level current	IIH(2)	FMIN, AMIN, HCTR: VI = VDD = 3.0 V			3	8	20	µA
			PA/PF (without pull-down resistors), the PC,
		IIH(3)	PD, PG, PH, PI, PJ, PK, and PL ports,					3	µA
			and BRES: VI = VDD = 3.0 V
		IIL(1)	XIN: VDD(1) = VSS					–3	µA
	Input low-level current	IIL(2)	FMIN, AMIN, HCTR: VI = VDD = VSS			–3	–8	–20	µA
			PA/PF (without pull-down resistors), the PC,
		IIL(3)	PD, PG, PH, PI, PJ, PK, and PL ports,					–3	µA
			and BRES: VI = VDD = VSS
	Input floating voltage	VIF	PA/PF (with pull-down resistors)					0.05 VDD	V
	Pull-down resistor values	RPD(1)	PA/PF (with pull-down resistors), VDD = 3.0 V			75	100	200	kΩ
		RPD(2)	TEST1, TEST2 (with pull-down resistors)				10		kΩ
	Hysteresis	VH	BRES			0.1 VDD	0.2 VDD		V
	Voltage doubler reference voltage	DBR4	Referenced to VDD, C(3) = 0.47 µF,			1.3	1.5	1.7	V
			Ta = 25°C *1
	Voltage doubler step-up voltage	DBR1, 2, 3	C(1) = 0.47 µF			2.7	3.0	3.3	V
			C(2) = 0.47 µF, without loading, Ta = 25°C *1
		VOH(1)	PB: IO = –1 mA			VDD –		VDD –	V
						0.7 VDD		0.3 VDD
		VOH(2)	PC, PD, PG, PH, PI, PJ, PK, PL: IO = –1 mA			VDD –			V
						0.3 VDD
		VOH(3)	EO: IO = –500 µA			VDD –			V
	Output high-level voltage					0.3 VDD
		VOH(4)	XOUT: IO = –1 µA			VDD –			V
						0.3 VDD
		V (5)	S1 to S28: I	O	= –20 µA *1	2.0			V
		OH
		VOH(6)	COM1, COM2, COM3, COM4:			2.0			V
			IO = –100 µA *1

Continued on next page.

No. 7022-3/14

LC72317, 72318, 72319

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

VOL(1)

PB: IO = –1 mA

0.3 VDD

0.7 VDD

V

VOL(2)

PC, PD, PG, PH, PI, PJ, PK, PL: IO = –1 mA

0.3 VDD

V

VOL(3)

EO: IO = –500 µA

0.3 VDD

V

VOL(4)

XOUT: IO = –1 µA

0.3 VDD

V

Output low-level voltage

VOL(5)

S1 to S28: IO = –20 µA *1

1.0

V

VOL(6)

COM1, COM2, COM3, COM4:

1.0

V

IO = –100 µA *1

VOL(7)

PE: IO = 2 mA

1.0

V

VOL(8)

AOUT, TU: IO = 1 mA, AIN = 1.3 V (AOUT), VDD = 3 V

0.5

V

Output off leakage current

IOFF(1)

Ports PB, PC, PD, PG, PH, PI, PJ, PK, PL, and EO

–3

+3

µA

IOFF(2)

AOUT, TU and port PE

–100

+100

nA

A/D converter error

ADI0, ADI1, ADI3

–1/2

+1/2

LSB

Supply voltage drop detection voltage

VSENSE(1)

Ta = 25°C

*2

1.6

1.75

1.9

V

Supply voltage rise detection voltage

V

(2)

Ta = 25°C

*2

(1)min

(1)max

V

SENSE

+0.1

+0.2

IDD(1)

VDD(1): FIN(2) 130 MHz, Ta = 25°C

5

15

mA

I

(2)

V

DD

(1): In HALT mode, Ta = 25°C *3

0.1

mA

DD

Current drain

IDD(3)

VDD = 3.6 V, with the oscillator stopped,

0.1

mA

Ta = 25°C

*4

IDD(4)

VDD = 1.8 V, with the oscillator stopped,

1

µA

Ta = 25°C *4

Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.

Pin Assignment

	COM4	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11	S12	S13/PH0	S14/PH1	S15/PH2	S16/PH3	S17/PG0	S18/PG1	S19/PG2
	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41
COM3	61						I / O				I / O					I / O			I / O
COM2	62
COM1	63																			I / O
DBR4	64
DBR3	65
DBR2	66
DBR1	67																			I / O
BRES	68
TU	69
HCTR	70
VDD	71																			I
FMIN	72
AMIN	73
VSS	74																		O (OD)
EO	75
AIN	76
AOUT	77																			I / O
AGND	78
TEST1	79				I				O							I
XIN	80												I / O				I / O		I / O
	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
	XOUT	TEST2	PA3	PA2	PA1	PA0	PB3	PB2	PB1	PB0	PC3	PC2	PC1	PC0	PL2	PL1	PL0	PD3	PD2	INT1/PD1

40 S20/PG3

39 S21/PI0

38 S22/PI1

37 S23/PI2

36 S24/PI3

35 S25/PJ0

34 S26/PJ1

33 S27/PJ2

32 S28/PJ3

31 VSS

30 ADI0/ PF0

29 ADI1/PF1

28 ADI3/PF2

27 BEEP/PE0

26 PE1

25 PK0

24 SCK1/PK1

23 SO1/PK2

22 SI1/PK3

21 INT0/PD0

No. 7022-4/14

LC72317, 72318, 72319

Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.

DBR1

0.1 to 1 F

DBR2

C(C1)

0.1 to 1 F						DBR3

C(C2)

0.1 to 1 F DBR4 C(C3)

Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.

*2. VSENSE

When the VDD voltage drops, the VSENSE flag is set when that voltage is 1.75 V (typical). Applications can check the VSENSE flag using the TST instruction. Battery or other power source depletion can be easily measured by monitoring this flag.

Note that the voltage for VSENSE detection differs for the falling and rising directions. Thus, after the VSENSE flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.

VDD

1.9 V

1.6 V

VSENSE (1)	t
For a falling voltage

*3. Halt mode current measurement circuit

	7 pF	A
	75 kHz
	XOUT VDD RESDBR1		0.1 F
	XIN	DBR2
	7pF		0.1 F
		DBR3
		DBR4	0.1 F
	FMIN	VSS
	AMIN	PA, PF, PL
	HCTR	AGND
	TEST1, 2	AIN

VDD

2.1 V

1.7 V

VSENSE (2)	t
For a rising voltage

*4. Backup mode current measurement circuit

	7 pF	A
	75 kHz
	XOUT VDD RESDBR1		0.1 F
	XIN	DBR2
	7pF		0.1 F
		DBR3
	FMIN	DBR4	0.1 F
		VSS
	AMIN
	HCTR	AGND
	TEST1, 2	AIN

With all ports other than those specified above left open. With output mode selected for PC and PD.

With segments S13 to S28 selected.

With all ports other than those specified above left open. With output mode selected for PC and PD.

With segments S13 to S28 selected.

No. 7022-5/14