Sanyo LC72316W Specifications

Ordering number : ENN*6650

N3001TN (OT) No. 6650-1/12

Overview

The LC72314W, LC72315W and LC72316W are
ultralow-voltage (0.9 to 1.8 V) electronic tuning
microcontrollers that include a PLL that operates up to
250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This
IC includes an on-chip DC-DC converter that can easily
create the power supply voltages needed for electronic
tuning and contribute to reducing end product costs. This
IC is optimal for portable audio equipment that must
operate from a single battery.

Function

• Program memory (ROM):

— 4096 × 16 bits (8K bytes) : LC72314W
— 6144 × 16 bits (12K bytes): LC72315W
— 8192 × 16 bits (16K bytes): LC72316W

• Data memory (RAM):

— 256 × 4 bits: LC72314W
— 512 × 4 bits: LC72315W/72316W

• Cycle time: 40 µs (all 1-word instructions)

• Stack: 8 levels

• LCD driver:
48 to 112 segments (1/4 duty, 1/2 bias drive)

• Interrupts: Two external interrupts

Timer interrupts (1, 5, 10, and 50 ms)

• A/D converter: Four input channels
(6-bit successive approximation conversion)

• Input ports: 11 ports (of which three can be switched for
use as A/D converter inputs)

• Output ports: 8 ports (of which 1 can be switched for use
as the beep tone output and 4 are open-drain ports)

• I/O ports: 29 ports (of which 16 can be switched for use
as LCD ports and as mask options, of which 3 can be
switched for use as serial I/O ports)

• Serial I/O: One system (LC72315W/72316W)

• PLL: Reference frequencies:
1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz

• Input frequencies:
FM band: 10 to 250 MHz
AM band (high): 2 to 20 MHz
AM band (low): 0.5 to 10 MHz

• Input sensitivity:FM band:
35 mVrms (130 MHz to 250 MHz: 50 mVrms)
AM band (high, low): 35 mVrms

• IF counter: HCTR input pin 0.4 to 15 MHz (35 mVrms)

• External reset input: During CPU and PLL operations,
instruction execution is started from location 0.

Continued on next page.

Package Dimensions

unit: mm

3220-SQFP80

14.0

12.0

1.25 1.25

0.5

14.0

12.0

1.25

1.25

0.5

120

21

40

41

60

61

80

0.1

0.5

1.6max

1.4

0.5

0.2

0.135

Preliminary

SANYO: SQFP80

[LC72314W, 72315W, 72316W]

LC72314W, 72315W, 72316W

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Ultralow-Voltage ETR Controller

with On-Chip LCD Driver

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

No. 6650-2/12

LC72314W, 72315W, 72316W

Continued from preceding page.

• Built-in power-on reset circuit:
The CPU starts execution from location 0 when power is
first applied.

• Halt mode: The controller-operating clock is stopped.

• Backup mode: The crystal oscillator is stopped.

• Static power-on function:
Backup state is cleared with the PF port

• Beep tone: 1.5 and 3.1 kHz

• Built-in DC-DC converter:
For LCD and A/D converter use (3 V)
Can also be used for TU + B creation by using a
secondary coil.

• Built-in remaining battery life verification function:
Converts the VDDpin level to digital.

• Memory retention voltage: 0.8 V or higher

• Dedicated memory power supply: The RAM retention
time has been increased by the provision of a dedicated
memory power supply.

• Package: SQFP-80 (0.5-mm pitch)

• VDDpower supply: 0.9 to 1.8 V

• Operating frequency: 75 kHz

Pin Assignment

15
16

13
14

11
12

9

10

7
8

5
6

3
4

XOUT

1

TEST2

PA3
PA2
PA1
PA0
PB3
PB2
PB1
PB0
PC3
PC2
PC1
PC0
PL3
PL2

2

17

PL1

18

PL0

19

PD3

20

PD2

777879

VDD

FMIN

VSS

AMIN

EO

TEST1

XIN

80 74

LC72314W
LC72315W
LC72316W

7576

S3

S2

S1

COM4

COM3

COM2

S4

BRES

COM1

707172 676869 646566

73

HCTR

63S562S661

S7

60
59
58
57
56
55
54
53
52
51
50
49
48

S8
S9
S10
S11
S12
S13/PH0
S14/PH1
S15/PH2
S16/PH3
S17/PG0
S18/PG1
S19/PG2
S20/PG3

47

S21/PI0

46

S22/PI1

45

S23/PI2

44

S24/PI3

43

S25/PJ0

42

S26/PJ1

41

S27/PJ2

(Top view)

PF2

ADI1/PF1

ADI0/PF0

SI1/PK3

SO1/PK2

SCK1/PK1

PK0

VSS

VDDRAM

VDC3

VDC1

VADJ

38 3936 3734 3532 3330 3128 29

INT1/PD1

INT0/PD0

PE1

BEEP/PE0

25 26

21

22

PE323PE2

24

ADI3/PF3

27

S28/PJ3

40

No. 6650-3/12

LC72314W, 72315W, 72316W

Parameter Symbol Conditions Ratings Unit

V

DD

1 max V

DD

–0.3 to +3.0 V

Maximum supply voltage V

DD

3 max VDDRAM –0.3 to +4.0 V

V

DD

4 max VDC3 –0.3 to +4.0 V

Input voltage

V

IN

1 FMIN, AMIN, HCTR –0.3 to VDD1 +0.3 V

V

IN

2 PA, PC, PD, PF, PG, PH, PI, PJ, PL, BRES –0.3 to VDD1 +0.3 V

V

OUT

1 PE –0.3 to +7 V

Output voltage

V

OUT

2 PB, PC, PD, PG, PH, PI, PJ, PK, PL –0.3 to VDD1 +0.3 V

V

OUT

3 VDC1, EO –0.3 to VDD4 +0.3 V

V

OUT

4 COM1 to COM4, S1 to S28 –0.3 to VDD4 +0.3 V

I

OUT

1 PC, PD, PG, PH, PI, PJ, PK, PL, EO 0 to 3 mA

I

OUT

2 PB 0 to 1 mA

Output current I

OUT

3 PE 0 to 2 mA

I

OUT

4 S1 to S28 300 µA

I

OUT

5 COM1 to COM4 3 mA
Allowable power dissipation Pdmax Ta = –10 to +60°C 100 mW
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –45 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

DD

1 Voltage applied to the VDDpin 0.9 1.3 1.8

Supply voltage

V

DD

3 Voltage applied to the VDDRAM pin 2.7 3.0 3.3

V

V

DD

4 Voltage applied to the VDC3 pin 2.7 3.0 3.3

V

DD

5 Memory retention voltage 0.8

V

IH

1 Ports PC, PD, PG, PH, PI, PJ, PK, and PL 0.7 VDD1 VDD1 V

Input high-level voltage

V

IH

2 Port PA 0.8 VDD1 VDD1 V

V

IH

3 Port PF 0.8 VDD1 VDD1 V

V

IH

4 Port BRES 0.6 VDD1 VDD1 V

V

IL

1 Ports PC, PD, PG, PH, PI, PJ, PK, and PL 0 0.3 VDD1 V

Input low-level voltage

V

IL

2 Port PA 0 0.2 VDD1 V

V

IL

3 Port PF 0 0.2 VDD1 V

V

IL

4 Port BRES 0 0.2 VDD1 V

V

IN

1 XIN 0.5 0.6 Vrms

Input amplitude V

IN

2 FMIN, AMIN, HCTR: VDD1 = 0.9 to 1.8 V 0.035 0.35 Vrms

V

IN

3 FMIN: VDD1 = 0.9 to 1.8 V 0.05 0.35 Vrms

Input voltage range V

IN

4 ADI0, ADI1, ADI3, VDD1 0 VDD4 V

F

IN

1 XIN: CI ≤ 35 kΩ 70 75 80 kHz

F

IN

2 FMIN: VIN2, VDD1 = 0.9 to 1.8 V 10 130 MHz

Input frequency

F

IN

3 FMIN: VIN3, VDD1 = 0.9 to 1.8 V 130 250 MHz

F

IN

4 AMIN(L): VIN2, VDD1 = 0.9 to 1.8 V 0.5 10 MHz

F

IN

5 AMIN(H): VIN2, VDD1 = 0.9 to 1.8 V 2.0 20 MHz

F

IN

5 HCTR: VIN2, VDD1 = 0.9 to 1.8 V 0.4 15 MHz

Allowable Operating Ranges at Ta = –10 to +60°C, VDD= 0.9 to 1.8 V

No. 6650-4/12

LC72314W, 72315W, 72316W

Parameter Symbol Conditions

Ratings

Unit

min typ max

I

IH

1 XIN: VDD1 = 1.3 V 3 µA

I

IH

2 FMIN, AMIN, HCTR: VDD1 = 1.3 V 3 8 20 µA

Input high-level current I

IH

3 Port PF: VDD1 = 1.3 V 4 µA

PA (without pull-down resistors), the PC,

IIH4 PD, PG, PH, PI, PJ, PK, and PL ports, and 3 µA

BRES: V

DD

1 = 1.3 V

I

IL

1 XIN: VDD1 = V

SS

–3 µA

I

IL

2 FMIN, AMIN, HCTR: VDD1 = V

SS

–3 –8 –20 µA

Input low-level current

I

IL

3 Port PF: VDD1 = V

SS

–4 µA

I

IL

4

PA (without pull-down resistors), the PC,
PD, PG, PH, PI, PJ, PK, and PL ports, and –3 µA
BRES: V

DD

1 = V

SS

Input floating voltage V

IF

PA (with pull-down resistors)

0.05 VDD1

V

R

PD

1 PA/PF (with pull-down resistors), VDD1 = 1.3 V 75 100 200 kΩ

Pull-down resistor

R

PD

2

TEST1, TEST2 (with pull-down resistors),

10 kΩ

V

DD

1 = 1.3 V

Hysteresis V

H

BRES 0.1 VDD1 0.2 VDD1 V

V

OH

1 PB: IO= 1 mA

V

DD

1 – V

0.3 V

DD

1

V

OH

2

PC, PD, PG, PH, PI, PJ, PK, and PL: V

DD

1 –

V

I

O

= 1 mA 0.3 VDD1

V

OH

3 EO: IO= 500 µA

V

DD

4 –

V

Output high-level voltage 0.3 V

DD

4

V

OH

4 XOUT: IO= 1 µA

V

DD

1 –

V

0.3 V

DD

1

V

OH

5 S1 to S28: IO= 20 µA VDD4 –1 V

V

OH

6

COM1, COM2, COM3, COM4:

VDD4 –1 V

I

O

= 100 µA

V

OH

7 VDC1: IO= 1 mA VDD4 –1 V

V

OL

1 PB: IO= –50 µA 0.3 VDD1 V

V

OL

2

PC, PD, PE, PG, PH, PI, PJ, PK,

0.3 VDD1 V

and PL: I

O

= –1 mA

V

OL

3 EO: IO= –500 µA 0.3 VDD4 V

Output low-level voltage

V

OL

4 XOUT: IO= –1 µA 0.3 VDD1 V

V

OL

5 S1 to S28: IO= –20 µA VDD4 –2 V

V

OL

6

COM1, COM2, COM3, COM4:

VDD4 –2 V

I

O

= –100 µA

V

OL

7 PE: IO= 2 mA 0.6 VDD1 V

I

OFF

1

Ports PB, PC, PD, PG, PH, PI, PJ, PK, PL,

–3 +3 µA

Output off leakage current

and EO

I

OFF

2 Port PE –100 +100 nA

A/D converter error ADI0, ADI1, ADI3 V

DD

1 –1/2 +1/2 LSB

I

DD

1 VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25°C 10 30 mA

I

DD

2 VDD1 = 1.3 V: In PLL stop mode, Ta = 25°C 0.15 mA

Current drain I

DD

3 VDD1 = 1.3 V: In HALT mode, Ta = 25°C *

1

0.1 mA

I

DD

4

V

DD

1 = 1.8 V, with the oscillator stopped,

1 µA

Ta = 25°C *

2

Electrical Characteristics under allowable operating conditions

Note*: The halt mode current drain is due to 20 instruction being executed every 125 ms.

No. 6650-5/12

LC72314W, 72315W, 72316W

A

7 pF

FMIN

XIN

AMIN

TEST1, 2

XOUT VDD

VDC3

RES

VSS

PA, PF, PK, PL1-3

7 pF

75 kHz

HCTR

VADJ

3 V

A

7 pF

FMIN

XIN

AMIN

TEST1, 2

XOUT VDD

VDC3

RES

VSS

7 pF

75 kHz

VADJ

3 V

HCTR

VADJ

VDC3

VDDRAM

VDC1

VSS

VDD

*1. Halt and PLL STOP mode current test circuit *2. Backup mode current test circuit

With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S28 selected.

With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S28 selected.

DC-DC Converter Application

Block Diagram

No. 6650-6/12

LC72314W, 72315W, 72316W

PHASE

DETECTOR

REFERENCE DIVIDER

DIVIDER

SYSTEM CLOCK

GENERATOR

PROGRAMMBLE DIVIDER

1/16,1/17

SEG

LA

P-ON

RESET

1/2

BANK

ADDRESS
DECODER

DATA BUS

TIMER 0

JUDGE

ALU

CF

SKIP

BANK

A

STACK

4

14

14

ADDRESS COUNTER

ADDRESS DECODER

ROM

4k×16bits
(LC72314)
6K×16bits
(LC72315)

8K×16bits
(LC72316)

BUS

CONTROL

JMP
CAL
RETURN
INTERRUPT
RESET

INSTRUCTION

DECODER

PLL DATA LATCH

PLL CONTROL

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

BUS

DRIVER

XIN

XOUT

FMIN

PC2

PC1

PC0

PC3

PA3

PA2

PA1

PA0

TEST2

TEST1

RES

*

AMIN

S16/PH3

S15/PH2

S13/PH0
S14/PH1

LCD

PORT

DRIVER

LCPA/B

LCDA/B

EO

S12

S1

VSS

PB2

PB1

PB0

PB3

PD2

INT1/PD1

INT0/PD0

PD3

LATCH

LATCH

B

PE0/BEEP

COM1

COM2

COM3

COM4

S20/PG3

S19/PG2

S17/PG0
S18/PG1

DATA

LATCH

/

BUS

DRIVER

MPX

(6bits)

MPX

MPX

BEEP TONE

COMMON

DRIVER

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

DATA

LATCH

/

BUS

DRIVER

7

PF3/ADI3

PF1/ADI1

PF0/ADI0

PE1

VDC3

VADJ

VDD

VDC1

PL2

PL1

PL0

PL3

SIO

VDDRAM

SO1/PK2

SCK1/PK1

PK0

SI1/PK3

S24/PI3

S23/PI2

S21/PI0
S22/PI1

DATA

LATCH

/

BUS

DRIVER

S28/PJ3

S27/PJ2

S25/PJ0
S26/PJ1

DATA

LATCH

/

BUS

DRIVER

PE2

PE3

PF2

HCTR

TIME BASE

COUNTROL

COUNT END

UNIVERSAL

COUNTER(20bits)

112

1/2

1/2

1/2

RAM
256×4bits
(LC72314)
512×4bits

(LC72315/316)

1/8

Clock control

*

DATA

1/2

DATA

No. 6650-7/12

LC72314W, 72315W, 72316W

Pin Functions

Pin No. Pin I/O Function I/O circuit

75 kHz oscillator connections

80

1

XIN

XOUT

I

O

IC testing.
These pins must be connected to ground during normal operation.

—

79

2

TEST1
TEST2

I
I

Special-purpose ports for key return signal input designed with a low threshold
voltage. When a key matrix is formed in combination with port PB, simultaneous
multiple key presses with up to 3 keys can be detected. The pull-down resistors are
set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This
setting cannot be specified for individual pins. In backup mode, these pins go to the
input disabled state, and the pull-down resistors are disabled after a reset.

6
5
4
3

PA0
PA1
PA2
PA3

I

Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction.
Since these outputs are unbalanced, no diodes are required to prevent short circuits
due to simultaneous multiple key presses. These outputs go to the high-impedance
output state in backup mode. After a reset, they go to the high-impedance output
state and remain in that state until an output instruction (OUT, SPB, or RPB) is
executed.

10

9
8
7

PB0
PB1
PB2
PB3

O

General-purpose I/O ports.
PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5)

is used for switching the general-purpose I/O port function, and these ports can be set
to input or output in 1-bit units. (0: input, 1: output)

In backup mode they go to the input disabled high-impedance state.
After a reset, they switch to the general-purpose input port function.

14
13
12
11
22
21
20
19

PC0
PC1
PC2

PC3
INT0/PD0
INT1/PD1

PD2

PD3

*

2

I/O

O

General-purpose output and beep tone output shared function ports (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output
port. The b0 and b1 bits are used to select the beep tone frequency. There are two
beep tone frequencies supported.

*: When PE0 is set up as the beep tone output, executing an output instruction to PE0

only changes the state of the internal output latch, it does not affect the beep tone
output in any way. Only the PE0 pin can be switched between the general-purpose
output function and the beep tone output function; the PE1 to PE3 pin only
functions as a general-purpose output. These pins go to the high-impedance state
in backup mode and remain in that state until an output instruction or a BEEP
instruction is executed. Since these ports are open-drain ports, resistors must be
inserted between these pins and V

DD

. These ports are set to general-purpose

output port function after a reset.

26
25
24
23

BEEP/PE0

PE1

PE2

PE3

I/O

I
I

I
I/O
I/O
I/O
I/O

Shared function pins used as either general-purpose I/O ports or a serial I/O port (only
port PK). When used as general-purpose I/O ports, the I/O direction can be switched
in single bit units with the IOS instruction (Pwn = 1, C). The IOS instruction (with Pwn
= 1, b2) is used to switch the function between the general-purpose I/O port and the
serial I/O port function. (0: general-purpose I/O port, 1: serial I/O)

In backup mode (low power mode) these pins go to the input disabled high­impedance state. After a reset, the general-purpose input port function is selected.

Pins PL1, PL2, and PL3 are used as input ports.

18
17
16
15
34
33
32
31

PL0
PL1
PL2
PL3
PK0

SCK1/PK1

SO1/PK2

SI1/PK3

Input with built-in

pull-down resistor

N-channel open-drain

CMOS input

CMOS push-pull

CMOS push-pull

Continued on next page.

Unbalanced CMOS push-pull

No. 6650-8/12

LC72314W, 72315W, 72316W

Continued from preceding page.

Pin No. Pin I/O Function I/O circuit

General-purpose input and A/D converter input shared function ports. The IOS
instruction (Pwn = FH) is used to switch between the general-purpose input and A/D
converter port functions. The general-purpose input and A/D converter port functions
can be switched in a units, with 0 specifying general-purpose input, and 1 specifying
the A/D converter input function. To select the A/D converter function, set up the A/D
converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started
with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion
completes. The INR instruction is used to read in the data.

*: If an input instruction is executed for one of these pins which is set up for analog

input, the read in data will be at the low level since CMOS input is disabled. In
backup mode these pins go to the input disabled high-impedance state. These
ports are set to their general-purpose input port function after a reset. The A/D
converter is a 6-bit successive approximation type converter, and features a
conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (3FH) is
(63/96) V

DD

.

30
29
28
27

PF0/ADI0
PF1/ADI1

PF2

PF3/ADI3

I

CMOS input/analog input

LCD driver segment output and general-purpose I/O shared function ports.
The IOS instruction is used for switching between the segment output and general-

purpose I/O functions and between input and output for the general-purpose I/O port
function.

• When used as segment output ports
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8).

b0 to b3 = S17 to 20/PG0 to 3
(0: segment output 1: general-purpose I/O)

The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9).

b0 to b3 = S13 to 16/PH0 to 3

(0: segment output 1: general-purpose I/O)
The general-purpose I/O port function is selected with the IOS instruction
(Rwn = D)

b0 to b3 = S21 to 24/PI0 to 3

(0: segment output 1: general-purpose I/O)
The general-purpose I/O port function is selected with the IOS instruction
(Rwn = E)

b0 to b3 = S25 to 28/PJ0 to 3

(0: segment output 1: general-purpose I/O)

• When used as general-purpose I/O ports
The IOS instruction (Pwn = 6, 7, A, B) is used to select input or output. Note that
the mode can be set in a bit units.

b0 = PG0 b0 = PH0 b0 = PI0 b0 = PJ0
b1 = PG1 b1 = PH0 b1 = PI1 b1 = PJ1 0: Input
b2 = PG2 b2 = PH0 b2 = PI2 b2 = PJ2 1: Output
b3 = PG3 b3 = PH0 b3 = PI3 b3 = PJ3

In backup mode, these pins go to the input disabled high-impedance state if set up as
general-purpose outputs, and are fixed at the low level if set up as segment outputs.
These ports are set up as segment outputs after a reset.

Although the general-purpose port/LCD port setting is a mask option, the IOS
instruction must be used as described above to set up the port function.

40
41
42
43

44
45
46
47

48
49
50
51

52
53
54
55

PJ3/S28
PJ2/S27
PJ1/S26
PJ0/S25

PI3/S24
PI2/S23
PI1/S22
PI0/S21

PG3/S20
PG2/S19
PG1/S18
PG0/S17

PH3/S16
PH2/S15
PH1/S14
PH0/S13

*2

I/O

CMOS push-pull

LCD driver segment output pins.
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
In backup mode, these outputs are fixed at the low level.
After a reset, these outputs are fixed at the low level.

56 to

67

S12 to S1 O

LCD driver common output pins.
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
In backup mode, these outputs are fixed at the low level.
After a reset, these outputs are fixed at the low level.

68
69
70
71

COM4
COM3
COM2
COM1

O

CMOS push-pull

Continued on next page.

No. 6650-9/12

LC72314W, 72315W, 72316W

Continued from preceding page.

Pin No. Pin I/O Function I/O circuit

System reset input.
In CPU operating mode or halt mode, applications must apply a low level for at least

one full machine cycle to reset the system and restart execution with the PC set to
location 0. This pin is connected in parallel with the internal power on reset circuit.

72 RES I

Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency
in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception
mode.

38 VDC1 O

Voltage stepped up by the DC-DC converter (3 V)
May also be used to input an equivalent voltage.

37 VDC3 I

RAM backup power supply. Connected to the VDC3 voltage through a diode.36 VDDRAM I

VDC3 voltage adjustment pin. Insert a 10 kΩ variable resistor between this pin and
ground to adjust the VDC3 voltage.

39 VADJ O

FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

75 FMIN I

CMOS amplifier input

AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.

The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

76 AMIN I

CMOS amplifier input

Dedicated input port for the universal counter.

• For frequency measurement, select the HCTR frequency measurement mode and
measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the counter with
a UCC instruction.

When the count operation completes, the CNTEND flag will be set. Since it operates
as an AC amplifier in this mode, the input must be provided through a coupling
capacitor.

Input is disabled in backup mode, HALT mode, after a reset, and in PLL STOP mode.

73 HCTR I

CMOS amplifier input

Main charge pump output. When the local oscillator frequency divided by N is higher
than the reference frequency a high level is output, when lower, a low level is output,
and the pin is set to the high-impedance state when the frequencies match.

This output goes to the high-impedance state in backup mode, in halt mode, after a
reset, and in PLL stop mode.

78 EO O

Power supply pin. This pin must be connected to ground.

This pin must be connected to ground.
This pin must be connected to V

DD

. Supports A/D converter.

—

77
35
74

V

SS

V

SS

V

DD

—

CMOS push-pull

CW1 b1, b0 Input pins Bandwidth

1 0 AMIN (H) 2 to 20 MHz (SW)
1 1 FMIN (L) 0.5 to 10 MHz (MW, LW)

UCS b3, b2 Input pin measurement mode

0 0 HCTR frequency measurement
0 1 —
1 1 —

UCS b1, b0

Measurement time
0 0 1 ms
0 1 4 ms
1 0 8 ms
1 1 32 ms

Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up

output mode with an IOS instruction.

LC72314 Series Instruction Set

Terminology

ADDR : Program memory address
b : Borrow
C : Carry
DH : Data memory address High (Row address) [2 bits]
DL : Data memory address Low (Column address) [4 bits]
I : Immediate data [4 bits]
M : Data memory address
N : Bit position [4 bits]
Rn : Resister number [4 bits]
Pn : Port number [4 bits]
PW : Port control word number [4 bits]
r : General register (One of the addresses from 00H to 0FH of BANK0)
( ), [ ] : Contents of register or memory
M (DH, DL) : Data memory specified by DH, DL

No. 6650-10/12

LC72314W, 72315W, 72316W

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

AD r M Add M to r R ← (r) + (M)

ADS r M Add M to r, then skip if carry R ← (r) + (M), skip if carry

AC r M Add M to r with carry R ← (r) + (M) + C

ACS r M

Add M to r with carry, R ← (r) + (M) + C
then skip if carry skip if carry

AI M I Add I to M M ← (M) + I
AIS M I Add I to M, then skip if carry M ← (M) + I, skip if carry
AIC M I Add I to M with carry M ← (M) + I + C

AICS M I

Add I to M with carry, M ← (M) + I + C,
then skip if carry skip if carry

SU r M Subtract M from r R ← (r) – (M)

SUS r M

Subtract M from r, R ← (r) – (M),
then skip if borrow skip if borrow

SB r M Subtract M from r with borrow R ← (r) – (M) – b

SBS r M

Subtract M from r with borrow, R ← (r) – (M) – b,
then skip if borrow skip if borrow

SI M I Subtract I from M M ← (M) – I
SIS M I

Subtract I from M, M ← (M) – I,
then skip if borrow skip if borrow

SIB M I Subtract I from M with borrow M ←(M) – I – b

SIBS M I

Subtract I from M with borrow, M ← (M) – I – b,
then skip if borrow skip if borrow

SEQ r M Skip if r equal to M (r) – (M), skip if zero
SEQI M I Skip if M equal to I (M) – I, skip if zero
SNEI M I Skip if M not equal to I (M) – I, skip if not zero

SGE r M

Skip if r is greater than or (r) – (M),
equal to M skip if not borrow

SGEI M I

Skip if M is greater than

(M) – I, skip if not borrow

equal to I

SLEI M I Skip if M is less than I (M) – I, skip if borrow

f e d c b a 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 DH DL r
0 1 0 0 0 1 DH DL r
0 1 0 0 1 0 DH DL r

0 1 0 0 1 1 DH DL r
0 1 0 1 0 0 DH DL I

0 1 0 1 0 1 DH DL I
0 1 0 1 1 0 DH DL I

0 1 0 1 1 1 DH DL I
0 1 1 0 0 0 DH DL r

0 1 1 0 0 1 DH DL r
0 1 1 0 1 0 DH DL r

0 1 1 0 1 1 DH DL r
0 1 1 1 0 0 DH DL I

0 1 1 1 0 1 DH DL I
0 1 1 1 1 0 DH DL I
0 1 1 1 1 1 DH DL I
0 0 0 1 0 0 DH DL r

0 0 0 1 1 0 DH DL I
0 0 0 0 0 1 DH DL I

0 0 0 1 1 0 DH DL r

0 0 0 1 1 1 DH DL I
0 0 0 0 1 1 DH DL I

Instruction

group

Continued on next page.

Addition instructionsSubtraction instructions

Comparison instructions

No. 6650-11/12

LC72314W, 72315W, 72316W

Continued from preceding page.

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

AND r M AND M with r R ← (r) AND (M)
ANDI M I AND I with M M ← (M) AND I

OR r M OR M with r R ← (r) OR (M)

ORI M I OR I with M M ← (M) OR I
EXL r M Exclusive OR M with r R ← (r) XOR (M)
EXLI M I Exclusive OR M with M M ← (M) XOR I

SHR r Shift r right with carry

LD r M Load M to r R ← (M)
ST M r Store r to M M ← (r)

MVRD r M

Move M to destination M

[DH, Rn] ← (M)

referring to r in the same row

MVRS M r

Move source M referring to r

M ← [DH, Rn]

to M in the same row

MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2]

MVI M I Move I to M M ← I
TMT M N

Test M bits, then skip if all bits

if M (N) = all 1, then skip

specified are true

TMF M N

Test M bits, then skip if all bits

if M (N) = all 0, then skip

specified are false

JMP ADDR Jump to the address PC ← ADDR
CAL ADDR Call subroutine

PC ← ADDR
Stack ← (PC) + 1

RT Return from subroutine PC ← Stack

PC ← Stack,

RTI Return from interrupt BANK ← Stack,

CARRY ← Stack
SS SWR N Set status register (Status W-reg) N ← 1
RS SWR N Reset status register (Status W-reg) N ← 0

TST SRR N Test status register true If (Status R-reg) N = all
TSF SRR N Test status register false If (Status R-reg) N = all

TUL N Test Unlock F/F

If Unlock F/F (N) = All 0s,

then skip

PLL M Load M to PLL register PLL reg ← PLL data

SIO I1 I2 Serial I/O control SIO reg ←I1, I2
UCS I Set I to UCCW1 UCCW1 ← I
UCC I Set I to UCCW2 UCCW2 ← I

BEEP I Beep control BEEP reg ← I

DZC I Dead zone control DZC reg ← I
TMS I Set timer register Timer reg ← I

IOS PWn N Set port control word IOS reg PWn ← N

IN M Pn Input register port data to M M ← (Pn)

OUT M Pn Output contents of M to port Pn ← M

INR M Rn Input port data to M M ← (Pn reg)

OUTR M Rn

Output contents of M to

Rn reg ← (M)

register/port
SPB Pn N Set port bits (Pn)N ←1
RPB Pn N Reset port bits (Pn)N ← 0

TPT Pn N

Test port1 bits, then skip if all bits

If (Pn)N = all 1, then skip

specified are true
TPF Pn N

Test port1 bits, then skip if all bits

If (Pn)N = all 0, then skip

specified are false

BANK I Select Bank BANK ← I

f e d c b a 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 0 DH DL r
0 0 1 0 0 1 DH DL I
0 0 1 0 1 0 DH DL r
0 0 1 0 1 1 DH DL I
0 0 1 1 0 0 DH DL r
0 0 1 1 1 0 DH DL I

0 0 0 0 0 0 0 0 1 1 1 0 r
1 1 0 1 0 0 DH DL r

1 1 0 1 0 1 DH DL r
1 1 0 1 1 0 DH DL r

1 1 0 1 1 1 DH DL r
1 1 1 0 0 0 DH DL1 DL2

1 1 1 0 0 1 DH DL I
1 1 1 1 0 0 DH DL N

1 1 1 1 0 1 DH DL N
1 0 0 ADDR (13 bits)

1 0 1 ADDR (13 bits)
0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 1 0 0 1

1 1 1 1 1 1 1 1 0 0 0

SWR

N

1 1 1 1 1 1 1 1 0 0 1

SWR

N
1 1 1 1 1 1 1 1 0 1 SRR N
1 1 1 1 1 1 1 1 1 0 SRR N

0 0 0 0 0 0 0 0 1 1 0 1 N
1 1 1 1 1 0 DH DL r

0 0 0 0 0 0 0 1 I1 I2
0 0 0 0 0 0 0 0 0 0 0 1 I
0 0 0 0 0 0 0 0 0 0 1 0 I
0 0 0 0 0 0 0 0 0 1 1 0 I
0 0 0 0 0 0 0 0 1 0 1 1 I
0 0 0 0 0 0 0 0 1 1 0 0 I
1 1 1 1 1 1 1 0 PWn N
1 1 1 0 1 0 DH DL Pn
1 1 1 0 1 1 DH DL Pn
0 0 1 1 1 0 DH DL Pn

0 0 1 1 1 1 DH DL Rn
0 0 0 0 0 0 1 0 Pn N

0 0 0 0 0 0 1 1 Pn N
1 1 1 1 1 1 0 0 Pn N

1 1 1 1 1 1 0 1 Pn N

0 0 0 0 0 0 0 0 0 1 1 1 I

Bit test

instructions

Jump and subroutine

call instructions

carry

(r)

Logic operation instructionsTransfer instructions

Continued on next page.

Instruction

group

Bank switching

instructions

Status register

instructions

I/O instructions Hardware control instructions

PS No. 6650-12/12

LC72314W, 72315W, 72316W

This catalog provides information as of November, 2001. Specifications and information herein are
subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

LCDA M I

Output segment pattern to LCD

LCD (DIGIT) ← M

LCDB M I

digit direct

LCPA M I

Output segment pattern to LCD

LCD (DIGIT) ← LA ← M

LCPB M I

digit through LA

HALT I Halt mode control

HALT reg ← I,
then CPU clock stop

CKSTP Clock stop Stop x’tal OSC

NOP No operation No operation

Continued from preceding page.

f e d c b a 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 DH DL DIGIT
1 1 0 0 0 1 DH DL DIGIT
1 1 0 0 1 0 DH DL DIGIT
1 1 0 0 1 1 DH DL DIGIT

0 0 0 0 0 0 0 0 0 1 0 0 I
0 0 0 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0

LCD

instructions

Other

instructions

Instruction

group