Sanyo LC72313W Specifications
Ordering number : ENN∗7143
CMOS IC
LC72311W, 72312W, 72313W
Low-Voltage ETR-Controller
Preliminary
Overview
The LC72311W, LC72312W, and LC72313W are
low-voltage single-chip FM/AM electronic tuning
microcontrollers that include a built-in PLL circuit for
frequencies up to 230 MHz, a 1/4 duty 1/2 bias LCD
controller, and a small EEPROM. These microcontroller
also provide a low-power standby mode that reduces power
consumption by switching the system clock frequency.
Furthermore, since these devices include a low-pass filter
amplifier required for the electronic tuning system and a
tuning voltage generator circuit, they can contribute to
reduced end product costs through lower parts counts.
These ICs are optimal for use in low-voltage portable audio
equipment that includes a radio receiver.
Functions
•
Program memory (ROM):
8192 × 16 bits (16 KB) LC72311W
16,384 × 16 bits (32 KB) LC72312W
24,576 × 16 bits (48 KB) LC72313W
•
Data memory (RAM):
512 × 4 bits (RAM)
512 × 4 bits (EEPROM)
•
Cycle time:
0.71 µs (at 4.2336 MHz) (All 1-word instructions)
40 µs (at 75 kHz) (All 1-word instructions)
•
Stack: 8 levels
•
LCD driver:
48 to 96 segments (1/4 duty 1/2 bias drive)
•
Interrupts:
Two external interrupt systems
Internal timer interrupts: two systems (1, 5, 10, and 50 ms)
Serial I/O interrupt (SIO0 only)
■ Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control
systems, or other applications whose failure can be reasonably expected to result in serious physical and/or
material damage. Consult with your SANYO representative nearest you before using any SANYO products
described or contained herein in such applications.
■ SANYO assumes no responsibility for equipment failures that result from using products at values that exceed,
even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters)
listed in products specifications of any and all SANYO products described or contained herein.
•
A/D converter:
Four-input 8-bit converter
•
Input ports:
9 or 10 ports (Ports PA, PF, and HCTR)
The PF port is shared with the A/D converter, and HCTR
is shared with the IF counter.
•
Output ports:
8 ports (Ports PB and PE)
PE3 is shared with the BEEP pin, PE0 to PE2 are
open-drain ports, and the PB port can be switched to
function as an open-drain port.
Continued on next page.
Package Dimensions
unit: mm
3220-SQFP80
[LC72311W, 72312W , 72313W]
14.0
12.0
1.25 1.25
0.5
0.2
0.5
14.0
60
61
1.25
0.5
12.0
1.25
80
120
0.135
41
40
21
1.4
1.6max
0.1
0.5
SANYO: SQFP80
N3001RM(OT)No.7143-1/9
LC72311W, 72312W, 72313W
Continued from preceding page.
•
I/O ports:
22 ports (Ports PC, PD, PL, PI, PG, and PH)
Port PD is shared with the interrupt function, ports PC and
PK are shared with th e ser ial I /O funct ion, and p ort s PI, P G,
and PH are shared with the LCD segment driver function.
•
PLL:
Provides dead band control (4 settings)
Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25
kHz
•
Input frequencies:
FM band: 10 to 230 MHz
AM band: 0.5 to 10 MHz
•
Input sensitivity:
FM band: 35 mVrms (130 MHz to 50 mVrms)
AM band: 35 mVrms
•
HCTR:
IF counter (0.4 to 15 MHz)
•
External reset pin:
Starts the PC from address 0 during CPU and PLL
operation.
•
Built-in power-on reset circuit:
Starts the PC from address 0 at power on.
•
Halt mode:
Temporarily slows the microcontroller operating clock
and reduces power consumption.
•
Backup mode:
Stops the crystal oscillator circuit.
•
Static power on:
Backup mode can be cleared with the PF port.
•
BEEP:
Seven alarm tones: 0.75, 1.25, 1.5, 2.08, 2.5, 3.125, and
6.25 kHz.
•
Serial I/O:
Two channels (These functions use the PC and PK port
pins.)
The internal serial transfer clock provides three
frequencies: 12.5, 25, and 75 kHz.
•
On-chip low-pass filter amplifier:
Reduces end product parts counts and costs.
•
Tuning voltage generator circuit:
Obviates the need for an external tuning power supply
circuit for reduced end product parts counts and costs.
•
Memory retention voltage:
Over 0.9 V.
•
VDD voltage:
PLL circuit: 1.8 to 3.6 V
CPU and A/D converter:
1.6 to 3.6 V (For a 40 µs instruction cycle)
2.4 to 3.6 V (For a 0.71 µs instruction cycle)
•
Option selections:
PH0 to PH3/S13 to S16
PG0 to PG3/S17 to S20
PI0 to PI3/S21 to S24
Vsense circuit present/absent
•
Package:
SQFP80 (0.5 mm lead pitch)
No.7143-2/9
Tuning Voltage Generator Circuit
LC72311W, 72312W, 72313W
XIN
80
XOUT
1
1/256
1/2
FM
AM
PLL instruction
100 µH
72
VDD
71
AMIN
73
TU
67
14 V
VDDP
68
No.7143-3/9
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