Sanyo LC7219M Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

PLL Frequency Synthesizers

Ordering number:ENN3661B

LC7219, 7219M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC7219 and LC7219M are high-performance, phase­locked loop (PLL) frequency synthesizer ICs that operate
over the AM and FM radio w a v ebands. The y feature excel­lent frequency tracking, making them ideal as reference
frequency sources for use in AM/FM tuners, television and
audio-video equipment, and high-quality car-stereo appli­cations.
The LC7219 and LC7219M operate from a 5 V supply and
are available in 24-pin DIPs and 24-pin MFPs, respectiv ely.

Features

• Programmable divider.

• General-purpose universal counter.
(The IF signal count must be used together with the SD

(station detect) signal from IF-IC).

• Unlock detector.

• 8 Hz real-time clock output.

• Ten selectable reference frequencies.

• 400 kHz microcontroller system-clock output.

• Swallow counter.

• Shift register.

• 5 V supply.

• 24-pin DIP and 24-pin MFP.

Package Dimensions

unit:mm

3067A-DIP24S

[LC7219]

21.0

24

1

0.9

(0.71)

1.78

unit:mm

3045B-MFP24

24

0.48

0.95

[LC7219M]

13

6.4

7.62

0.25

12

(3.25)

3.9max

3.3

0.51min

SANYO : DIP24S

13

1

15.3

0.35

71901TN (KT)/D2593JN/1142JN No.3661–1/12

12

1.27

7.9

2.15

0.1

0.67

SANYO : MFP24

0.15

2.5max

9.0

0.75

10.5

LC7219, 7219M

Block Diagram

XOUT

FMIN

AMIN

XIN

CE

CL

DO

SYC

6

1

24

19

18

2

DI

3

4

5

REFERENCE

DIVIDER

1

SWALLOW COUNTER

2

91011121314

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 IN0 IN1

OUT0

1/16, 1/17 4BIT

12BIT PRORAMABLE

SHIFT REGISTER

LATCH

PHASE DETECTOR

CHARGE PUMP

DIVIDER

UNIVERSAL

COUNTER

17 7 8

21

22

16

15

20

23

PD1

PD2

HCTR

LCTR

V

DD

V

SS

Pin Assignment

Pin Description

rebmuNemaNnoitpircseD
1NIXtupnirotallicsolatsyrczHM2.7
2ECtupnielbane-pihC
3IDrellortnocorcimmorftupniataD
4LCtupnikcolC
5ODrellortnocorcimottuputoataD
6CYStuptuokcolc-metsys,elcycytud%66,zHk004

8,71NI,0NIstupniatadretsigertfihS

71,41ot96TUOot0TUOstuptuoatadretsigertfihS
51RTCL tupniretnuocesoprup-larenegtnemerusaemycneuqerfrodoireP
61RTCHtupniretnuocesoprup-larenegtnemerusaemycneuqerF
81NIMAtupnilangisOCVdnabMA
91NIMFtupnilangisOCVdnabMF
02VDDegatlovylppuS

22,122DP,1DPstuptuopmupegrahcrotceted-esahP
32VSSdnuorG
42TUOXtuptuorotallicsolatsyrczHM2.7

Top view

No.3661–2/12

LC7219, 7219M

Specifications

Absolute Maximum Ratings at Ta = 25˚C, VSS = 0V

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppusmumixaMV

egatlovtupni1NIdna0NI,ID,LC,ECV

sniprehtollarofegatlovtupnIV

egatlovtuptuoCYSdnaODV

egatlovtuptuo2TUOdna1TUOV

egatlovtuptuo6TUOot3TUOdna0TUOV

sniprehtollarofegatlovtuptuOV

noitapissidrewopelbawollAxamdP

erutarepmetgnitarepOrpoT –58+ot04

erutarepmetegarotSgtsT –521+ot55

Reommended Operating Conditions at Ta = 25˚C, VSS = 0V

retemaraPlobmySsnoitidnoC

egnaregatlovylppuSV

noitarepo

egatlovtuptuilevel-hgihRTCLV

egatlovtuptuilevel-wolRTCLV

egatlovtuptuoCYSdnaODV

ycneuqerftupniNIXf

1*ycneuqerftupniNIMFf

ycneuqerftupniNIMAf

2*ycneuqerftupniRTCHf

ycneuqerftupniRTCLf

ycneuqerfrotallicsolatsyrCf

edutilpmatupnismrNIXV

1*edutilpmatupnismrNIMFV

edutilpmatupnismrNIMAV

2*edutilpmatupnismrRTCHV

edutilpmatupnismrRTCLV

rotallicsolatsyrcrofegnaregatlovylppuS

egatlovtupnilevel-hgih1NIdna0NI,ID,LC,ECV

egatlovtupnilevel-wol1NIdna0NI,ID,EC,LCV

egatlovtuptuo6TUOot3TUOdna0TUOV

Notes

1. f

=10 to 160MHz for V

IN2

2. f

=10 to 70MHz for V

IN4

=0.1V(min)

IN2

=0.1V(min)

IN4

xamDD
1NI
2NI

1TUO
2TUO
3TUO
4TUO

V

1DD

DD

V

V

2DD

DD

1HI
2HI
1LI

2LI

1TUO
2TUO

1NI

2NI

3NI

4NI

5NI

V
XNI–X

LATX

1NI

2NI
3NI
4NI

5NI

5elbateeS

5elbateeS

V,gnilpuoc

DD

V,gnilpuoc

DD

DD

V5.6ot5.4=

TUO

V,gnilpuoc

DD

–

–

–

nimpytxam

5.4

5.35.6V

2.2

V,tnemerusaemdoireP

DD

V,tnemerusaemdoireP

DD

V5.6ot5.4=

V5.6ot5.4=

V,tnemerusaemycneuqerF

V5.6ot5.4=

V5.6ot5.4=V7.0

V5.6ot5.4=0

V,gnilpuoceviticapac,evaweniS

DD

V,gnilpuoceviticapac,evaweniS

DD

V,gnilpuoceviticapac,evaweniS

DD

ecnadepmilatsyrC: ≤ 05 Ω 0.32.70.8zHM

V,gnilpuoceviticapac,evaweniS

DD

V,gnilpuoceviticapac,evaweniS

DD

V,gnilpuoceviticapac,evaweniS

DD

DD

V5.6ot5.3=0.12.70.8zHM
V5.6ot5.4=

V5.6ot5.4=

eviticapac,evawenis,tnemerusaemdoirP

eviticapac,evawenis,tnemerusaemycneuqerF

,gnilpuocCDevaweslup,tnemerusaemdoirP

V5.6ot5.4=5.05.1smrV
V5.6ot5.4=70.05.1smrV
V5.6ot5.4=70.05.1smrV

V5.6ot5.4=70.05.1smrV

eviticapac,evawenis,tnemerusaemycneuqerF

DD

0

01031zHM

5.00.04zHM

0106zHM

51005

100.00.02

70.05.1smrV

–0.7+ot3.0V
–0.7+ot3.0V

Vot3.0

3.0+

3.0+

3.0+

)9127CL(053
)M9127CL(053

5.6V

5.6V

V

DD

7.0

V3.0

DD

5.6V
31V

V

V

V

Wm

˚C
˚C

tinU

V
V
V

zHK

DD

–0.7+ot3.0V

Vot3.0

DD

–0.51+ot3.0V

Vot3.0

DD

sgnitaR

No.3661–3/12

LC7219, 7219M

Electrical Characteristics at Ta = –40 to +85˚C, VSS = 0V

retemaraPlobmySsnoitidnoC

ecnatsiserlanretniNIXR

ecnatsiserlanretniNIMFR

ecnatsiserlanretniNIMAR

ecnatsiserlanretniRTCHR

ecnatsiserlanretniRTCLR

htdiwsiseretsyhRTCLV

tnerructupnilevel-hgihIDdnaLC,ECI

tnerructupnilevel-hgih1NIdna0NII

tnerructupnilevel-hgihNIXI

tnerructupnilevel-hgihNIMFdnaNIMAI

tnerructupnilevel-hgihRTCLdnaRTCHI

tnerructupnilevel-wolIDdnaLC,ECI

tnerructupnilevel-wol1NIdna0NII

tnerructupnilevel-wolNIXI

tnerructupnilevel-wolNIMAdnaNIMFI

tnerructupnilevel-wolRTCLdnaRTCHI
egatlovtuptuolevel-hgih2TUOot1TUOV

egatlovtuptuolevel-hgih2DPot1DPV

egatlovtuptuolevel-wol2TUOot1TUOV

egatlovtuptuolevel-wol2DPot1DPV

egatlovtuptuolevel-wol6TUOot3TUOV

egatlovtuptuolevel-wol0TUOV

egatlovtuptuolevel-wolODV

egatlovtuptuolevel-wolCYSV

egakaelffotuptuo6TUOot3TUOdna0TUO

tnerruc

tnerrucegakaelffotuptuoODI

tnerrucegakaelffotuptuoCYSI

tnerrucegakaelffolevel-wol2DPdna1DPI

tnerrucegakaelffolevel-hgih2DPdna1DPI

ecnaticapactupniRTCHdnaNIMFC

tnerrucylppuSI

1f
2f

3f
4f
5f

H

V

1HI
2HI
3HI
4HI
5HI
1LI

2LI
3LI
4LI
5LI

1HO
2HO

1LO
2LO
3LO
4LO

5LO
6LO

I

1FFO

2FFO

3FFO

LFFO

HFFO

NI

DD

V5.6= 5Aµ

NI

VNIV=

DD

VNIV=

DD

VNIV=

DD

VNIV=

DD

VNIV=

SS

VNIV=

SS

VNIV=

SS

VNIV=

SS

VNIV=

SS

IOAm1=V
I

Am5.0=V

O

IOAm1= 0.1V
I

Am5.0= 0.1V

O

IOAm5= 0.1V
IOAm1= 0.1V
IOAm5= 0.1V
I

O

VOV31= 5Aµ
VOV5.6= 5Aµ

VOV5.6= 5Aµ
VOV=
VOV=

f

V,Am5.0=

SS
DD

2NI

sgnitaR

nimpytxam

1MΩ
005kΩ
005kΩ
005kΩ
005kΩ

V1.0

DD

–1 V

DD

–1 V

DD

DD

V,zHM031=

V5.6ot5.3=0.1V

123Fp

2NI

nepostuptuo,dednuorg

latsyrc,zHM2.7,Vm07=

nepostuptuodednuorgstupni,gninnurrotallicso

stupni,gninnurrotallicso,detibihniLLP

V6.0

10.00.01An

10.00.01An

0203Am

0.1Am

DD

5Aµ
02Aµ
04Aµ
04Aµ
5Aµ
5Aµ
02Aµ
04Aµ
04Aµ

tinU

V

Functional Description

Serial Data Input

The LC7219 and LC7219M are initialized by 36-bit data on the serial data input, DI, after power-on as shown in
figure 1 and table 1.

Figure 1. Input data format

No.3661–4/12

Table 1. Input data bits

stiBemaNnoitpircseDstibdetaleR

61ot1D

32ot71O

42NETC

82ot52R

03,92PS,VD

23,13FS,CS

33TG

43BT

63,53T

0

0

0

0T,1

LC7219, 7219M

Dot

D

51

51

D0Dot

3

atadtroptuptuO

OstibataD

Oot

RstiB

stiBT0Tot

0

Oeht,1siBTfI

0

Rot

0

3

.derongi

stiblortnoctseT

1

Oot

6

Rot

3

oitarredividelbammargorP

Dfiderongiera

4

6

.noitcelesdnabycneuqerf

.edomtnemerusaem

elbanetuptuoesabemiT

.bslehtsi

elbaneretnuocesoprup-lareneG

.0ottessiNETCerofebrellortnoclanretxeehtotderrefsnart

tcelesycneuqerfecnerefeR

.ecnadepmihgihemocebstuptuopmup-egrahceht

tcelesytivitisnesdnatcelesrediviD

.6elbatninwohssadetcelessiNIMA

tceleslavretniemitretnuocesoprup-lareneG

.0TUOnotuptuosilangisesabemitzH8ehtdnaderongisitib

tcelestnemerusaemdoirep/ycneuqerfdnatcelestupniretnuocesoprup-lareneG

OehT.0TUOnotuptuosilangisesabemitelcycytud%04,zH8eht,1siBTnehW

0

.noitarepolamronrof0otteseradnagnitsetecivedrofdesuera

.6elbatninwohssasgalfPSdnaVDehtfognittesehtybdenimretedsibslehT.bsmehtsi

,1sitibatadanehW.ylevitcepser,strop6TUOot0TUOehtotnidehctalera

rofdesuebnacstuptuoesehT.HGIH,0nehwdna,WOLsiniptuptuognidnopserroceht

erastuniRTCLdnaRTCHehtdnatesersiretnuocesoprup-larenegtib-02eht,0siNETCnehW

roRTCHnolangisehtdnadelbanesiretnuoceht,1sigalfNETCehtnehW.dnuorgotdellup

ebdluohstuptuoretnuocesoprup-larenegehttahtetoN.derusaemsi,CSybdetceles,RTCL

ehtnehW.2elbatninwohssaycneuqerfecnereferehttcelesroLLPehtelbasid

dna,dnuorgotdelluperaNIMFdnaNIMA,deppotssiredividelbammargorpeht,delbasidsiLLP

nehwegnarycneuqerftupniehtstcelesPS.NIMAroNIMFtupnirotallicso-lacolehttcelesVD

nehwtnemerusaemdoireproycneuqerfstcelesFS.tupniretnuocesoprup-larenegehtstcelesCS

ycneuqerfnisiretnuoceht,detcelessiRTCHnehW.7elbatninwohssadetcelessiRTCL

nehW.derusaemebotsdoirepforebmunehtrolavretniemittnemerusaemehtstcelesTGtiB

.detcelessidoirep1rosm06,0=TGnehwdna,detceleserasdoirep2rosm03neht,1=TG

sistib

PS,VD

BT

TG,FS,CS

TG,NETC

FS,CS,NETC

O

0

The reference frequency is selected by bits R0 to R3 as shown in table 2.
Table 2. Reference frequency selection

R

R

R

0

0000 001
0001 05
0010 52
0011 52
0100 5.21
0101 52.6
0110 521.3
0111 521.3

1

R

2

3

)zHk(ycneuqerfecnerefeR

Table 2. Reference frequency selection–continued

R

R

R

0

1000 01
1001 9
1010 5
1011 1
1100
1101
1110
1111

1

R

2

3

Serial Data Input Timing

The timing for the serial data input is shown in figure 2. The first four bits, A0 to A3, are the mode select bits.
In 36-bit transfer mode, the final data bits are T0 and T1, and in 24-bit transfer mode, O6 and CTEN.

)zHk(ycneuqerfecnerefeR

tibihniLLP

Note

t1≥1.5µs, t2≥0µs, t3≥1.5µs, t4<1.5µs

Figure 2. Input timing

No.3661–5/12

LC7219, 7219M

Serial Data Output

The LC7219 and LC7219M both have an internal 28-bit shift register that comprise two bits representing the state of
IN0 and IN1 (I0 and I1, respectively), a 20-bit general-purpose counter address (C0 to C19) and unlock flags (UL0 to
UL3) as shown in table 3.
The shift register contents are clocked out on DO when the serial data output mode is selected as shown in figure 3.
The internal circuit of outputs DO and OUT0 to OUT6 are shown in figure 4.

Table 3. Shift register data

stiBemaN noitpircseD
2,1I
4,3dilavnI

42ot5C

82ot520LUot3LU

0

0I,1

I

0

Cot

91

stiBC0Cot

atadtroptupnI

91

nehwtessi0LU Φ
nehwtessi1LU Φ
nehwtessi2LU Φ
nehwtessi3LU Φ

dna,0NIfoetatsehtsiI1.1NIfoetatseht,

eulavretnuocesoprup-lareneG

stibsutatskcolnuLLP

≥ sµ1.1

RORRE

≥ sµ2.2

RORRE

≥ sµ3.3

RORRE

≥ sµ55.0

RORRE

C.retnuoctib-02ehtfoeulavdehctalehtera

91

.tessitibeht,latsyrczHM2.7arofwolebnwohssatibnevig

.bsmehtsi

arofeulavehtsdeecxerorreesahpehtnehW.tiucricrotcetedkcolnuehtmorfataddehctalehtera3LUot0LUstiB

Figure 3. Shift register data format

Figure 4. Output driver internal circuits

Serial Data Output Timing

The timing for the serial data output is shown in figure 5. Bits A0 to A3 are the mode select bits. When CE goes HIGH,
I0 is output on DO, and each subsequent data bit is output on the falling edge of CL. CE should be held HIGH for 27
clock cycles to allow all data to be output.
In serial data output mode, DO is forced HIGH when CE goes LOW as shown in figure 5. DO goes LOW when the
status of IN0 changes. In frequency or period measurement modes, DO goes LOW when frequency or period measure­ment is completed.

Note

t1≥1.5µs, t2≥0µs, t3≥1.5µs, t5<1.5µs

Figure 5. Output timing

No.3661–6/12

LC7219, 7219M

Serial Bus Data Transfer

The LC7219 and LC7219M can both transfer data in
three different modes-36-bit input data transfer, 24-bit
input data transfer and 28-bit output data transfer. The
transfer mode is selected by the four data bits on DI
immediately prior to CE going HIGH as shown in figure
6 and table 4. These bits are synchronized to the clock
and are latched into the mode register on the rising edge
of CE.

Table 4. Mode selection

edoMA

tupniatadlairestib-63 0001

tupniatadlairestib-42 0010

tuptuoatadlaires 0011

0000

lagellI

01
10
11

A

3

A

2

1

××
××
××

Figure 6. Transfer mode select

A

0

Rstibfoseulav

Rot1.

0

.derrefsnartebtonnacataD

noitpircseD

desuebdluosedomsihT.lDnonidekcolceraatadlortnocehtfostibllA

ehtyfidomotdesueboslanactI.ecivedehtezilaitiniotpu-rewopretfa

otdesusiedomsihT.lDnonidekcolceraatadlortnocehtfostib42

.tibelbaneretnuocesoprup-lareneg

.sgalfkcolnuLLPehtdnaeulavretnuocesoprup

ehtdnastibtroptuptuoeht,stiboitarreividelbammargorpehttupni

-larenegeht,atadtupniehtsesirpmocatadehT.ODnotuptuosiataD

Note

× = don’t care

Programmable Divider

The configurration of the programmable divider is shown in figure 7. Input mode selection is shown in table 5.

Figure 7. Programmable divider

Table 5. Programmable divider selection

VDPS)zHM(egnarycneuqerftupnIredivid2/1

1
01 04ot2–
00 0.01ot5.0––

×

061ot01

✓✓✓

71/1dna61/1

rewollawseslup

✓✓

✓

elbammargorptib-21

redivid

Note

× = don’t care
When an FM signal is input on FMIN, the actual divider
ratio is double the set ratio. For channel steps of 1, 5 and
9 kHz, a 3.6MHz crystal should be used. The program­mable divider ratio is determined by the setting of the DV
and SP bits as shown in table 6.

Table 6. Divider ratio settings

VDPSbsloitarteSoitarlautcA

1

×

01 0D53556ot652oitarteS
00 4D6904ot4oitarteS

0D53556ot652oitarteseciwT

troptupnI

NIMF
NIMA
NIMA

Note

× = don’t care

No.3661–7/12

LC7219, 7219M

General-purpose Counter

The 20-bit general-purpose counter is used for both frequency and period measurement as shown in figure 8. The
measurement mode is selected by bits SC and SF as shown in table 7. The counter value is output on DO with the msb
first.

Figure 8. General-purpose counter

Table 7. General-purpose counter mode selection

CSFStroptupnIretemaraP

1

×

01 RTCL)evawenis(tnemerusaemycneuqerF
00 RTCL)evaweslup(tnemerusaemdoireP

RTCH)evawenis(tnemerusaemycneuqerF

Note

× = don’t care
In frequency measurement mode, the input cycles during a 30 or 60 ms interval are counted. Either LCTR or HCTR

can be selected as the counter input.
In period measurement mode, LCTR is the single input, and the 900kHz cycles in one or two periods of the LCTR
signal are counted.
The counter starts when the CTEN flag is set. The serial input data is latched in on the falling edge of CE. The input
data on HCTR or LCTR should be input within 10 ms of this transition.
The period or frequency measurement count should be read while CTEN is still set to 1, as the counter is reset by
setting CTEN to 0. CTEN should be set to 0 before each measurement.
The LCTR signal is passed directly to the counter input. The HCTR signal is passed through a divide-by-eight
prescaler. The actual HCTR frequency is, therefore, eight times the measured frequency.
When the universal counter is used as the IF counter, the state of the IF-IC SD (station detect) signal must be checked
by the microcontroller, and the IF counter buffer output turned on only after the SD signals are activated. Auto-search
techniques using only the IF counter are not advisable since it is possible that the search can stop incorrectly at a
location that does not have a station due to the IF counter buffer output leakage.
DO goes HIGH when the CTEN flag is set to 1, and LOW when frequency or period measurement is completed. DO
can be monitored to check for measurement completion. The timing for the general-purpose counter is shown in figure

9.

No.3661–8/12

LC7219, 7219M

Figure 9. General-purpose counter timing

Using DO monitor IN0

If the general-purpose counter is not being used and CTEN is 0, DO can be used to monitor changes in the external
input signal IN0 as shown in figure 10.

Figure 10. IN0 output monitoring timing

Notes

1. Specify serial data output. DO goes HIGH after data is output on DO and CE goes LOW.

2. DO goes LOW when IN0 changes.

No.3661–9/12

LC7219, 7219M

Using DO to monitor for measurement completion

DO can be used to monitor for frequency or period measurement completion as shown in figure 11.

Figure 11. Measurement completion timing

Notes

1. Setting CTEN to 1 sets DO HIGH and prevents IN0 from affecting DO.

2. DO goes LOW when the measurement is complete.

Phase-locked Loop

Reading the PLL unlock flags

The PLL unlock flags are set on the rising edge of the internal Φ
signal. In serial data output mode, the flags set since the last rising edge of CE can be read. This is the interval t0 to t
shown in figure 12.
Each PLL unlock flag is set if the corresponding time interval is exceeded as follows.

UL0 is set when Φ
UL1 is set when Φ
UL2 is set when Φ
UL3 is set when Φ

The flag values for different error ranges, where Φ

If Φ
If 0.55µs≤Φ
If 1.11µs≤Φ
If 2.22µs≤Φ
If 3.33µs≤Φ

<0.55µs, UL=0000

ERROR

ERROR
ERROR
ERROR
ERROR,

≥1.11µs

ERROR

≥2.22µs

ERROR

≥3.33µs

ERROR

≥0.55µs

ERROR

<1.11µs, UL=1000
<2.22µs, UL=1001
<3.33µs, UL=1011

UL=1111

is the phase error for the 7.2MHz crystal, are as follows.

ERROR

signal and cleared on the rising edge of the CE

ERROR

1

Figure 12. PLL unlock flag timing

No.3661–10/12

LC7219, 7219M

Application Notes

The recommended crystal oscillator for the LC7219 and
LC7219M is the Nihon Dempa Kogyo Co., Ltd. (NDK)
LN-X-0702 (NR-18 type) or the LN-P-0001 (AT-51
type). The oscillator is connected as shown in figure 13.

Figure 13. Crystal oscillator connection

The device parameters for crystal oscillator frequencies

3.6MHz and 7.2MHz are shown in table 8.

T ypical Application

Figure 14 shows a TV/AM/FM system using the IF counting system for electronic tuning.

Table 8. Device parameters vs. crystal frequency

retearaP

kcolcesabemiTzH8zH4

kcolcmetsySzHk004zHk002

ycneuqerF

tnemerusaem

lavretni

doireP

tnemerusaem

langiskcehc

ecnerefeR

seicneuqerf

tuptuo/tupniataD

gnimit

sm06/03sm021/06

zHk009zHk054

,zHk001

t

t,sµ5.1

1

3

ycneuqerflatsyrC

zHM2.7zHM6.3

,zHk9,zHk5,zHk1

,zHk05,zHk52,zHk01

,zHk05

sµ5.1t1t,sµ3

,zHk5.4,zHk5.2,zHk5.0

,zHk52,zHk5.21,zHk5

sµ3

2

Figure 14. TV/AM/FM system

The FMIN, AMIN, HCTR, and LCTR inputs should be capacitively coupled using a capacitor in the range 50 to
100pF. These coupling capacitors should be as close as possible to their respective inputs to minimize the effects of
stray capacitance.
The IF signals measurement should be done afte the IF-IC SD (station detect) signal are activated.
The circuit characteristics for each mode, TV, FM and AM, are shown in table 9.

Table 9. Circuit characteristics

edoMVDPS

VT1
MF1

MA00 zHk01zHk000,1zHk054zHk054,1zHk01541

×
×

gninuT

spetsycneuqerf

zHk05

zHk001zHM09zHM7.01zHM7.001zHk05700,1

ycneuqerfFRycneuqerfFIycneuqerfOCV

zHM57.736

)FHU(

zHM7.01zHM54.846zHk521.3969,21

ecnereferLLP

ycneuqerf

Note

× = don’t care

No.3661–11/12

elbammargorP

oitarredivid

LC7219, 7219M

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

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Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
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This catalog provides information as of July, 2001. Specifications and information herein are subject to
change without notice.

PS No.3661–12/12