Sanyo LC7216M Specifications

CMOS IC

Ordering number : EN3355B

31299RM(OT)/02793JN KAWA/4280TA, TS KAWA No. 3355-1/15

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PLL Frequency Synthesizer

for Electronic Tuning in AV Systems

LC7216M

Overview

The LC7216M is PLL frequency synthesizers for electronic tuning. The LC7216M is optimal for AM/FM tuner circuits that require high mounting densities.

Features

• This product feature a rich set of built-in functions for AV applications, including reference frequency and unlock detection circuits, I/O ports and a generalpurpose counter.

Functions

• Programmable dividers — FMIN pin: 130 MHz at 70 mVrms and 160 MHz at

110 mVrms input (built-in prescaler)

— AMIN pin: Pulse swallower and direct division

techniques

• Reference frequencies: Ten selectable frequencies: 1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz

• Output ports: 5 pins Complementary outputs: 2 pins N-channel open drain outputs: 3 pins

• Input ports: 2 pins

• General-purpose counter: For measuring IF and other signals (Also used for station detection when functioning as an IF counter.) — HCTR pin: Frequency measurement (for inputs up

to 70 MHz)

— LCTR pin: Frequency and period measurement

• PLL unlock detection circuit Detects phase differences of 0.55, 1.11, 2.22 and 3.33 µs.

• Package: MFP20

Package Dimensions

unit: mm

3036B-MFP20

12.6

0.15

1.27

0.35

0.59

1.8 max

1.50.1

5.4

0.625 6.35

7.6

SANYO: MFP20

[LC7216M]

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

No. 3355-2/15

LC7216M

Pin Assignment

Block Diagram

Pin Symbols

XIN, XOUT: Crystal oscillator (7.2 MHz) FMIN, AMIN: Local oscillator signal input CE, CL, DI, DO: Serial data I/O OUT1 to OUT5: Output ports IN0, IN1: Input ports HCTR, LCTR: General-purpose counter inputs PD: Charge pump output

Note: Crystal oscillator example: 7.200 MHz, CL16 pF (C = 27 pF)

•LN-X-0702 (NR-18 type)

•LN-P-0001 (AT-51 type)

Manufactured by: NIHON DEMPA KOGYO CO., LTD.

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V

Note: 1.

DV and SP are bits in the serial data. *: don’t care

2. Frequency measurement

3. Frequency measurement

4. Period measurement

5. f

2: 10 to 160 MHz/VIN2

0.11 Vrms (minimum)

6. f

4: 10 to 70 MHz/VIN4

0.11 Vrms (minimum)

No. 3355-3/15

LC7216M

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

1 V

4.5 6.5 V

2 VDD: Crystal oscillator guaranteed operation 3.5 6.5 V

Input high level voltage

1 CE, CL, DI, IN0, IN1 2.2 6.5 V

2 LCTR: Pulse waveform, DC coupling

0.7 VDD1 VDD1 V

Input low level voltage

1 CE, CL, DI, IN0, IN1 0 0.7 V

2 LCTR

0 0.3 VDD1 V

Output voltage

OUT

1 DO 6.5 V

OUT

2 OUT3 to OUT5 13 V

1 XIN: Sine wave capacitor coupling, VDD2 1.0 7.2 8.0 MHz

2 FMIN: Sine wave capacitor coupling, VDD1

10 130 (160)*5MHz

Input frequency

3 AMIN: Sine wave capacitor coupling, VDD1

0.5 40 MHz

4 HCTR: Sine wave capacitor coupling, VDD1

10 60 (70)*6MHz

5 LCTR: Sine wave capacitor coupling, VDD1

15 500 kHz

6 LCTR: Pulse wave DC coupling, VDD1

1.0 20 × 103Hz

Crystal oscillators for which

Xtal XIN-XOUT: CI ≤ 50 Ω 3.0 7.2 8.0 MHz

operation is guaranteed

1 XIN: Sine wave capacitor coupling, VDD1 0.5 1.5 Vrms

2 FMIN: Sine wave capacitor coupling, VDD1

0.07

0.5 Vrms

(0.11)

Input amplitude VIN3 AMIN: Sine wave capacitor coupling, VDD1 0.07 0.5 Vrms

4 HCTR: Sine wave capacitor coupling, VDD1

0.07

0.5 Vrms

(0.11)

VIN5 LCTR: Sine wave capacitor coupling, VDD1

0.07 0.5 Vrms

DV SP Input frequency 1/2 divider 1/16, 17 swallow 12-bit main divider Input pin

1 * 10 to 130 (160) MHz

●● ●● ●● FMIN

0 1 2 to 40 MHz —

●● ●● AMIN

0 0 0.5 to 10 MHz — —

●● AMIN

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max V

–0.3 to +7.0 V

Input voltage

1 CE, CL, DI, IN0, IN1 –0.3 to +7.0 V

2 Input pins other than VIN1 –0.3 to VDD+ 0.3 V

OUT

1 DO –0.3 to +7.0 V

Output voltage

OUT

2 OUT1, OUT2 –0.3 to VDD+ 0.3 V

OUT

3 OUT3 to OUT5 –0.3 to +15 V

OUT

4 Output pins other than V

OUT

1, V

OUT

2 and V

OUT

3 –0.3 to VDD+ 0.3 V Allowable power dissipation Pd max Ta ≤ 85°C 200 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Electrical Characteristics for the Allowable Operating Ranges

Note: A capacitor of at least 2000 pF must be inserted between the power supply VDDand VSSpotentials.

No. 3355-4/15

LC7216M

Parameter Symbol Conditions

Ratings

Unit

min typ max

Rf1 XIN 1.0 MΩ Rf2 FMIN 500 kΩ

Internal feedback resistance Rf3 AMIN 500 kΩ

Rf4 HCTR 500 kΩ Rf5 LCTR 500 kΩ

Hysteresis V

LCTR 0.1 V

0.6 V

1 CE, CL, DI: VI= 6.5 V 5.0 µA

2 IN0, IN1: VI= V

5.0 µA

Input high level current I

3 XIN: VI= V

20 µA

4 FMIN, AMIN: VI= V

40 µA

5 HCTR, LCTR: VI= V

40 µA

1 CE, CL, DI: VI= V

5.0 µA

2 IN0, IN1: VI= V

5.0 µA

Input low level current I

3 XIN: VI= V

20 µA

4 FMIN, AMIN: VI= V

40 µA

5 HCTR, LCTR: VI= V

40 µA

Output high level voltage

1 OUT1, OUT2: IO= 1 mA VDD– 1.0 V

2 PD: IO= 0.5 mA VDD– 1.0 V

1 OUT1, OUT2: IO= 1 mA 1.0 V

2 PD: IO= 0.5 mA 1.0 V

Output low level voltage

3 OUT3 to OUT5: IO= 5 mA 1.0 V

4 DO: IO= 5 mA 1.0 V

OFF

1 OUT3 to OUT5 = 13 V 5.0 µA

Output off leakage current

OFF

2 DO: VO= 6.5 V 5.0 µA

Three-state high level

OFFH

PD: VO= V

0.01 10.0 nA

off leakage current Three-state low level

OFFL

PD: VO= V

0.01 10.0 nA

off leakage current Input capacitance C

FMIN, HCTR 1 2 3 pF V

: fIN2 = 130 MHz, VIN2 = 70 mVrms,

1 with a 7.2 MHz crystal, other input pins at VSS, 20 30 mA

Current drain

output pins open VDD: PLL block stopped (PLL inhibit state), crystal

2 oscillator operating, with a 7.2 MHz crystal, 1.0 mA

other input pins at V

, output pins open

Pin Functions

Note: * The high and low level input voltages for the CE, CL, DI, IN0 and IN1 pins are VIH= 2.2 to 6.5 V and VIL= 0 to 0.7 V, regardless of the power

supply voltage V

No. 3355-5/15

LC7216M

Pin No. Symbol I/O Type Function

XIN

XOUT

FMIN

AMIN

Input

Output

Input

Three-state

—

Input*

Output

(N-channel

open drain)

Xtal OSC

Local oscillator signal input

Charge pump outputs

Power supply

Ground

Chip enable

Clock

Input data

Output data

• Connections for a 7.2 MHz crystal oscillator

• FMIN is selected when DV in the serial input data is set to 1.

• Input frequency range: 10 to 130 MHz (70 mVrms minimum)

• The signal passes through an internal divide-by-two prescaler and is then supplied to the swallow counter.

• Although the divisor setting is in the range 256 to 65,536, the actual divisor will be twice the set value due to the presence of the internal divide-by-two prescaler.

• AMIN is selected when DV in the serial input data is set to 0.

• When SP in the serial input data is set to 1: — Input frequency range: 2 to 40 MHz (70 mVrms minimum). — The signal is supplied directly to the swallow counter without passing through the

internal divide-by-two prescaler.

— The divisor setting is in the range 256 to 65,536 and the actual divisor will be the

value set.

• When SP in the serial input data is set to 0: — Input frequency range: 0.5 to 10 MHz (70 mVrms minimum). — The signal is supplied directly to a 12-bit programmable divider. — The divisor setting is in the range 4 to 4,096 and the actual divisor will be the

value set.

• PLL charge pump outputs. High levels are output from PD when the local oscillator frequency divided by n is higher than the reference frequency, and low levels are output when that frequency is lower than the reference frequency. This pin go to the floating state when the frequencies agree.

• The LC7216M power supply pin. A voltage of between 4.5 and 6.5 V must be provided when the PLL is operating. The supply voltage can be lowered to 3.5 V when only operating the crystal oscillator circuit to acquire the controller clock and the clock time base outputs.

• The LC7216M ground pin

• This pin must be set high when inputting serial data (via DI) or when outputting serial data (via DO).

• The clock input used for data signal synchronization during serial data input (via DI) or output (via DO).

• Input pin used when transferring serial data from the controller to the LC7216M.

• A total of 36 bits of data must be supplied to set up the LC7216M initial state.

• Output pin used when transferring serial data to the controller from the LC7216M.

• A total of 28 bits from an internal shift register can be output in synchronization with the CL signal.

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