Sanyo LC72151V Specifications

Ordering number : ENN*6976

83101RM (OT) No. 6976-1/29

Overview

The LC72151V is a PLL frequency synthesizer for car audio systems. It can implement high-performance multifunction tuners such as RDS tuners and features a fast locking circuit.

Functions

• High-speed programmable divider — FMIN: 10 to 160 MHz: Pulse swallower type — AMIN: 2 to 40 MHz: Pulse swallower type

0.5 to 10 MHz: Direct division type

• IF counter — HCTR: 0.4 to 25 MHz: for FM IF count — LCTR: 10 to 500 kHz: for AM IF count

1.0 to 20 × 103Hz: for frequency measurement

• Reference frequency — One of 11 frequencies may be selected (when a

10.25 or 10.35 MHz crystal is used) 50, 30*, 25, 12.5, 10, 9*, 6.25, 5, 3.125, 3*, 1 kHz Note:

Cannot be used when a 10.25 MHz crystal is used

• Phase comparator — Supports dead band control — Built-in unlock detection circuit — Built-in deadlock clearing circuit

• Built-in amplifier for forming an active low-pass filter — Built-in operational amplifier for FM high-speed

locking

— Built-in MOS transistor for AM tuning

• Built-in crystal oscillator output buffer

• I/O ports — General-purpose I/O: 2 pins — Four input ports (maximum) — Three output ports (maximum)

• Serial data I/O — Supports communication with the controller in the

CCB format.

• Operating ranges — Supply voltage: 4.5 to 5.5 V (VDD)

7.5 to 9.5 V (AVDD)

— Operating temperature: –40 to +85°C

• Package — SSOP30

Package Dimensions

unit: mm

3191A-SSOP30

151

1630

9.75

0.5

7.6

5.6

0.1

(1.3)

1.5max

0.65 (0.43)

0.22

0.15

Preliminary

SANYO: SSOP30

[LC72151V]

LC72151V

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PLL Frequency Synthesizer for Electronic Tuning

in Car Audio Systems

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

No. 6976-2/29

LC72151V

Pin Assignment

LC72151

(Top view)

XIN

XOUT

I/O-1

I/O-2

1 30

XBUF

O-3

FMIN

AMIN

AOUT1

AOUT2

PDM2

PDF

PDM1

AIN2

PDS

TGI1

TGO

TGI2

AIN1

–

HCTR/I-3

LCTR/I-4

AREF

No. 6976-3/29

LC72151V

Block Diagram

PDS

PDF

AOUT1

AIN1 AREF

PDM1

AMIN

HCTR/I-3

TGI2

FMIN

XOUT

XIN

UNIVERSA L

COUNTER

FAST LOCK UP

CONTROL

UNLOCK

DETECTOR

REFERENCE

DIVIDER

PHASE DETECTOR

CHARGE PUMP

DATA SHIFT REGISTER

LATCH

12bits PROGRAM MABL E

DIVIDER

SWALLOW COUNTER

1/16,1/17 4bits

POWER

RESET

CCB

I/F

PDS

TGI1

CL DO I/O-1 I/O-2

CHARGE PUMP

for FAST LOCK

TGO

CE DI O-3

PDM2

AOUT2

AIN2

LCTR/I-4

XBUF

No. 6976-4/29

LC72151V

Parameter Symbol Pin Ratings Unit

Supply voltage V

max

* –0.3 to +7.0

* –0.3 to +11.0

1 max CE, CL, DI –0.3 to +7.0

2 max

XIN, FMIN, AMIN, HCTR/I-3, LCTR/I-4,

–0.3 to VDD+ 0.3

Maximum input voltage

AIN2, TGI1, TGI2, TGO

3 max I/O-1, I/O-2 –0.3 to +15.0

4 max AIN1, AREF –0.3 to +6.5

1 max DO –0.3 to +7.0

2 max

XOUT, PDM1, PDM2, PDS, PDF, XBUF, TGI1,

–0.3 to VDD+ 0.3

Maximum output voltage

TGI2, TGO

3 max I/O-1, I/O-2, O-3, AOUT2 –0.3 to +15.0

4 max AOUT1 –0.3 to +11.0

1 max I/O-1, I/O-2, O-3 0 to 10.0

Maximum output current I

2 max DO, TGI1, TGI2, TGO, AOUT1, AOUT2 0 to 5.0 mA

3 max XBUF 0 to 3.0 Allowable power dissipation Pd max (Ta ≤ 85°C) SSOP30 :160 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= AVSS= 0 V

Note: Power must be applied to AVDDbefore applying to VDDand AVDDmust be higher than or equal to VDD.

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

VDD1 V

VDD≤ AV

4.5 5.5

Supply voltage V

2 AV

VDD≤ AV

7.5 8.5 9.5 V

3 V

Serial data retention voltage 2.0

1 CE, CL, DI 0.7V

6.5

High-level input voltage

2 I/O-1, I/O-2 0.7V

HCTR/I-3,

0.7V

LCTR/I-4 CE, CL, DI,

Low-level input voltage V

I/O-1, I/O-2,

0 0.3V

HCTR/I-3, LCTR/I-4

1 DO 0 6.5

Output voltage

2 AOUT1 0 9.5

I/O-1, I/O-2, O-3,

0 13

AOUT2

1 XIN VIN1 *

7 11

2 FMIN VIN2 *

10 160

3 AMIN (SNS=1) VIN3 *

2 40 MHz

Input frequency f

4 AMIN (SNS=0) VIN4 *

0.5 10

5 HCTR/I-3 VIN5 *

0.4 25

6 LCTR/I-4 VIN6 *

10 500 kHz

7 LCTR/I-4 VIN7 *

1.0 20 × 10

Allowable Operating Ranges at Ta = –40 to 85°C, VSS= AVSS= 0 V

Continued on next page.

No. 6976-5/29

LC72151V

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

1 XIN fIN1 200 1500

2-1 FMIN f = 10 to 50 MHz 40 1500

2-2 FMIN f = 50 to 130 MHz 20 1500

2-3 FMIN f = 130 to 160 MHz 40 1500

3 AMIN (SNS=1) fIN3 40 1500

Input amplitude V

4 AMIN (SNS=0) fIN4 40 1500 mVrms

5-1 HCTR/I-3 f = 0.4 to 25 MHz *

40 1500

5-2 HCTR/I-3 f = 8 to 12 MHz *

70 1500

6-1 LCTR/I-4 f = 10 to 400 kHz *

40 1500

6-2 LCTR/I-4 f = 400 to 500 kHz *

20 1500

6-3 LCTR/I-4 f = 400 to 500 kHz *

70 1500

Guaranteed crystal oscillator

X’tal XIN, XOUT *

10.25 10.35 MHz

frequency ranges

Notes: 1. Sine wave with capacitor coupled.

2. Pulse wave with DC coupled.

3. Serial data: CTC = 0

4. Serial data: CTC = 1

5. Recomended CI value for the crystal oscillator: CI ≤ 70 Ω

Continued from preceding page.

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max Rf1 XIN 1 MΩ Rf2 FMIN 500

Internal feedback resistance Rf3 AMIN 500

kΩ

Rf4 HCTR/I-3 500 Rf5 LCTR/I-4 500

Internal pull-down resistance

Rpd1 FMIN 80 200 600

kΩ

Rpd2 AMIN 80 200 600

Hysteresis V

HIS

CE, CL, DI, LCTR/I-4 0.1 V

1 PDM1, PDM2, PDS, PDF

= – 1 mA VDD– 1.0

High-level output voltage

= – 2 mA VDD– 2.0

2 AOUT1 IO= – 1 mA AVDD– 1.0

3 XBUF IO= – 0.5 mA VDD– 1.5

1 PDM1, PDM2, PDS, PDF

= 1 mA 1.0

= 2 mA 2.0

2 AOUT1 IO= 1 mA 1.0

3 XBUF IO= 0.5 mA 1.5

Low-level output voltage

= 1 mA 0.2

4 I/O-1, I/O-2, O-3 IO= 5 mA 1.0

= 8 mA 1.6

5 DO

=1 mA 0.2

= 5 mA 1.0

6 AOUT2 IO= 1 mA, AIN2 = 1.3 V 0.5

1 CE, CL, DI VI= 6.5 V 5.0

2 I/O-1, I/O-2 VI= 13 V 5.0

3 HCTR/I-3, LCTR/I-4 VI= V

5.0 µA

High-level input current

4 XIN VI= V

0.11 0.9

FMIN, AMIN, HCTR/I-3,

VI= V

1.8 15

LCTR/I-4

6 AIN1, AREF VI= 5.5 V 0.01 100 nA

7 TGI1, TGI2, TGO VI= V

3.0 µA

Electrical Characteristics in the Allowable Operating Ranges

Continued on next page.

No. 6976-6/29

LC72151V

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

1 CE, CL, DI VI= 0 V 5.0

2 I/O-1, I/O-2 VI= 0 V 5.0

3 HCTR/I-3, LCTR/I-4 VI= 0 V 5.0

µA

Low-level input current

4 XIN VI= 0 V 0.11 0.9

FMIN, AMIN, HCTR/I-3,

VI= 0 V 1.8 15

LCTR/I-4

6 AIN1, AREF VI= 0 V 0.01 100 nA

7 TGI1, TGI2, TGO VI= 0 V 3.0 µA

= 8.5 V, I = ±3 mA,

70 140

= 8.5 V

Analog switch on resistance R

TGI1, TGI2, TGO

= 4.5 V, I = ±3 mA,

50 100 Ω

= 8.5 V

= 0.5 V, I = ±3 mA,

70 140

= 8.5 V

OFF

1 AOUT1 VO= 6.5 V 5.0

Output off leakage current I

OFF

2 I/O-1, I/O-2, O-3, AOUT2 VO= 13 V 5.0 µA

OFF

3 DO VO= 6.5 V 5.0

High-level 3-state off leakage current

OFFH

PDM1, PDM2, PDS, PDF VO= V

0.01 200 nA

Low-level 3-state off leakage current

OFFL

PDM1, PDM2, PDS, PDF VO= 0 V 0.01 200 nA

Input capacitance C

FMIN 6 pF

X’tal = 10.35 MHz

IDD1 V

fIN2 = 160 MHz 10 18 V

2 = 40 mVrms

PLL block stopped

2 V

(PLL INHIBIT)

0.5 1.5

X’tal OSC operating mA

Supply current

(X’tal = 10.35 MHz) PLL block stopped

3 AV

(PLL INHIBIT)

1.5

X’tal OSC stopped On-chip op-amp stopped

PLL block stopped

4 V

(PLL INHIBIT)

10 µA

X’tal OSC stopped On-chip op-amp stopped

Continued from preceding page.

No. 6976-7/29

LC72151V

Pin Functions

Pin No. Symbol Usage Function Pin circuit

• Crystal oscillator connection. (10.25 or 10.35 MHz)

XIN

XOUT

X’tal OSC

• FMIN is selected by setting DVS in the control data to 1.

• Enters high-speed locking mode by setting SNS in the control data to 1.

• Enters normal mode by setting SNS in the control data to 0.

• Input frequency: 10 to 160 MHz

• The signal is transmitted to the swallow counter.

• The divisor can be set to a value in the range 272 to 65,535.

8 FMIN Local oscillator signal input

• AMIN is selected by setting DVS in the control data to 0.

• When SNS in the control data is set to 1: Input frequency: 2 to 40 MHz The signal is directly transmitted to the swallow counter.

• When SNS in the control data is set to 0: Input frequency: 0.5 to 10 MHz The signal is directly transmitted to the 12-bit programmable divider. The divisor can be set to a value in the range 5 to 4,095.

9 AMIN Local oscillator signal input

• This pin must be set to the high level when inputting serial data to the LC72151V DI pin and when outputting serial data from the DO pin.

29 CE Chip enable

• Serial data input for transferring data from the controller to the LC72151V.

28 DI Input data

• Data synchronization clock signal used when inputting serial data to the LC72151V DI pin and when outputting serial data from the DO pin.

27 CL Clock

• Serial data output for transferring data from the LC72151V to the controller.

26 DO Output data

• LC72151V power supply. A voltage in the range 4.5 to 5.5 V must be provided when the PLL circuit is operating.

• The power-on reset circuit operates when power is first applied. Note: Power must be applied to AV

before applied to VDDand

must be higher than or equal to VDD.

———

Power

• LC72151V ground.7

Ground

• Input/output dual function pins

• The function will be selected according to IOC1 and IOC2 in the control data.

Data = 0: Input port

1: Output port

• When specified as an input port: The input pin state is transmitted to the system microcontroller from

DO pin. Input state = Low: data is 0

= High: data is 1.

• When specified as an output port: The output state will be determined according to I/O-1 and I/O-2 in

the control data. Data = 0: Low

= 1: Open

• These pin function as an input port at a power-on reset.

2 3

I/O-1 I/O-2

I/O ports

Continued on next page.

No. 6976-8/29

LC72151V

Continued from preceding page.

Pin No. Symbol Usage Function Pin circuit

• Dedicated output pin

• Latches OUT3 in the control data and outputs data from O-3 pin.

• This pin goes open state at a power-on reset.

5 O-3 Output port

• Op-amp for PLL active low-pass filter

• AV

is the analog system ground pin shared with low-pass filter Nch

MOS transistor.

• Voltage applied to AREF pin must be 1/2 that to VDDpin.

Note: Power must be applied to AV

before applied to VDD, and AV

must be higher than or equal to VDD.

19 12 13 14 15

AIN1 AREF AV

AOUT1

Op-amp for low-pass filter amp

AREF

AIN1

–

AOUT1

• PLL active low-pass filter Nch MOS transistor

• Source of the transistor is connected to AV

pin.

Note: Connect AV

pin to ground in use.

24 25

AIN2

AOUT2

Transistor for low-pass

filter amp

• PLL charge pump output When the frequency created by dividing the local oscillator signal

frequency by N is higher than the reference frequency, a high level is output from the PD pin. When lower, a low level is output. The PD pin goes to the high-impedance state when the frequencies match.

21 23 20

PDM1 PDM2

PDS

Charge pump output

• PLL high-speed locking charge pump output When the high-speed locking mode is selected, signal pulses is

output according to the frequency variation. This pin enters highimpedance state when the local oscillation frequency enters the set frequency range.

22 PDF

PLL high-speed locking charge

pump output

• PLL high-speed locking active low-pass filter transmission gate input/output dual function pins

Note: Connect AVSSpin to ground in use.

18 17 16

TGI1 TGI2 TGO

PLL high-speed locking TG

TGO

TGI2

TGI1

• HCTR is selected by setting CTS1 in the control data to 1. Input frequency: 0.4 to 25 MHz The signal is input to a divide-by-2 circuit and the result is input to a

general-purpose counter. This counter can also be used as an integrating counter.

The counter value is output as the result of the count, MSB first, from the DO pin.

There are four measurement periods: 4, 8, 32, and 64 ms.

• When H/I-3 in the control data is set, this pin functions as an input port, and the value is output from the output pin DO.

10 HCTR/I-3 General-purpose counter

• LCTR is selected by setting CTS1 in the control data to 1.

• When the LCTR is selected as described above and CTS0 is set to 1: This pin enters the frequency measurement mode. Input frequency: 10 to 500 kHz The signal is directly transmitted to the general-purpose counter.

• When CTS0 is set to 0 This pin enters period measurement mode. Input frequency: 1 Hz to 20 kHz Period can be measured either in single period or in double period. If

double period measurement is selected, the frequency is 2 Hz to 40 kHz.

The counter value is output as the result of the count, MSB first, from the DO pin.

• When L/I-4 in the control data is set: This pin functions as an input port, the value is output from the output

pin DO.

11 LCTR/I-4 General-purpose counter

Continued on next page.

Serial Data I/O Methods

Data is input to and output from the LC72151V using the Sanyo CCB (Computer Control Bus) format, which is the serial bus format used by SANYO audio ICs. This IC adopts a CCB format with an 8-bit address.

No. 6976-9/29

LC72151V

I/O mode

Address

Content

B0 B1 B2 B3 A0 A1 A2 A3

• Control data input (serial input) mode.

[1] IN1 (82) 0 0 0 1 0 1 0 0

• 32 bits of data are input.

• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of the input data.

• Control data input (serial input) mode.

[2] IN2 (92) 1 0 0 1 0 1 0 0

• 32 bits of data are input.

• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of the input data.

• Data output (serial data output) mode.

[3] OUT (A2) 0 1 0 1 0 1 0 0

• The number of bits output is equal to the number of clock cycles.

• See the “DO Output Data (Serial Data Output) Structure” item for details on the content of the output data.

Continued from preceding page.

Pin No. Symbol Usage Function Pin circuit

• Output buffer for the crystal oscillator circuit

• When XB in the serial data is set to 1, the output buffer operates and the crystal oscillator signal (a pulse signal) is output.

When XB is 0, XBUF outputs a low level. After the power-on reset, the output buffer is fixed at the low level.

4 XBUF Crystal oscillator buffer

XOUT

I/O mode determined

A3A2A1A0B3B2B1B0DI

Fir

st Data IN1/2

First Data OUT

CL: Normally Hi

1 2

CL: Normally Low

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