Sanyo LC72151V Specifications

Ordering number : ENN*6976

CMOS IC

LC72151V

PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems

Preliminary

Overview

The LC72151V is a PLL frequency synthesizer for car audio systems. It can implement high-performance multifunction tuners such as RDS tuners and features a fast locking circuit.

Functions

•High-speed programmable divider

—FMIN: 10 to 160 MHz: Pulse swallower type

—AMIN: 2 to 40 MHz: Pulse swallower type

0.5to 10 MHz: Direct division type

•IF counter

—HCTR: 0.4 to 25 MHz: for FM IF count

—LCTR: 10 to 500 kHz: for AM IF count

1.0to 20 × 103 Hz: for frequency measurement

•Reference frequency

—One of 11 frequencies may be selected (when a

10.25or 10.35 MHz crystal is used)

50, 30*, 25, 12.5, 10, 9*, 6.25, 5, 3.125, 3*, 1 kHz Note: Cannot be used when a 10.25 MHz crystal is

used

•Phase comparator

—Supports dead band control

—Built-in unlock detection circuit

—Built-in deadlock clearing circuit

•Built-in amplifier for forming an active low-pass filter

—Built-in operational amplifier for FM high-speed locking

—Built-in MOS transistor for AM tuning

•Built-in crystal oscillator output buffer

•I/O ports — General-purpose I/O: 2 pins

—Four input ports (maximum)

—Three output ports (maximum)

•Serial data I/O

—Supports communication with the controller in the CCB format.

•Operating ranges

—Supply voltage: 4.5 to 5.5 V (VDD)

7.5to 9.5 V (AVDD)

—Operating temperature: –40 to +85°C

•Package

—SSOP30

Package Dimensions

unit: mm

3191A-SSOP30

[LC72151V]

30		16
			5.6	7.6
				0.5
1		15	1.5max	0.15
	9.75	(1.3)

		0.1
0.22	0.65	(0.43)

SANYO: SSOP30

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

83101RM (OT) No. 6976-1/29

		LC72151V
Pin Assignment
		LC72151V
XOUT	1		30	XIN
I/O-1	2	S	29	CE
I/O-2	3	S	28	DI
XBUF	4	S	27	CL
O-3	5		26	DO
VDD	6		25	AOUT2
VSS	7	AVSS	24	AIN2
FMIN	8		23	PDM2
AMIN	9		22	PDF
HCTR/I-3	10		21	PDM1
LCTR/I-4	11		20	PDS
AREF	12		19	AIN1
AVDD	13	–	18	TGI1
AVSS		+	17	TGI2
	14
AOUT1	15		16	TGO

(Top view)

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LC72151V

Block Diagram
			XBUF
XIN	REFERENCE						PHASE DETECTOR	PDM1
	DIVIDER						CHARGE PUMP
								PDM2
XOUT							PDS
								PDS
FMIN	SWAL						UNLOCK	TGI1
							DETECTOR
								TGI2
								TGO
AMIN	12bits						CHARGE PUMP	PDF
							for FAST LOCK
								AIN2
HCTR/I-3	UNIVERSAL	DATA SHIFT REGISTER					FAST LOCK UP	AOUT2
	COUNTER		LATCH				CONTROL
								AVDD
LCTR/I-4								AIN1
			CCB					AREF
			I/F					AVSS
VDD	POWER							AOUT1
	ON
VSS	RESET
	CE	DI	CL	DO	I/O-1	I/O-2	O-3

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LC72151V

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = AVSS = 0 V

	Parameter	Symbol	Pin	Ratings	Unit
	Supply voltage	VDD max	VDD *	–0.3 to +7.0	V
			AVDD *	–0.3 to +11.0
		VIN1 max	CE, CL, DI	–0.3 to +7.0
		VIN2 max	XIN, FMIN, AMIN, HCTR/I-3, LCTR/I-4,	–0.3 to VDD + 0.3
	Maximum input voltage		AIN2, TGI1, TGI2, TGO		V
		VIN3 max	I/O-1, I/O-2	–0.3 to +15.0
		VIN4 max	AIN1, AREF	–0.3 to +6.5
		VO1 max	DO	–0.3 to +7.0
		VO2 max	XOUT, PDM1, PDM2, PDS, PDF, XBUF, TGI1,	–0.3 to VDD + 0.3
	Maximum output voltage		TGI2, TGO		V
		VO3 max	I/O-1, I/O-2, O-3, AOUT2	–0.3 to +15.0
		VO4 max	AOUT1	–0.3 to +11.0
		IO1 max	I/O-1, I/O-2, O-3	0 to 10.0
	Maximum output current	IO2 max	DO, TGI1, TGI2, TGO, AOUT1, AOUT2	0 to 5.0	mA
		IO3 max	XBUF	0 to 3.0
	Allowable power dissipation	Pd max	(Ta ≤ 85°C)	SSOP30 :160	mW
	Operating temperature	Topr		–40 to +85	°C
	Storage temperature	Tstg		–55 to +125	°C

Note: Power must be applied to AVDD before applying to VDD and AVDD must be higher than or equal to VDD.

Allowable Operating Ranges at Ta = –40 to 85°C, VSS = AVSS = 0 V

Parameter	Symbol			Pin			Conditions		Ratings		Unit
								min	typ	max
	VDD1			VDD	VDD ≤ AVDD			4.5		5.5
Supply voltage	VDD2			AVDD	VDD ≤ AVDD			7.5	8.5	9.5	V
	VDD3			VDD	Serial data retention voltage			2.0
	VIH1			CE, CL, DI				0.7VDD		6.5
High-level input voltage	VIH2			I/O-1, I/O-2				0.7VDD		13	V
	VIH3			HCTR/I-3,				0.7VDD		VDD
				LCTR/I-4
				CE, CL, DI,
Low-level input voltage	VIL			I/O-1, I/O-2,				0		0.3VDD	V
				HCTR/I-3,
				LCTR/I-4
	VO1			DO				0		6.5
Output voltage	VO2			AOUT1				0		9.5	V
	VO3			I/O-1, I/O-2, O-3,				0		13
				AOUT2
	f	IN	1	XIN	V	IN	1 *1	7		11
	f	IN	2	FMIN	V	IN	2 *1	10		160
	f	IN	3	AMIN (SNS=1)	V	IN	3 *1	2		40	MHz
Input frequency	f	IN	4	AMIN (SNS=0)	V	IN	4 *1	0.5		10
	f	IN	5	HCTR/I-3	V	IN	5 *1	0.4		25
	f	IN	6	LCTR/I-4	V	IN	6 *1	10		500	kHz
	fIN7			LCTR/I-4	VIN7 *2			1.0		20 × 103	Hz

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LC72151V

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	Parameter	Symbol	Pin	Conditions		Ratings		Unit
					min	typ	max
		VIN1	XIN	fIN1	200		1500
		VIN2-1	FMIN	f = 10 to 50 MHz	40		1500
		VIN2-2	FMIN	f = 50 to 130 MHz	20		1500
		VIN2-3	FMIN	f = 130 to 160 MHz	40		1500
		VIN3	AMIN (SNS=1)	fIN3	40		1500
	Input amplitude	VIN4	AMIN (SNS=0)	fIN4	40		1500	mVrms
		VIN5-1	HCTR/I-3	f = 0.4 to 25 MHz *3	40		1500
		VIN5-2	HCTR/I-3	f = 8 to 12 MHz *4	70		1500
		VIN6-1	LCTR/I-4	f = 10 to 400 kHz *3	40		1500
		VIN6-2	LCTR/I-4	f = 400 to 500 kHz *3	20		1500
		VIN6-3	LCTR/I-4	f = 400 to 500 kHz *4	70		1500
	Guaranteed crystal oscillator	X’tal	XIN, XOUT	*5	10.25		10.35	MHz
	frequency ranges

Notes: 1. Sine wave with capacitor coupled.

2.Pulse wave with DC coupled.

3.Serial data: CTC = 0

4.Serial data: CTC = 1

5.Recomended CI value for the crystal oscillator: CI ≤ 70 Ω

Electrical Characteristics in the Allowable Operating Ranges

	Parameter	Symbol	Pin	Conditions		Ratings		Unit
					min	typ	max
		Rf1	XIN			1		MΩ
		Rf2	FMIN			500
	Internal feedback resistance	Rf3	AMIN			500		kΩ
		Rf4	HCTR/I-3			500
		Rf5	LCTR/I-4			500
	Internal pull-down resistance	Rpd1	FMIN		80	200	600	kΩ
		Rpd2	AMIN		80	200	600
	Hysteresis	VHIS	CE, CL, DI, LCTR/I-4			0.1 VDD		V
		VOH1	PDM1, PDM2, PDS, PDF	IO = – 1 mA	VDD – 1.0
	High-level output voltage			IO = – 2 mA	VDD – 2.0			V
		VOH2	AOUT1	IO = – 1 mA	AVDD – 1.0
		VOH3	XBUF	IO = – 0.5 mA	VDD – 1.5
		VOL1	PDM1, PDM2, PDS, PDF	IO = 1 mA			1.0
				IO = 2 mA			2.0
		VOL2	AOUT1	IO = 1 mA			1.0
		VOL3	XBUF	IO = 0.5 mA			1.5
	Low-level output voltage			IO = 1 mA			0.2	V
		VOL4	I/O-1, I/O-2, O-3	IO = 5 mA			1.0
				IO = 8 mA			1.6
		VOL5	DO	IO =1 mA			0.2
				IO = 5 mA			1.0
		VOL6	AOUT2	IO = 1 mA, AIN2 = 1.3 V			0.5
		IIH1	CE, CL, DI	VI = 6.5 V			5.0
		IIH2	I/O-1, I/O-2	VI = 13 V			5.0
		IIH3	HCTR/I-3, LCTR/I-4	VI = VDD			5.0	µA
	High-level input current	IIH4	XIN	VI = VDD	0.11		0.9
		IIH5	FMIN, AMIN, HCTR/I-3,	VI = VDD	1.8		15
			LCTR/I-4
		IIH6	AIN1, AREF	VI = 5.5 V		0.01	100	nA
		IIH7	TGI1, TGI2, TGO	VI = VDD			3.0	µA

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LC72151V

Continued from preceding page.

	Parameter	Symbol	Pin	Conditions		Ratings		Unit
					min	typ	max
		IIL1	CE, CL, DI	VI = 0 V			5.0
		IIL2	I/O-1, I/O-2	VI = 0 V			5.0
		IIL3	HCTR/I-3, LCTR/I-4	VI = 0 V			5.0	µA
	Low-level input current	IIL4	XIN	VI = 0 V	0.11		0.9
		IIL5	FMIN, AMIN, HCTR/I-3,	VI = 0 V	1.8		15
			LCTR/I-4
		IIL6	AIN1, AREF	VI = 0 V		0.01	100	nA
		IIL7	TGI1, TGI2, TGO	VI = 0 V			3.0	µA
				VIN = 8.5 V, I = ±3 mA,		70	140
				AVDD = 8.5 V
	Analog switch on resistance	RON	TGI1, TGI2, TGO	VIN = 4.5 V, I = ±3 mA,		50	100	Ω
				AVDD = 8.5 V
				VIN = 0.5 V, I = ±3 mA,		70	140
				AVDD = 8.5 V
		IOFF1	AOUT1	VO = 6.5 V			5.0
	Output off leakage current	IOFF2	I/O-1, I/O-2, O-3, AOUT2	VO = 13 V			5.0	µA
		IOFF3	DO	VO = 6.5 V			5.0
	High-level 3-state off leakage current	IOFFH	PDM1, PDM2, PDS, PDF	VO = VDD		0.01	200	nA
	Low-level 3-state off leakage current	IOFFL	PDM1, PDM2, PDS, PDF	VO = 0 V		0.01	200	nA
	Input capacitance	CIN	FMIN			6		pF
				X’tal = 10.35 MHz
		IDD1	VDD	fIN2 = 160 MHz		10	18
				VIN2 = 40 mVrms
				PLL block stopped
		IDD2	VDD	(PLL INHIBIT)		0.5	1.5
				X’tal OSC operating				mA
	Supply current			(X’tal = 10.35 MHz)
				PLL block stopped
		IDD3	AVDD	(PLL INHIBIT)			1.5
				X’tal OSC stopped
				On-chip op-amp stopped
				PLL block stopped
		IDD4	VDD	(PLL INHIBIT)			10	µA
				X’tal OSC stopped
				On-chip op-amp stopped

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LC72151V

Pin Functions

Pin No.

Symbol

Usage

Function

Pin circuit

30

XIN

X’tal OSC

•

Crystal oscillator connection.

1

XOUT

(10.25 or 10.35 MHz)

•

FMIN is selected by setting DVS in the control data to 1.

•

Enters high-speed locking mode by setting SNS in the control data

to 1.

8

FMIN

Local oscillator signal input

•

Enters normal mode by setting SNS in the control data to 0.

• Input frequency: 10 to 160 MHz

•

The signal is transmitted to the swallow counter.

•

The divisor can be set to a value in the range 272 to 65,535.

•

AMIN is selected by setting DVS in the control data to 0.

•

When SNS in the control data is set to 1:

Input frequency: 2 to 40 MHz

9

AMIN

Local oscillator signal input

The signal is directly transmitted to the swallow counter.

•

When SNS in the control data is set to 0:

Input frequency: 0.5 to 10 MHz

The signal is directly transmitted to the 12-bit programmable divider.

The divisor can be set to a value in the range 5 to 4,095.

29

CE

Chip enable

•

This pin must be set to the high level when inputting serial data to the

S

LC72151V DI pin and when outputting serial data from the DO pin.

28

DI

Input data

• Serial data input for transferring data from the controller to the

S

LC72151V.

27

CL

Clock

•

Data synchronization clock signal used when inputting serial data to

S

the LC72151V DI pin and when outputting serial data from the DO pin.

26

DO

Output data

• Serial data output for transferring data from the LC72151V to the

controller.

• LC72151V power supply. A voltage in the range 4.5 to 5.5 V must be

provided when the PLL circuit is operating.

6

VDD

Power

•

The power-on reset circuit operates when power is first applied.

———

Note: Power must be applied to AVDD before applied to VDD and

AVDD must be higher than or equal to VDD.

7

VSS

Ground

• LC72151V ground.

———

•

Input/output dual function pins

• The function will be selected according to IOC1 and IOC2 in the

control data.

Data = 0: Input port

1: Output port

•

When specified as an input port:

The input pin state is transmitted to the system microcontroller from

2

I/O-1

I/O ports

DO pin.

3

I/O-2

Input state = Low: data is 0

= High: data is 1.

•

When specified as an output port:

The output state will be determined according to I/O-1 and I/O-2 in

the control data.

Data = 0: Low

= 1: Open

•

These pin function as an input port at a power-on reset.

Continued on next page.

No. 6976-7/29

LC72151V

Continued from preceding page.

Pin No.

Symbol

Usage

Function

Pin circuit

•

Dedicated output pin

5

O-3

Output port

• Latches OUT3 in the control data and outputs data from O-3 pin.

•

This pin goes open state at a power-on reset.

19

AIN1

•

Op-amp for PLL active low-pass filter

AVDD

• AVSS is the analog system ground pin shared with low-pass filter Nch

12

AREF

AIN1

13

AVDD

Op-amp for low-pass filter amp

MOS transistor.

–

•

Voltage applied to AREF pin must be 1/2 that to VDD pin.

+

14

AVSS

AOUT1

Note: Power must be applied to AVDD before applied to VDD, and AVDD

AREF

15

AOUT1

must be higher than or equal to VDD.

AVSS

24

AIN2

•

PLL active low-pass filter Nch MOS transistor

Transistor for low-pass

•

Source of the transistor is connected to AVSS pin.

25

AOUT2

filter amp

Note: Connect AVSS pin to ground in use.

AVSS

21

PDM1

• PLL charge pump output

When the frequency created by dividing the local oscillator signal

23

PDM2

Charge pump output

frequency by N is higher than the reference frequency, a high level is

20

PDS

output from the PD pin. When lower, a low level is output. The PD pin

goes to the high-impedance state when the frequencies match.

• PLL high-speed locking charge pump output

22

PDF

PLL high-speed locking charge

When the high-speed locking mode is selected, signal pulses is

pump output

output according to the frequency variation. This pin enters high-

impedance state when the local oscillation frequency enters the set

frequency range.

18

TGI1

• PLL high-speed locking active low-pass filter transmission gate

TGI1

TGO

17

TGI2

PLL high-speed locking TG

input/output dual function pins

TGI2

16

TGO

Note: Connect AVSS pin to ground in use.

•

HCTR is selected by setting CTS1 in the control data to 1.

Input frequency: 0.4 to 25 MHz

The signal is input to a divide-by-2 circuit and the result is input to a

general-purpose counter. This counter can also be used as an

10

HCTR/I-3

General-purpose counter

integrating counter.

The counter value is output as the result of the count, MSB first, from

the DO pin.

There are four measurement periods: 4, 8, 32, and 64 ms.

• When H/I-3 in the control data is set, this pin functions as an input

port, and the value is output from the output pin DO.

•

LCTR is selected by setting CTS1 in the control data to 1.

• When the LCTR is selected as described above and CTS0 is set to 1:

This pin enters the frequency measurement mode.

Input frequency: 10 to 500 kHz

The signal is directly transmitted to the general-purpose counter.

• When CTS0 is set to 0

This pin enters period measurement mode.

11

LCTR/I-4

General-purpose counter

Input frequency: 1 Hz to 20 kHz

Period can be measured either in single period or in double period. If

double period measurement is selected, the frequency is 2 Hz to

40 kHz.

The counter value is output as the result of the count, MSB first, from

the DO pin.

•

When L/I-4 in the control data is set:

This pin functions as an input port, the value is output from the output

pin DO.

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LC72151V

Continued from preceding page.

Pin No.

Symbol

Usage

Function

Pin circuit

•

Output buffer for the crystal oscillator circuit

XOUT

•

When XB in the serial data is set to 1, the output buffer operates and

4

XBUF

Crystal oscillator buffer

the crystal oscillator signal (a pulse signal) is output.

When XB is 0, XBUF outputs a low level.

After the power-on reset, the output buffer is fixed at the low level.

Serial Data I/O Methods

Data is input to and output from the LC72151V using the Sanyo CCB (Computer Control Bus) format, which is the serial bus format used by SANYO audio ICs. This IC adopts a CCB format with an 8-bit address.

		I/O mode				Address					Content
			B0	B1	B2	B3	A0	A1	A2	A3
											• Control data input (serial input) mode.
	[1]	IN1 (82)	0	0	0	1	0	1	0	0	• 32 bits of data are input.
											• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
											the input data.
											• Control data input (serial input) mode.
	[2]	IN2 (92)	1	0	0	1	0	1	0	0	• 32 bits of data are input.
											• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
											the input data.
											• Data output (serial data output) mode.
	[3]	OUT (A2)	0	1	0	1	0	1	0	0	• The number of bits output is equal to the number of clock cycles.
											• See the “DO Output Data (Serial Data Output) Structure” item for details on the content
											of the output data.

								I/O mode determined
CE
	1
CL
	2
DI	B0	B1	B2	B3	A0	A1	A2	A3
								First Data IN1/2
	1
DO								First Data OUT
	2

First Data OUT

1CL: Normally Hi

2CL: Normally Low

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