Sanyo LC72146V Specifications

Ordering number : ENN4922D

CMOS IC

LC72146, 72146M, 72146V

PLL Frequency Synthesizer

for Electronic Tuning

Overview

The LC72146 is a PLL frequency synthesizer LSI circuit for electronic tuning in car stereo systems. The LC72146 supports the construction of high-performance, multifunctional electronic tuning systems for the VHF MW, and LW bands.

Features

•High-speed programmable dividers for

—10 to 160 MHz on FMIN using pulse swallower

—0.5 to 40.0 MHz on AMIN using pulse swallower and direct division

•General-purpose counters

—HCTR for 0.4 to 25.0 MHz frequency measurement

—LCTR for 10 to 500 kHz frequency measurement and 1.0 Hz to 20 × 103 kHz period measurement

•Reference frequencies: Twelve selectable reference frequencies (4.5 or 7.2 MHz crystal) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 25, 30, 50 and 100 kHz

•Phase comparator

—Insensitive band control

—Unlock detection

—Sub-charge pump for high-speed locking

—Deadlock clear circuit

•CCB input/output data interface

•Power-on reset circuit

•Built-in MOS transistor for a low-pass filter

•Inputs/outputs (using five general-purpose input/output ports)

—Maximum of seven inputs (max)

—Maximum of seven outputs (max/four n-channel open-drain and three CMOS outputs)

—Time-base output for clock (8 Hz)

•Operating ranges

—Supply voltage ..................................4.5 to 5.5 V

—Opetating temperature ......................–40 to 85°C

•Package

—DIP24S, MFP24S, SSOP24

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

N2001TN (OT)/73096HA (OT)/11095TH (OT) No. 4922-1/22

LC72146, 72146M, 72146V

Package Dimensions

unit: mm

unit: mm

3067A-DIP24S					3112A-MFP24S
			[LC72146]
		21.0
	24		13		24
			7.62	6.4	0.25
	1		12
	0.9				1
			(3.25)	3.9max
(0.71)	1.78	0.48	0.51min	3.3
			0.95
				SANYO: DIP24S

unit: mm

3175B-SSOP24

[LC72146V]

[LC72146M]

13

5.4

7.6

12.5	12	1.7max	0.15	0.63
		1.5
	1.0	0.1
0.35		(0.75)

SANYO: MFP24S

SANYO: SSOP24

No. 4922-2/22

LC72146, 72146M, 72146V

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter	Symbol	Conditions	Ratings	Unit
Maximum supply voltage	VDD max	VDD	–0.3 to +7.0	V
	VIN1 max	CE, CL, DI	–0.3 to +7.0	V
Maximum input voltage	VIN2 max	XIN, FMIN, AIN, AMIN, HCTR/I-6, LCTR/I-7, I/O-4, I/O-5	–0.3 to VDD + 0.3	V
	VIN3 max	I/O-1 to I/O-3	–0.3 to +15	V
	VO1 max	DO	–0.3 to +7.0	V
Maximum output voltage	VO2 max	XOUT, I/O-4, I/O-5, O-6, PD0, PF1, AIN	–0.3 to VDD + 0.3	V
	VO3 max	I/O-1 to I/O-3, AOUT, O-7	–0.3 to +15	V
	IO1 max	I/O-4, I/O-5, O-6, O-7	0 to 3.0	mA
Maximum output current	IO2 max	DO, AOUT	0 to 6.0	mA
	IO3 max	I/O-1 to I/O-3	0 to 10	mA
		DIP24S:Ta ≤ 85°C	350	mW
Allowable power dissipation	Pd max	MFP24S:Ta ≤ 85°C	220	mW
		SSOP24:Ta ≤ 85°C	150	mW
Operating temperature	Topr		–40 to +85	°C
Storage temperature	Tstg		–55 to +125	°C

Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V

Parameter	Symbol	Conditions	min	typ	max	Unit
Supply voltage	VDD1	VDD	4.5		5.5	V
	VDD2	VDD: Serial data retain voltage	2.0			V
Input high-level voltage	VIH1	CE, CL, DI, I/O-1 to I/O-3	2.2		6.5	V
	VIH2	I/O-4, I/O-5, HCTR/I-6 and LCTR/I-7	2.2		VDD	V
Input low-level voltage	VIL1	CE, CL, DI and I/O-1 to I/O-5, HCTR/I-6, LCTR/I-7	0		0.8	V
Input high-leve lvoltage	VIH3	LCTR/I-7, Pulse wave*1	2.2		VDD	V
Input low-level voltage	VIL2	LCTR/I-7, Pulse wave*1	0		0.8	V
Output voltage	VO1	DO	0		6.5	V
	VO2	I/O-1 to I/O-3, AOUT, O-7	0		13	V
	fIN1	XIN; Sine wave, capacitive coupling	1.0		8.0	MHz
	fIN2	FMIN; Sine wave, capacitive coupling	10		160	MHz
Input frequency	fIN3	AMIN; Sine wave, capacitive coupling	0.5		40	MHz
	fIN4	HCTR/I-6; Sine wave, capacitive coupling	0.4		25	MHz
	fIN5	LCTR/I-7; Sine wave, capacitive coupling	10		500	kHz
	f 6	LCTR/I-7; Pulse wave, DC coupling*1	1.0		20 × 103	Hz
	IN
Guaranteed oscillator	Xtal	XIN, XOUT *2	4.0		8.0	MHz
element frequencies
	VIN1	XIN	200		1500	mVrms
	VIN2-1	FMIN; 50 ≤ f < 130 MHz*3	40		1500	mVrms
	VIN2-2	FMIN; 10 ≤ f < 50 MHz*3, 130 ≤ f 160 MHz	70		1500	mVrms
	VIN3-1	AMIN; 2 ≤ f < 25 MHz*3	40		1500	mVrms
	VIN3-2	AMIN; 25 ≤ f < 40 MHz*3	70		1500	mVrms
Input amplitude	VIN3-3	AMIN; 0.5 ≤ f < 2.5 MHz*3	40		1500	mVrms
	VIN3-4	AMIN; 2.5 ≤ f < 10 MHz*3	70		1500	mVrms
	VIN4-1	HCTR/I-6; 0.4 ≤ f < 25 MHz*4	40		1500	mVrms
	VIN4-2	HCTR/I-6; 8 ≤ f < 12 MHz*5	70		1500	mVrms
	VIN5-1	LCTR/I-7; 10 ≤ f < 400 kHz*4	40		1500	mVrms
	VIN5-2	LCTR/I-7; 400 ≤ f < 500 kHz*4	20		1500	mVrms
	VIN5-3	LCTR/I-7; 400 ≤ f < 500 kHz*5	70		1500	mVrms
Data set up time	t	DI, CL*6	0.45			µS
	SU
Data hold time	tHD	DI, CL*6	0.45			µS

Continued on next page.

No. 4922-3/22

LC72146, 72146M, 72146V

Continued from preceding page.

Parameter	Symbol		Conditions	min	typ	max	Unit
Clock low-level time	t	CL	CL*5	0.45			µs
Clock high-level time	t	CH	CL*5	0.45			µs
CE wait time	t		CE, CL*5	0.45			µs
		EL
CE setup time	tES		CL, CE*5	0.45			µs
CE hold time	t		CE, CL*5	0.45			µs
		EH
Chip enable to data latch time	tLC		*5			0.45	µs
Data output time	tDC		DO, CL; Depends on pull-up resistor			0.2	µs

Note: 1. Period measurement

2.Recommended crystal oscillator CI values: CI ≤ 120 Ω (For a 4.5 MHz crystal)

CI ≤ 70 Ω (For a 7.2 MHz crystal)

3.See the description of the structure of the programmable divider.

4.With the CTC bit in the serial data set to 0

5.With the CTC bit in the serial data set to 1

6.See the description of the serial data timing.

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V

Parameter	Symbol	Conditions		min	typ	max	Unit
	Rf1	XIN			1.0		MΩ
	Rf2	FMIN			500		kΩ
Internal feedback resistance	Rf3	AMIN			500		kΩ
	Rf4	HCTR/I-6			250		kΩ
	Rf5	LCTR/I-7			250		kΩ
Sub charge pump	R1S	AIN			100		Ω
internal resistance
Hysteresis	VHIS	CE, CL, DI, LCTR/I-7			0.1 VDD		V
			IO = 0.5 mA	VDD – 0.5			V
Output high-level voltage	VOH1	PD0, PD1, I/O-4, I/O-5, O-6	IO = 1 mA	VDD – 1.0			V
			IO = 2 mA	VDD – 2.0			V
	VOH2	AIN: IO = 1 mA		VDD – 0.6	VDD – 0.3		V
		PD0, PD1, I/O-4,	IO = 0.5 mA			0.5	V
	VOL1		IO = 1 mA			1.0	V
		I/O-5, O-6, O-7
			IO = 2 mA			2.0	V
	VOL2	AIN: IO = 1 mA			0.3	0.6	V
Output low-level voltage			IO = 1 mA			0.2	V
	VOL3	I/O-1 to I/O-3	IO = 2.5 mA			0.5	V
			IO = 5 mA			1.0	V
			IO = 9 mA			1.8	V
	VOL4	DO; IO = 5 mA				1.0	V
	VOL5	AOUT; IO = 1 mA, AIN = 1.3 V				0.5	V
	IIH1	CE, CL, DI; VI = 6.5 V				5.0	µA
	IIH2	I/O-1 to I/O-3; VI = 13 V				5.0	µA
Input high-level current	IIH3	I/O-4, I/O-5, HCTR/I-6, LCTR/I-7; VI = VDD				5.0	µA
	IIH4
		XIN; VI = VDD		2.0		11	µA
	IIH5	FMIN, AMIN; VI = VDD		4.0		22	µA
	IIH6	HCTR/I-6, LCTR/I-7; VI = VDD		8.0		44	µA
	IIL1	CE, CL, DI; VI = 0 V				5.0	µA
	IIL2	I/O-1 to I/O5; VI = 0 V				5.0	µA
Input low-level current	IIL3	HCTR/I-6, LCTR/I-7; VI = 0 V				5.0	µA
	IIL4	XIN; VI = 0 V		2.0		11	µA
	IIL5	FMIN, AMIN; VI = 0 V		4.0		22	µA
	IIL6	HCTR/I-6, LCTR/I-7; VI = 0 V		8.0		44	µA

Continued on next page.

No. 4922-4/22

LC72146, 72146M, 72146V

Continued from preceding page.

Parameter	Symbol	Conditions	min	typ	max	Unit
Output off leakage current	IOFF1	I/O-1 to I/O3, AOUT, O-7; VO = 13 V			5.0	µA
	IOFF2	DO; VO = 6.5 V			5.0	µA
High-level three state	IOFFH	PD0, PD1, AIN; VO = VDD		0.01	200	nA
off leakage current
Lowh-level three state	IOFFL	PD0, PD1, AIN; VO = 0 V		0.01	200	nA
off leakage current
Input cacitance	CIN	FMIN		6		pF
Pull-down transistor	Rpd1	FMIN	80	200	600	kΩ
on resistance	Rpd2	AMIN	80	200	600	kΩ
		VDD; Xtal = 7.2 MHz, fIN2 = 160 MHz,
	IDD1	VIN2 = 70 mVrms, fIN4 = 25 MHz		10	15	mA
Supply current		VIN4 = 40 mVrms
	IDD2	VDD; PLL inhibited,		0.5	1.5	mA
		crystal oscillator running (Xtal = 7.2 MHz)
	IDD3	VDD; PLL inhibited, crystal oscillator stoped			10	µA

Pin Assignment

	XIN		V		AOUT		AIN		PD0		PD1		V		FMIN		AMIN		V		HCTR/I-6		LCTR/I-7
			SS										SS						DD
	24		23		22		21		20		19		18		17		16		15		14		13

LC72146, 72146M, 72146V

Top View

1 2 3 4 5 6 7 8 9 10 11 12

XOUT

CE

DI

CL

DO

O-7

O-6

I/O-5

I/O-4

I/O-3

I/O-2

I/O-1

Block Diagram

									19	PD1
XIN 24			REFERENCE					PHASE DETECTOR	20 PD0
			DIVIDER					CHARGE PUMP
XOUT	1
FMIN	17		SWALLOW COUNTER						14	HCTR/I-6
			1/16, 1/17, 4bits
VSS	18
AMIN	16		12bits PROGRAMMABLE						13	LCTR/I-7
				DIVIDER
CE	2							UNIVERSAL
DI	3							COUNTER	21	AIN
		CCB	DATA SHIFT REGISTER
		I/F		LATCH
CL	4								22	AOUT
DO	5
VDD	15	POWER
		ON
		RESET
VSS	23
		12	11	10	9	8	7	6
		I/O-1	I/O-2	I/O-3	I/O-4	I/O-5	O-6	O-7
										No. 4922-5/22

LC72146, 72146M, 72146V

Pin Functions

Number

Symbol

Type

Function

Equivalent circuit

24

XIN

Xtal OSC

Connection for crystal oscillator element (7.2 or 4.5 MHz)

1

XOUT

•

Serial data input: FMIN is selected when DVS is set to 1.

17

FMIN

Local oscillator

Input frequency range: 10 to 160 MHz

signal input

•

The signal is transmitted directly to the swallow counter

•

Divisor value range: 272 to 65535

•

Serial data input: AMIN is selected when DVS is set to 0.

•

Serial data input: when SNS is set to 1.

• Input frequency range: 2 to 40 MHz

•

The signal is transmitted directly to the swallow counter.

16

AMIN

Local oscillator

•

Divisor value range: 272 to 65535

signal input

•

Serial data input: when SNS is set to 0.

• Input frequency range: 0.5 to 10 MHz

•

The signal is transmitted directly to the 12-bit

programmable divider.

•

Divisor value range: 4 to 4095

2

CE

Chip enable

•

This pin must be set high to input serial data to the

S

LC72146 DI pin or to output serial data from the DO pin.

•

Inputs the clock used for data synchronization when

4

CL

Clock

inputting serial data to the LC72146 DI pin or outputting

S

serial data from the DO pin.

3

DI

Input data

•

Input pin for serial data transmitted to the LC72146 from

S

a controller.

5

DO

Output data

•

Output pin for serial data transmitted from the LC72146 to

a controller.

• The LC72146 power supply connection. A voltage

15

VDD

Power supply

between 4.5 and 5.5 volts must be supplied when the

PLL circuit is used.

•

The power on reset circuit operates when power is first

applied.

18

VDD

Ground

• The LC72146 ground connection.

23

12

•

General-purpose I/O ports

I/O-1

•

Output mode circuit type: open drain

11

General-purpose

I/O-2

•

Function after a power on reset: input port

10

I/O port

I/O-3

•

Can be set up to function as output ports by bits I/O-1 to

I/O-3 in the serial data sent from the controller.

Continued on next page.

No. 4922-6/22

LC72146, 72146M, 72146V

Continued from preceding page.

Number

Symbol

Type

Function

Equivalent circuit

• General-purpose I/O ports

9

I/O-4

General-purpose

• Output mode circuit type: complementary

• Function after a power on reset: input port

8

I/O-5

I/O port

• Can be set up to function as output ports by bits I/O-4

and I/O-5 in the serial data sent from the controller.

7

O-6

Output port

• The LC72146 latches the OUT6 bit in the serial data and

outputs it from pin O-6.

• The LC72146 latches the OUT7 bit in the serial data and

6

O-7

Output port

outputs it from pin O-7.

• Outputs a time base signal (8 Hz) when TBC is set to 1.

•

Function after a power on reset: open circuit

• PLL charge pump output pin

If the frequency generated by dividing the local oscillator

20

PD0

Charge pump

frequency by N is higher than the reference frequency, a

19

PD1

output

high level will be output from PD0, and if it is lower, a low

level will be output. PD0 goes to the high-impedance

state when the frequencies match.

•

PD1 operates identically.

• Connections to the n-channel MOS transistor used for

Connections for the

the PLL active low-pass filter.

21

AIN

•

A high-speed locking circuit can be formed by using

22

AOUT

low-pass filter

these pins with the built-in sub charge pump.

transistor

• See the item on the structure of the charge pump for

details.

• HCTR is selected when CTS1 is set to 1.

• Input frequency range: 0.4 to 25 MHz

•

The signal is passed through a divide-by-two circuit and

then input to a general-purpose counter. This input also

supports an integrating count function.

14

HCTR/I-6

General-purpose

•

The result is output from the DO output pin starting with

counter

the MSB of the general-purpose counter.

•

See the item on the structure of the general-purpose

counter for details.

•

When the H/I-6 bit in the serial data is set to 0:

•

This pin functions as an input port, and the value input is

output from the DO pin.

Continued on next page.

No. 4922-7/22