SANYO LC72134M Datasheet

Overview

The LC72134M is a dual PLL frequency synthesizer product that integrates on a single chip both an AM/FM audio broadcast reception PLL circuit (main PLL) and a dedicated FM multiplex reception PLL circuit (sub PLL). Since the main PLL circuit is equivalent to the LC72135M, software developed for that product can be used with this chip. The sub-PLL circuit can be controlled independently.

Functions

• High-speed programmable divider — FMINa (main): 10 to 160 MHz ... Pulse swallower

technique (With built-in divide-by-2 prescaler)

— FMINb (sub): 10 to 160 MHz ... Pulse swallower

technique (With built-in divide-by-2 prescaler)

— AMIN (main): 0.5 to 40 MHz ... Pulse swallower

and direct division techniques

• IF counter — Two input pins provided: IFIN1 and IFIN2 — IFIN1: 0.4 to 25 MHz ... For AM and FM IF

counting

— IFIN2: 0.4 to 25 MHz ... For AM and FM IF

counting

• Reference frequency — One of 12 reference frequencies can be selected

(using a 4.5 or 7.2 MHz crystal element) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5*, 15*, 25*, 50*, or 100 kHz *: Sub PLL reference frequencies

• Phase comparator — Supports dead zone control. — Built-in unlocked state detection circuit — Built-in deadlock clear circuit

• An MOS transistor for an active low-pass filter is built in.

• I/O ports — Output-only ports: 4 pins — I/O ports: 1 pin — Input-only ports: 1 pin (function shared with the

IFIN2 pin)

— Supports the output of an 8-Hz clock time base

signal.

• CCB interface used for data I/O. — The main PLL is compatible with the LC72135M. — The sub PLL can be controlled at an independent

address.

• Operating ranges — Supply voltage: 4.5 to 5.5 V — Operating temperature: –40 to 85°C

• Package: MFP24S

Package Dimensions

unit: mm

3112-MFP24S

CMOS IC

41098RM (OT) No. 5814-1/27

SANYO: MFP24S

[LC72134M]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Dual PLL Frequency Synthesizer

for FM Tuner Systems

LC72134M

Ordering number : EN5814

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

This product supports the Sanyo-original CCB bus format.

Pin Assignments

No. 5814-2/27

LC72134M

No. 5814-3/27

LC72134M

Block Diagram

No. 5814-4/27

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Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max V

–0.3 to +7.0 V

1 max CE, DI, CL, AINa, AINb –0.3 to +7.0 V

Maximum input voltage V

2 max XIN, FMINa, FMINb, AMIN, IFIN1, IFIN2/I1 –0.3 to VDD+0.3 V

3 max IO2 –0.3 to +15 V

1 max DO –0.3 to +7.0 V

Maximum output voltage V

2 max XOUT, PDa, PDb –0.3 to VDD+0.3 V

3 max BO1 to BO4, IO2, AOUTa, AOUTb –0.3 to +15 V

1 max BO1 0 to +3.0 mA

Maximum output current I

2 max DO, AOUTa, AOUTb 0 to +6.0 mA

3 max BO2 to BO4, IO2 0 to +10.0 mA Allowable power dissipation Pd max Ta ≤ 85°C 200 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DDVDD

4.5 5.5 V

1 CE, DI, CL 0.7 V

6.5 V

Input high-level voltage V

2 IFIN2/I1 0.7 V

3 IO2 0.7 V

13 V

Input low-level voltage V

CE, DI, CL, IO2, IFIN2/I1 0 0.3 V

Output voltage

1 DO 0 6.5 V

2 BO1 to BO4, IO2, AOUTa, AOUTb 0 13 V

1 XIN: VIN1 1 8 MHz

2 FMINa, FMINb: VIN2 10 160 MHz

Input frequency f

3 AMIN: VIN3, SNS = 1 2 40 MHz

4 AMIN: VIN4, SNS = 0 0.5 10 MHz

5 IFIN1, IFIN2/I1: VIN5 0.4 25 MHz

1 XIN: fIN1 400 1500 mVrms

2-1 FMINa, FMINb: f = 10 to 130 MHz 40 1500 mVrms

2-2 FMINa, FMINb: f = 130 to 160 MHz 70 1500 mVrms

Input amplitude V

3 AMIN: fIN3, SNS = 1 40 1500 mVrms

4 AMIN: fIN4, SNS = 0 40 1500 mVrms

5 IFIN1, IFIN2/I1: f = 0.4 to 25 MHz, IFS = 1 70 1500 mVrms

6 IFIN1, IFIN2/I1: f = 0.4 to 12 MHz, IFS = 0 100 1500 mVrms

Guaranteed crystal oscillator frequency Xtal XIN, XOUT: *1 4.0 8.0 MHz

Allowable Operating Ranges at Ta = –40 to 85°C, VSS= 0 V

Note: Recommended value for CI for the crystal oscillator element: CI ≤ 120 Ω (4.5 MHz) or CI ≤ 70 Ω (7.2 MHz)

However, since the oscillator circuit characteristics depend on the printed circuit board, circuit constants, and other factors, consult with the manufacturer of the crystal element.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Rf1 XIN 1.0 MΩ

Internal feedback resistance

Rf2 FMINa, FMINb 500 kΩ Rf3 AMIN 500 kΩ Rf4 IFIN1, IFIN2/I1 250 kΩ

Internal pull-down resistance

Rpd1 FMINa, FMINb 200 kΩ Rpd2 AMIN 200 kΩ

Hysteresis V

HIS

CE, DI, CL, IO2, IFIN2/II 0.1 V

Output high-level voltage V

1 PDa, PDb: IO= –1 mA VDD– 1.0 V

Electrical Characteristics in the Allowable Operating Ranges

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Parameter Symbol Conditions

Ratings

Unit

min typ max

1 PDa, PDb: IO= 1 mA 1.0 V

BO1: I

= 0.5 mA 0.5 V

BO1: I

= 1 mA 1.0 V

DO: I

= 1 mA 0.2 V

Output low-level voltage DO: I

= 5 mA 1.0 V

BO2 to BO4, IO2: I

= 1 mA 0.2 V

4 BO2 to BO4, IO2: IO= 5 mA 1.0 V

BO2 to BO4, IO2: I

= 8 mA 1.6 V

5 AOUTa, AOUTb: IO= 1 mA, AIN = 1.3 V 0.5 V

1 CE, DI, CL: VI= 6.5 V 5.0 µA

2 IFIN2/I1: VI= VDD, L/I1 = 0 5.0 µA

3 IO2: VI= 13 V 5.0 µA

Input high-level current I

4 XIN: VI= V

2.0 11 µA

5 FMINa, FMINb, AMIN: VI= V

4.0 22 µA

6 IFIN1, IFIN2/I1: VI= V

8.0 44 µA

7 AINa, AINb: VI= 6.5 V 200 nA

1 CE, DI, CL: VI= 0 V 5.0 µA

2 IFIN2/I1: VI= 0 V, L/I1 = 0 5.0 µA

3 IO2: VI= 0 V 5.0 µA

Input low-level current I

4 XIN: VI= 0 V 2.0 11 µA

5 FMINa, FMINb, AMIN: VI= 0 V 4.0 22 µA

6 IFIN1, IFIN2/I1: VI= 0 V 8.0 44 µA

7 AINa, AINb: VI= 0 V 200 nA

Output off leakage current

OFF

1 BO1 to BO4, AOUTa, AOUTb, IO2: VO= 13 V 5.0 µA

OFF

2 DO: VO= 6.5 V 5.0 µA

High-level 3-state off leakage current I

OFFH

PDa, PDb: VO= V

0.01 200 nA

Low-level 3-state off leakage current I

OFFL

PDa, PDb: VO= 0 V 0.01 200 nA

Input capacitance C

FMINa, FMINb 6 pF

: Crystal = 7.2 MHz, fIN2 = 130 MHz

5 10 mA

(FMINa operating), V

2 = 40 mV rms

: Crystal = 7.2 MHz, fIN2 = 130 MHz

2 (FMINa and FMINb operating), 8 16 mA

Current drain

2 = 40 mV rms

: PLL block stopped (PLL INHIBIT mode)

3 Crystal oscillator operating 0.5 mA

(crystal frequency: 7.2 MHz)

: PLL block stopped, crystal oscillator

10 µA

stopped

Continued from preceding page.

Pin Descriptions

Pin Pin No. Type Function Equivalent circuit

Xtal • Crystal oscillator element connections (4.5 or 7.2 MHz)

XIN

XOUT

Main PLL local oscillator signal input

• FMINa is selected when DVS in the serial data is set to 1.

• Input frequency: 10 to 160 MHz

• The signal is passed through an internal divide-by-two prescaler and then input to the swallow counter.

• The divisor can be set to a value in the range 272 to 65535. Since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value.

FMINa 18

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Continued from preceding page.

Pin Pin No. Type Function Equivalent circuit

Main PLL local oscillator signal input

• AMIN is selected when DVS in the serial data is set to 0.

• When SNS in the serial data is set to 1:

• Input frequency: 2 to 40 MHz

• The signal is input to the swallow counter directly.

• The divisor can be set to a value in the range 272 to 65535. The set value

becomes the actual divisor.

• When SNS in the serial data is set to 0:

• Input frequency: 0.5 to 10 MHz

• The signal is input to a 12-bit programmable divider directly.

• The divisor can be set to a value in the range 5 to 4095. The set value becomes

the actual divisor.

AMIN 17

Chip enable

• This pin must be set high to enable serial data input (DI) or serial data output (DO).

CE 2

Input data • Input for serial data transferred from the controllerDI 3

Clock

• Clock used for data synchronization for serial data input (DI) and serial data output (DO).

CL 4

Output data

• Output for serial data transmitted to the controller. The content of the data transmitted is determined by DOC0 through DOC2.

DO 5

Power supply

• LC72134M power supply (V

= 4.5 to 5.5 V)

• The power on reset circuit operates when power is first applied.

——

Ground • LC72134M ground ——

Output ports

• Output-only ports

• The output state is determined by BO1 through BO4 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level.

• A time base signal (8 Hz) is output from BO1 when TBC in the serial data is set to

BO1 BO2 BO3 BO4

6 7 8

I/O port

• Shared function I/O port

• The pin function is determined by IOC2 in the serial data. When the data value = 0: Input port When the data value = 1: Output port

• When specified to function as an input port: The input pin state is reported to the controller through the DO pin. When the input state is low: The data will be 0: When the input state is high: The data will be 1:

• When specified to function as an output port: The output state is determined by IO2 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level.

• This pin is set to input mode after a power on reset.

IO2 16

Main PLL charge pump output

• PLL charge pump output A high level is output when the frequency of the local oscillator signal divided by N is higher than the reference frequency, and a low level is output when that frequency is lower. This pin goes to the high-impedance state when the frequencies match.

PDa 20

Main PLL lowpass filter amplifier transistor

• Connections for the n-channel MOS transistor to be used for the PLL active lowpass filter.

AINa

AOUTa2122

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Pin Pin No. Type Function Equivalent circuit

IF counter 1

• IFIN1 is selected when LCTS in the serial data is set to 0.

• The input frequency range is 0.4 to 25 MHz when IFS is 1, and 0.4 to 12 MHz when IFS is 0.

• The signal is passed directly to the IF counter.

• The result is output, MSB first, through the DO pin.

• Four measurement periods are supported: 4, 8, 32, and 64 ms.

IFIN1 15

IF counter 2 input port

• IFIN2 is selected when both LCTS and L/I1 in the serial data are set to 1.

• The input frequency range is 0.4 to 25 MHz when IFS is 1 and 0.4 to 12 MHz when IFS is 0.

• The signal is passed directly to the IF counter.

• The result (the IF counter value) is output, MSB first, through the DO pin.

• Four measurement periods are supported: 4, 8, 32, and 64 ms.

• If the L/I1 bit in the serial data is set to 0, the IFIN2/I1 port will function as an input port and the state of the input pin will be reported to the microcontroller from the DO pin. (Note that the LCTS value is ignored in this case.) When the input state is low: the data will be 0: When the input state is high: the data will be 1:

IFIN2/I1 13

Sub PLL local oscillator signal input

• FMINb is selected when SDVS in the serial data is set to 1.

• The input frequency range is 10 to 160 MHz.

• The signal is passed through an internal divide-by-two prescaler and then input to the swallow counter.

• The divisor can be set to a value in the range 272 to 8191. Since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value.

• FMINb goes to the stopped state (pulled down) when SDVS in the serial data is set to 0.

FMINb 12

Sub PLL charge pump output

• Sub PLL charge pump output A high level is output from the PD pin when the frequency of the local oscillator signal divided by N is higher than the reference frequency, and a low level is output when that frequency is lower. This pin goes to the high-impedance state when the frequencies match.

PDb 11

Sub PLL lowpass filter amplifier transistor

• Connections for the n-channel MOS transistor used for the sub PLL active lowpass filter.

AINb

AOUTb

Procedures for Input and Output of Serial Data

This product uses the CCB (Computer Control Bus), which is Sanyo’s audio product serial bus format, for data input and output. This product adopts an 8-bit address CCB format.

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I/O mode

Address

Function

B0 B1 B2 B3 A0 A1 A2 A3

• Control data input (serial data input) mode

1 IN1 (82) 0 0 0 1 0 1 0 0

• 24 bits of data are input.

• See the “DI Control Data (serial data input)” section for details on the content of the input data.

• Control data input (serial data input) mode

2 IN2 (92) 1 0 0 1 0 1 0 0

• 24 bits of data are input.

• See the “DI Control Data (serial data input)” section for details on the content of the input data.

• Control data input (serial data input) mode

3 IN3 (B2) 1 1 0 1 0 1 0 0

• 24 bits of data are input.

• See the “DI Control Data (serial data input)” section for details on the content of the input data.

• Data output (serial data output) mode

4 OUT (A2) 0 1 0 1 0 1 0 0

• The number of bits output is equal to the number of clock cycles.

• See the “DO Control Data (serial data output)” section for details on the content of the output data.

Structure of the DI Control Data (serial data input)

• IN1 (Main PLL/Latch-a)

• IN2 (Main PLL/Latch-a)

• IN3 (Sub PLL/Latch-b)

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IN 1

IN 2

IN 3

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