Sanyo LC7185-8750 Specifications

Ordering number: EN 3356A

CMOS IC

LC7185-8750

CB Transceiver PLL Frequency Synthesizer

and Controller

Overview

This 27 MHz band, PLL frequency synthesizer LSI chip is
designed specifically for CB transceivers.
The specifications are suited for use in U.S.A.(FCC).

Functions

The LC7185-8750 incorporates PLL circuitry and a controller
for CB applications on a single CMOS chip. The controller
handles the PLL circuitry, frequency data ROM, channel
preset/recall RAM, and LED display driver. It also supports
channel scan, channel preset/recall, and emergency channel
call.

Features

1. A built-in programmable divider for the 16 MHz VCO

2. Transmission is inhibited when the PLL is unlocked (digital
lock monitor).

3. Direct channel 9 or 19 selection (sliding switch)

4. A 7-segment, 2-character LED display

5. ‘‘PA’’ is displayed in public announcement mode.

6. Output beep-tone control circuitry

7. Up to 5 channel settings can be stored in memory.

8. 4 × 3 key matrix implementation

Package Dimensions

unit : mm

3061-DIP30S

[LC7185-8750]

SANYO : DIP30S (400 mil)

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS=0V

Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
Input voltage V

Output voltage V

Output Current I

Allowable power
dissipation

Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

max Pin V

DD

1 max Pins HOLD, TX –0.3 to +15 V

IN

V

2 max Input pins other than VIN1 max –0.3 to VDD+0.3 V

IN

1 max Pins SA, SB, SC, SD, SE, SF, SG, D1, D2 –0.3 to +15 V

O

V

2 max Pins UL, BEEP –0.3 to +15 V

O

V

3 max Pin PD –0.3 to VDD+0.3 V

O

V

4 max Output pins other than mentioned above –0.3 to VDD+0.3 V

O

1 max Pins SA, SB, SC, SD, SE, SF, SG 0 to +30 mA

O

I

2 max Pins D1, D2 0 to +10 mA

O

I

3 max Pins UL 0 to +20 mA

O

I

4 max Pin BEEP 0 to +10 mA

O

Pd max (Ta % 85°C) 350 mW

DD

–0.3 to +9.0 V

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

73098HA(II)/5220TA No.3356-1/12

LC7185-8750

Allowable Operating Conditions at Ta = –40 to +85°C, VSS=0V

Parameter Symbol Conditions min typ max Unit

Supply voltage V

Input high-level voltage

Input low-level voltage

Output voltage

Input frequency

Input amplitude
Required oscillating

frequency

DD

V

1 Pins HOLD, TX 0.7V

IH

V

2 Pin INIT 3.2 V

IH

V

3 Pins KI1, KI2, KI3, KI4 0.6V

IH

1 Pins HOLD, TX 0 0.3V

V

IL

V

2 Pin INIT 0 1.3 V

IL

V

3 Pins KI1, KI2, KI3, KI4 0 0.4V

IL

V

1 Pins SA, SB, SC, SD, SE, SF, SG, D1, D2 0 13 V

OUT

V

2 Pins UL, BEEP 08V

OUT

f

1 Pin XIN (sine wave, capacitor coupled) 1.0 10.24 15 MHz

IN

f

2 Pin PIN (sine wave, capacitor coupled) 10 30 MHz

IN

V

1 Pin XIN (sine wave, capacitor coupled) 0.5 1.5 Vrms

IN

V

2 Pin PIN (sine wave, capacitor coupled) 0.15 1.5 Vrms

IN

X’tal Pins XIN, XOUT (CI % 50 Ω) 5.0 10.24 15 MHz

Electrical Characteristics at under allowable operating conditions

Parameter Symbol Conditions min typ max Unit
Internal feedback resistance
Pull-down resistor RpdN Pins KI1, KI2, KI3, KI4, TEST 30 50 70 kΩ

Input high-level current

Input low-level current

Output high-level voltage

Output low-level voltage

Output leakage current

High-level tristate leakage
current

Low-level tristate leakage
current

Supply current

Rf1 Pin XIN 1.0 MΩ
Rf2 Pin PIN 500 kΩ

I

1 Pins HOLD, TX VI=12V 5.0 µA

IH

I

2 Pin INIT VI=V

IH

I

3 Pin XIN VI=V

IH

I

4 Pin PIN VI=V

IH

1 Pins HOLD, TX VI=V

I

IL

I

2 Pin INIT VI=V

IL

I

3 Pin XIN VI=V

IL

I

4 Pin PIN VI=V

IL

V

1 Pins KO1, KO2, KO3 IO=1mA VDD–2.0 VDD–1.0 VDD–0.5 V

OH

V

2 Pin PD IO= 0.5 mA VDD–1.0 V

OH

V

1 Pins KO1, KO2, KO3 IO= 20 µA 0.6 1.0 1.4 V

OL

V

2 Pin PD IO= 0.5 mA 1.0 V

OL

V

3 Pin BEEP IO= 2 mA 1.0 V

OL

V
V

V
I

OFF

I

OFF

I

OFFH

I

OFFL

I

Pins SA, SB, SC, SD, SE, SF, SG

4

OL

I

=20mA

O

5 Pins D1, D2 IO= 5 mA 1.0 V

OL

6 Pin UL IO=10mA 1.0 V

OL

Pins SA, SB, SC, SD, SE, SF, SG, D1, D2

1

V

=13V

O

2 Pins UL, BEEP VO=8V 5.0 µA

Pin PD VO=V

Pin PD VO=V
Normal mode

1

DD

*1 (PLL operates)
Hold mode V

I

*2 (memory backup)

2

DD

V

DD

= 8.0 V

DD

DD
DD
DD

SS

SS
SS
SS

DD

SS

= 3.2 V

5.0 8.0 V

DD

DD

12 V

DD

V

DD
DD

DD

5.0 µA
25 µA
50 µA

5.0 µA

5.0 µA
25 µA
50 µA

1.0 V

5.0 µA

0.01 10.0 nA

0.01 10.0 nA

510mA

515µA

V
V
V

V

µA

*1: fIN2 = 20 MHz (PIN)

V

2 = 0.15 Vrms

IN

X’tal = 10.240 MHz
TX = HOLD = INIT = V
Other inputs = V

SS

DD

*2: HOLD = V

TX = INIT = V
Other inputs = V
Other outputs = open

SS

DD

SS

Other outputs = open

Note: Be careful that the dielectric strength of pins SA, SB, SC, SD, SE, SF, D1, D2, UL, BEEP are weak.

No. 3356-2/12

Pin Assignment

Block Diagram

LC7185-8750

No. 3356-3/12

LC7185-8750

Pin Descriptions

TX Transmit/receive select PD Charge pump output
HOLD
INIT
TEST Test point (input) D1, D2 Digit output (for display)
V
PIN Programmable divider input KO1 to KO3 Key scan outputs
XIN, XOUT Crystal oscillator input, output

UL

1, VSS2 Power supply KI1 to KI4 Key inputs

DD,VSS

Key Matrix

Hold mode select NC NC pin
Initial input SAto SG Segment driver (for display)

BEEP Beep-tone control output

(10.240 MHz)
Unlock detection signal output

CH9 Emergency CH9 recall ME Station Memory Enable
CH19 Emergency CH19 recall M1 to M5 Station Memory recall
PA Public announcement display UP/DN/ME/M1 to 5 Momentary SW
MODE 1/2 Display Mode CH9/CH19/PA Slide SW
UP CH up/scan MODE 1/2 Diode
DN CH down/scan

LED Display Configuration (Common anode/7 segment)

No. 3356-4/12