Sanyo LC7153M Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

Universal Dual-PLL Frequency Synthesizers

Ordering number:ENN4160A

LC7153, 7153M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC7153 and LC7153M are universal dual-PLL fre­quency synthesizers for use in cordless telephone applica­tions in the USA, South Korea and Australia, and satellite
broadcast tuners in the USA and Europe.
The LC7153 and LC7153M both have two PLLs with a
16-bit programmable divider to generate a 1.5 to 160MHz
local-oscillator frequency, and a phase detector.
They also have a dual charge pump and fast lock-up cir­cuitry for rapid PLL locking when changing frequency, an
unlock indication output and an uncommitted output under
external control. The PLLs share a 14-bit divider to gener­ate a 320Hz to 640kHz reference frequency using a

10.24MHz crystal.
The LC7153 and LC7153M can be controlled from an ex­ternal microcontroller using a C2B serial interface.
They also have a standby mode for single PLL operation.
The LC7153 and LC7153M operate from a 4.0 to 5.5V
supply. The LC7153 is available in 24-pin DIPs, and the

LC7153M, in 24-pin MFPs.

Features

• Dual charge pump and fast lock-up circuitry for rapid
PLL locking.

• PLL unlock indication.

• 16-bit programmable local-oscillator divider.

• 1.5 to 160MHz local-oscillator frequency (VDD=4.0 to

5.5V).

• 14-bit programmable reference-frequency divider.

• 320Hz to 640kHz reference frequency using a 10.24MHz
crystal.

• LPF transistor.

• C2B serial interface.

• 4.0 to 5.5V supply.

• 24-pin DIP (LC7153) and 24-pin MFP (LC7153M)

Package Dimensions

unit:mm

3067A-DIP24S

[LC7153]

21.0

24

1

0.9

(0.71)

1.78

unit:mm

3112A-MFP24S

0.48

24

112

0.95

[LC7153M]

12.5

0.35

13

6.4

7.62

0.25

12

(3.25)

3.9max

3.3

0.51min

SANYO : DIP24S

13

5.4

1.7max

1.5

0.1

1.0

(0.75)

7.6

0.15

0.63

SANYO : MFP24S

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses
are controlled by SANYO.

73101TN (KT)/33195TH (ID)/9302JN No.4160–1/11

Pin Assignment

Block Diagram

LC7153, 7153M

No.4160–2/11

Pin Functions

rebmuNemaNnoitcnuF
1NIXtupnirotallicsolatsyrC
2ECtupnielbanepihC
3LCtupnikcolC
4IDtupniatadlaireS
5BDLtuptuorotceted-kcolnuBLLP
6ADLtuptuorotceted-kcolnuALLP
7ACnoitcennocAroticapacpu-kcoltsaF
8TSETtupnitseT
92ADPtuptuoyradnocesrotceted-esahpALLP

011ADPtuptuoniamrotceted-esahpALLP
11AIAtupniArotsisnartFPL
21AOAtuptuoArotsisnartFPL
31ATUOAtuptuodettimmocnU
41AIPtupnirotallicso-lacolALLP
51VSSdnuorG
61BIPtupnirotallicso-lacolBLLP
71VDDylppusV5
81BCnoitcennocBroticapacpu-kcoltsaF
91BTUOBtuptuodettimmocnU
02BOAtuptuoBrotsisnartFPL
12BIAtupniBrotsisnartFPL
221BDPtuptuoniamrotceted-esahpBLLP
322BDPtuptuoyradnocesrotceted-esahpBLLP
42TUOXtuptuorotallicsolatsyrC

LC7153, 7153M

Specifications

Absolute Maximum Ratings at Ta = 25˚C

retemaraPlobmySsnoitidnoCsgnitaRtinU

egnaregatlovylppuSV

egnaregatlovtupniBIAdnaAIA,ID,LC,ECV

egatlovtupniTSETdnaBC,AC,BIP,AIP,NIX

egnar

tnerructuptuoBTUOdnaATUO,BDL,ADL

egnar

egnartnerructuptuoBOAdnaAOAI

egnartnerructuptuoBCdnaACI

egnaregatlovtuptuoBDLdnaADLV

egatlovtuptuoBTUOdnaATUO,BOA,AOA

egnar

TUOXdnaBC,AC,2BDP,1BDP,2ADP,1ADP

egnaregatlovtuptuo

noitapissidrewopelbawollAxamdP

erutarepmetgnitarepOrpoT 58+ot04–

erutarepmetegarotSgtsT 521+ot55–

(Note) Pins PIA, PIB, CA and CB have a weaker electrostatic breakdown strength than the other pins.

Recommended Operating Conditions at Ta = 25˚C

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppuSV

egnaregatlovylppuSV

DD

1I

V

2I

I

1O
2O

3O

1O

V

2O

V

3O

3517CL 053Wm

M3517CL 042Wm

DD
DD

0.7+ot3.0–V

0.7+ot3.0–V

Vot3.0–

3.0+V

DD

3ot0Am
6ot0Am

1ot0Am

0.7+ot3.0–V

0.51ot3.0–V

Vot3.0–

3.0+V

DD

5V

5.5ot0.4V

˚C
˚C

No.4160–3/11

LC7153, 7153M

Electrical Characteristics at Ta = –40 to +85˚C, VDD=4.0 to 5.5V, VSS=0V, unless otherwise noted.

retemaraPlobmySsnoitidnoC

V

tnerrucylppuSI

egatlovtupnilevel-wolIDdnaLC,ECV

egatlovtupnilevel-hgihIDdnaLC,ECV

egatlovtuptuolevel-wol1BDPdna1ADPV
egatlovtuptuolevel-wol2BDPdna2ADPV

tuptuolevel-wolBTUOdnaATUO,BDL,ADL

egatlov

egatlovtuptuolevel-wolBOAdnaAOAV

egatlovtupuolevel-hgih1BDPdna1ADPV
egatlovtupuolevel-hgih2BDPdna2ADPV

egatlovtuptuoBDLdnaADLV

egatlovtuptuoBTUOdnaATUO,BOA,AOAV

egatlovtuptuoBCdnaACV

egatlovdlohserhtlevel-wolBCdnaACV

egatlovdlohserhtlevel-hgihBCdnaACV

tnerructupnilevel-wolIDdnaLC,ECI

tnerructupnilevel-wolNIXI

tnerructupnilevel-wolBIPdnaAIPI
tnerructupnilevel-wolBIAdnaAIAI

tnerructupnilevel-wolTSETI

tnerructupnilevel-hgihIDdnaLC,ECI

tnerructupnilevel-hgihNIXI

tnerructupnilevel-hgihBIPdnaAIPI
tnerructupnilevel-hgihBIAdnaAIAI

tnerructupnilevel-hgihTSETI

tnerrucegakaeltuptuoBDLdnaADLI

tnerruc

tnerruc

tnerrucegakaeltuptuoBCdnaACI

tnerrucecruosBCdnaACI

ycneuqerftupniNIXf

ycneuqerftupniBIPdnaAIPf

edutilpmatupnismrNIXV

edutilpmatupnismrBIPdnaAIPV

ycneuqerfrotallicsolatsyrCf

rotsiserkcabdeeflanretniNIXR

rotsiserkcabdeeflanretniBIPdnaAIPR

rotsisernwod-lluplanretniTSETR

ecnaticapactupniBIPdnaAIP,NIXC

V

egakaeltuptuo2BDPdna2ADP,1BDP,1ADP

I

egakaeltuptuoBTUOdnaATUO,BOA,AOA

I

tnerrucknisBCdnaAC0edompu-kcoltsaFI
tnerrucknisBCdnaAC1edompu-kcoltsaFI
tnerrucknisBCdnaAC2edompu-kcoltsaFI
tnerrucknisBCdnaAC3edompu-kcoltsaFI

V

DD

V
V

1LI

1HI

IOAm1= 0.1V

1LO

IOAm2= 0.1V

2LO

IOAm2=00.1V

3LO

I

O

4LO

I

O

IOAm1=V

1HO

IOAm2=V

2HO
1O
2O
3O

–

T

+

T

VIV0= 0.5Aµ

1LI

VIV,V0=

2LI

VIV,V0=

3LI

VIV0=10.00.01An

4LI

VIV,V0=

5LI

VIV5.5= 0.5Aµ

1HI

V

2HI

I

V

3HI

I

VIV0.5=10.00.01An

4HI

V

5HI

I

VOV5.5= 0.5Aµ

1FFO

V

2FFO

O

VOV31= 0.5Aµ

3FFO

V

4FFO

O

V

1S

O

V

)0(2S

O

V

)1(2S

O

V

)2(2S

O

V

)3(2S

O
1I
2I

1I
2I

CI≤ 05 Ω .3etoneeS.0.442.010.31zHM

LATX

V

1f

V

2f

V

d

I

f,V5.4=

DD

I

f,V5.5=

DD

I

f,V5.4=

DD

I

f,V5.5=

DD

I

V,Am5.0=

V=

AIA

V,Am1=

DD
DD

DD

V,V0.5=
V,V0.5=

V,V0.5=

VroV0=

V,V0=

DD

V,V0.3=
V,V0.3=
V,V0.3=
V,V0.3=

V0.5=7.0MΩ

DD

V0.5=034kΩ

DD

V0.5=03kΩ

DD

BIA

V=

AIA

BIA

V0.5=5.311Aµ
V0.5=0.60.81Aµ

V0.5=0.5Aµ

V0.5=5.30.11Aµ

DD

V0.5=0.60.81Aµ

DD

V0.5=061Aµ

DD

V5.5ro0=10.00.01An

DD

V0.5=59–091–083–Aµ

V0.5=l5.3

DD

V0.5=l5.2

DD

V0.5=l5.1

DD

V0.5=815307Aµ

DD

.1etoneeS.zHM06=0.90.81Am

.1etoneeS.zHM061=0.020.04Am

.2etoneeS.zHM06=0.50.01Am

.2etoneeS.zHM061=0.110.22Am

V2.1=05.0V

V3.1=05.0V

evawenisdelpuocyleviticapaC131zHM

V,evawenisdelpuocyleviticapaC

V0.5=5.1061zHM

DD

evawenisdelpuocyleviticapaC001008Vm
evawenisdelpuocyleviticapaC07008Vm

Notes

1. Dual PLL, both PLLA and PLLB operating, SB=0, f

=10.24MHz, V

XTAL

PIA=VPIB

outputs open.

2. Standby mode, PLLB stopped, SB=1, f

=10.24MHz, V

XTAL

=70mV, all other inputs=0V, all outputs open.

PIA

3. CI in the crystal impedance. Contact Nihon Denpa Kogyo for further information.

nimpytxam

08.0V

2.25.5V

1–V

DD

1–V

DD

05.5V

00.31V
0V

V5.0

DD

l0.4

)3(2s

l0.3

)3(2s

l0.2

)3(2s

=70mV, all other inputs=0V, all

sgnitaR

DD

V2.0

DD

001An

l5.4

)3(2s
)3(2s
)3(2s

0.6Fp

)3(2s

l4.3

)3(2s

l4.2

)3(2s

tinU

V
V
V

Aµ
Aµ
Aµ

No.4160–4/11

Serial Data Input Timing

LC7153, 7153M

retemaraPlobmySsnoitidnoC

emitputesataDt

emitdlohataDt

emitelbanepihclevel-WOLt

emitputeselbanepihCt

emitdlohelbanepihCt

htdiweslupkcolclevel-WOLt

htdiweslupkcolclevel-HGIHt

emithctalatadotelbanepihCt

US

DH

LE

SE

HE

LC

HC

AL

Functional Description
PLLA and PLLB Programmable Dividers

PLLA and PLLB input frequency ranges are set by Mode 2
command bits FA and FB, respectively. Their divider ra­tios, NA and NB, are set by Mode 1 command bits DA0 to
DA15 and DB0 to DB15, respectively.

Programmable Reference Divider

The divider ratio, NR, is set by Mode 2 command bits R0
to R13. The reference frequency is given by f

XIN

/(2×NR).

Phase Detector

The state of the phase-detector output as a function of the
divider ratio and reference frequency is shown in table 1.
Table 1. Phase-detector output states

noitidnoC1BDP,1ADP

fIf>N/

fer

fIf<N/

fer

fIf=N/

fer

HGIH

WOL

ecnadepmiHGIH

Note
N=NA for PLLA, and NB for PLLB

sgnitaR

nimxam

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01004sn

seicneuqerflatsyrcrehtOf/4

latsyrczHM42.01 004sn

seicneuqerflatsyrcrehtO f/4

LATX

LATX

LATX

LATX

LATX

LATX

LATX

tinU

sn

sn

sn

sn

sn

sn

sn

sn

LATX

When PLLA is unlocked, LDA is pulled LOW and both
PDA1 and PDA2 are active. PLLB operates identically to
PLLA. Mode 2 command bits UL0 and UL1 set the unlock
phase-error threshold, and bits UE0 and UE1, the LDA and
LDB output extension.

Dual Charge Pump

A typical dual charge-pump configuration is shown in fig­ure 1. The phase-detector secondary output is active after a
change in frequency , and the phase er ror causes the PLL to
unlock. In this case, the load resistance R1 becomes
R1M||R1S, decreasing the LPF time constant and the time
required to lock the PLL.

No.4160–5/11

LC7153, 7153M

Figure 1. Dual charge-pump circuit

The phase-detector secondary output is high impedance
when the PLL is locked. In this case, R1 becomes R1M,

Test Mode

TEST should be LOW or open for normal operation.

Serial Input Data

Serial data should be input only after f

has become

XIN

stable.

Mode 1 command format and functions

The Mode 1 command comprises the data bits which de­termine the PLLA and PLLB programmable divider ratios.

increasing the LPF time constant and improving sideband
and modulation response.

The command format is shown in figure 2. Bits DA0 to
DA15 and DB0 to DB15 determine the PLLA and PLLB
programmable divider ratios, respectively. Bit DA0 is the
first bit receiv ed. The r ange of allo wable divider ratios is N
=256 (0100H) to 65535 (FFFFH).

Figure 2. Mode 1 command (programmable divider data)

No.4160–6/11

LC7153, 7153M

Mode 2 command format and functions

The Mode 2 command comprises the data bits which de­termine the reference frequency divider ratio and control

Figure 3. Mode 2 command (reference divider and control data)

functions. The command format is shown in figure 3. Bit
R0 is the first bit received.

Bits R0 to R13 determine the reference divider ratio. The
range of allowable divider ratios is NR=8 (0008H) to 16383
(3FFFH).

Bits FL0 and FL1 are the fast lock-up mode select bits.
The fast lock-up modes are shown in table 2. The higher
the mode number, the greater the expansion width of the
detected phase error signal.

0LF1LFedompu-kcoltsaF
00 0
10 1
01 2
11 3

Bits OA and OB are the uncommitted output control bits.
They are latched and then inverted to control OUTA and
OUTB, respectively. If either bit is 1, the open-drain out­put is pulled LOW.

Bits FA and FB are the input frequency range select bits.
The PIA and PIB frequency ranges, set by FA and FB, re­spectively, are shown in table 3.
Table 3. Frequency ranges

BF,AFegnarycneuqerftupnItinU

00.04ot5.1zHM

1061ot53zHM

Bits HSA, HSB and HSM are the fast lock-up control bits.
When HSA or HSB=1, the fast lock-up circuits for PLLA
or PLLB, respectively, are ON. When HSA or HSB=0, the
respective circuits are OFF. For use with FM, the fast lock­up circuits should be OFF. HSM determines the fast lock­up operating mode. When HSM=0, operating mode 0 is
selected and the fast lock-up only operates when the PLLs
are unlocked. When HSM=1, operating mode 1 is selected
and the fast lock-up operates normally, as shown in figure

4.

Figure 4. Fast lock-up operating modes

Bit SB is the standby mode control bit. When SB=1, standby
mode is selected. In standby mode, PLLB is stopped, PIB
is pulled LOW, and PDB1 and PDB2 are high impedance.
When SB=0, normal operation is selected.

Bits UL0 and UL1 determine the unlock detection thresh­old. The PLL unlock detector output, LDA or LDB, is pulled
LOW when the phase differential between the reference
and the divider inputs exceeds the threshold set by UL0
and UL1. The threshold for different crystal frequencies is
shown in table 4, and the threshold for other frequencies
can be calculated. The threshold is common to both PLLs.
Note that a PLL will temporarity lose lock when either UL0
or UL1 is changed.

No.4160–7/11

LC7153, 7153M

Table 4. Unlock detector thresholds

0LU1LU

000 00000
10 f/4±
01 f/61±
11 f/46±

Bits UE0 and UE1 determine the unlock extension, or de­lay, before the unloc k detector outputs, LD A and LDB, can
change state. The extension for different reference frequen-

esahpBDL,ADL

dlohserhtrorre

f

NIX

NIX
NIX

zHM4=f

NIX

00.1±55.0±05.0±93.0±13.0±

00.4±22.2±00.2±65.1±02.1±

00.61±88.8±00.8±52.6±00.5±

NIX

zHM2.7=f

NIX

zHM8=f

cies is shown in table 5. However, if a phase-error thresh­old of zero is set using UL0 and UL1, no output extension
occurs.

Table 5. LDA, LDB output extension

0EU1EU

00 f/4
10 f/8
01 f/23
11 f/46

Bit DZ is the dead-zone selection bit. It selects the phase­insensitive bandwidth, or dead zone, of the phase compara-

tuptuoBDL,ADL

noisnetxe

fer
fer

fer
fer

f

zHk1=f

fer

)pyt(0.48.023.0

0.86.146.0

0.23)pyt(4.665.2

0.468.21)pyt(21.5

Bits T0, T1 and T2 are test bits. The y should be set to 0 for

normal operation.
tor. When DZ=1, DZB mode is selected, and when DZ=0,
DZA mode. DZB mode has larger dead zone than DZA
mode.

)sµ(sdlohserhtrorreesahpelpmaxE

NIX

zHk5=f

fer

zHM42.01=f

)sm(snoisnetxetuptuoelpmaxE

fer

NIX

zHM8.21=

zHk5.21=

No.4160–8/11

LC7153, 7153M

T ypical Application

A LC7153 or LC7153M cordless telephone application cir­cuit is shown in figure 5. The telephone is tuned to channel

1, which has a transmit VCO frequency of 46.610MHz

and a receive VCO frequency of 38.975MHz.

Figure 5. American 10-channel, 46/49 MHz, cordless telephone base station

For f

= 5kHz, the divider ratios are as follows.

ref

f

RX VCO

IA

NA= = = =7795 (1E73H)

f

ref

f

IB

NB= = = =9322 (246AH)

f

ref

f

XIN

NR= = 1024 (400H)

2×f

ref

f

ref

TX VCO

f

ref

10.24MHz

2×5kHz

38.975MHz
5kHz

46.610MHz
5kHz

No.4160–9/11

LC7153, 7153M

The Mode 1 and Mode 2 commands are shown in tables 6 and 7, respectively, and in figures 6 and 7, respectively.

Table 6. Mode 1 command

dleiFeulaVtnemmoC

51ADot0ADH37E15977oitarredividALLP
51BDot0BDHA6422239oitarredividBLLP

Figure 6. Mode 1 command

Table 7. Mode 2 command

dleiFeulaVtnemmoC

31Rot0RH00404201fooitarredividecnerefeR

1LF,0LF000edompu-kcoltsaF
AO0
BO0
AF1 egnarycneuqerftupniOCVXRzHM55ot02
BF1 egnarycneuqerftupniOCVXTzHM55ot02

BSH,ASH00FFOpu-kcoltsafBLLPdnaALLP

MSH0 0edomgnitarepopu-kcoltsaF

BS1ro0noitcelesedomybdnatS

1LU,0LU11dlohserhtnoitcetedkcolnu/kcolsµ52.6±

1EU,0EU10noisnetxetuptuoBDLdnaADLsm4.6

ZD1 edomenoz-daedBZD

2T,1T,0T000detcelesededomtseT

.nepotfelBTUOdnaATUO

Figure 7. Mode 2 command

No.4160–10/11

LC7153, 7153M

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of July, 2001. Specifications and information herein are subject to
change without notice.

PS No.4160–11/11