Sanyo LC7073M Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

Error Detection and Correction ICs

for RDS Demodulators

Ordering number:ENN *3932

LC7073, 7073M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Preliminary
Overview

The LC7073 and LC7073M are error detection and correc­tion ICs that provide an easy interface to the LA2230 and
LA2231 radio data system (RDS) demodulators. Both de­vices incorporate an on-chip oscillator that connects directly
to an external ceramic resonator.
The LC7073 and LC7073M provide group synchroniza­tion, selectable error detection and correction, output clock
polarity selection, a block data start signal output and an
error output that signals error correction failures.
The LC7073 and LC7073M operate from a 5 V supply and
are available in 18-pin DIPs and MFPs, respectively.

Features

• RDS error detection and correction.

• Easy interface with LA2230 and LA2231 demodulator
ICs.

• Serial data transfer system.

• Group synchronization capability.

• Selectable error detection and correction.

• Output clock polarity selection.

• Block data start output.

• Error output.

• On-chip oscillator.

• 5 V supply.

• 18-pin DIP (LC7073) and 18-pin MFP (LC7073M).

Pin Assignment

Package Dimensions

unit:mm

3007B-DIP18

[LC7073]

24.0

18

1

(1.84)

unit:mm

3095-MFP18

18

1

2.54

[LC7073M]

12.6

0.35

1.27

10

9

(3.25)

1.20.5

10

5.4

9

1.22

0.15

1.8max

1.5

0.1

6.4

7.62

3.85max

3.3

0.51min

SANYO : DIP18

7.6

6.35

0.625

0.25

Top view

71901TN (KT)/5281JN(US) No.3932–1/9

SANYO : MFP18

Block Diagram

LC7073, 7073M

Pin Function

rebmuNemaNtiucrictnelaviuqEnoitpircseD

11CSO 1noitcennocrotanosercimareclanretxE

2V
3V

4SER selcyckcolc4fomuminimarofWOLdleH.tupniteserreggirt-ttimhcS

5NIKC kcolctuptuorotaludomedSDRotstcennoC.kcolctupniatadlaireS

6NID tuptuoatadrotaludomedSDRotstcennoC.tupniatadlaireS

1SS
2SS

dnuorG
dnuorG

7NEROC

noitcerrocrorreselbane

HGIHdnanoitcerrocrorreselbasidWOL.tupnielbanenoitcerroc-rorrE

Continued on next page.

No.3932–2/9

Continued from preceding page.

rebmuNemaNtiucrictnelaviuqEnoitpircseD

8LOPKC tupnitcelesytiralopkcolctuptuoatadlaireS

LC7073, 7073M

9V

01CER

11LTCTSD

21ROC

31RRE

DD

ylppusV5

cnysretfa,gniviecerelihwWOL.tuptuotcetedevieceratadlaireS

teser

skcolbllarof,HGIH

teserretfa

retfaecnadepmihgiH.gniviecertonnehwecnadepmihgiH.noitceted

dna,kcolbdnocesroftratsatadsetaitiniWOL.tupnilortnoctratsataD

noitcerrocrorrenehwWOL.tuptuodelbasid/delbanenoitcerroc-rorrE

ecnadepmihgiH.srucconoitcerrocrorreonnehwHGIHdnasrucco

ecnadepmihgiH.sliafnoitcerrocrorrenehwWOL.tuptuotceted-rorrE

teserretfaecnadepmihgiH.liaftonseodnoitcerrocrorrenehw

41TSD

51TUOD teserretfaHGIH.tuptuoatadlaireS

61TUOKC kcolctuptuoatadlaireS

71V

812CSO 2noitcennocrotanosercimareclanretxE

3SS

atad,HGIHdna,tratsatadonsetacidniWOL.tuptuotratsatadlaireS

teserretfaHGIH.trats

dnuorG

No.3932–3/9

LC7073, 7073M

Specifications

Absolute Maximum Ratings at Ta = +25˚C, V

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppusmumixaMV

egatlovtuptuoTUOKCdnaTUOD,TSD,2CSOV

egatlovtuptuoRREdnaROC,CERV

egatlovtupni1CSOdnaSERV

tupniLTCSDdnaLOPKC,NEROC,NID,NIKC

egatlov

tnerructuptuoRREdnaROC,CERI

tnerructuptuoTUOKCdnaTUOD,TSDI

tnerruclatotsniptuptuOI

noitapissidrewopelbawollaPIDxamdP

noitapissidrewopelbawollaPFMxamdP 002otWm

erutarepmetgnitarepOrpoT

erutarepmetegarotSgtsT

xamDD
1O
2O

1I

V

2I

1O

2O

O

, V

SS2

, V

SS3

SS1

DIP: Ta=–40 to +85˚C
MFP: Ta=–40 to +85˚C

= 0V

– 0.7+ot3.0V

– ot3.0

V

3.0+V

DD

– 51+ot3.0

–

ot3.0

V

DD

– 51+ot3.0

–

–

–

–

V

3.0+

V
V

02

Am

02+ot2

Am

09+ot41

Am

082ot

Wm

58+ot04

˚C

521+ot55

˚C

Reommended Operating Conditions at Ta = –40 to +85˚C, V

retemaraPlobmySsnoitidnoC

egnaregatlovylppuSV

-hgihLTCSDdnaLOPKC,NEROC,NID,NIKC

egatlovtupnilevel

egatlovtupnilevel-hgih1CSOdnaSERV

-wolLTCSDdnaLOPKC,NEROC,NID,NIKC

egatlovtupnilevel

egatlovtupnilevel-wolSERV

Electrical Characteristics at Ta = –40 to +85˚C, V

retemaraPlobmySsnoitidnoC

-hgihLTCSDdnaLOPKC,NEROC,NID,NIKC

tnerructupnilevel

-wolLTCSDdnaLOPKC,NEROC,NID,NIKC

tnerructupnilevel

tnerructupnilevel-wolSERI

tuptuolevel-hgihTUOKCdnaTUOD,TSD

egatlov

TUOKCdnaTUOD,TSD,RRE,ROC,CER

egatlovtuptuolevel-wol

tnerrucegakaeltuptuoRREdnaROC,CERI

egatlovsiseretsyhSERV

tnerrucylppuSI

emitnoitazilibatsrotallicsOt

DD

V

1HI

2HI

V

1LI
2LI

, V

SS1

I

VIV5.31= 0.5Aµ

1HI

I

VIV=

1LI

2LI

V

HO

V

LO

FFO

SYH

DD

SFC

VIV=
IHO=– Aµ05
IHO=– Aµ01
I

LO

I

LO

V

O

VOV=

SS
SS

SS

, V

SS2

Am01= 5.1

V5.31= 0.5

.2etoneeS401Am

.7erugifeeS 01sm

, V

, V

SS1

SS2

= 0V, VDD = 4.5 to 6.0V

SS3

.1etoneeS,Am8.1= 4.0

= 0V, VDD = 4.5 to 6.0V

SS3

nimpytxam

5.40.6V

V7.0

DD

V8.0

DD

V

SS

V

SS

nimpytxam

– 0.1Aµ

– 54 – 01Aµ

VDD– 2.1
VDD– 5.0

– 0.1

V1.0

sgnitaR

sgnitaR

DD

5.31V

V

DD

V3.0

DD

V52.0

DD

tinU

V
V
V

tinU

V

V

Aµ

V

Note

1. Idle pins have output currents less than 1mA.

2. Oscillator running, V

I=VDD

, IO=0mA

No.3932–4/9

LC7073, 7073M

Timing Diagrams

The relationship between the LC7073 and LC7073M input data (RDS demodulated data output) and output data is shown
in figure 1.

Figure 1. Input and output data

Note

The dotted lines show data start (DST) pulses when the data start control (DSTCTL) is LOW. The serial output data is
delayed by one block between input and output. The error (ERR) and correction (COR) signals remain acti v e if errors are
detected continually.

Serial Output Data Timing and Format

The following list shows the symbols used in the serial output data string in figure 2.

S Start bit (normally 0)
E Error flag (See table 1.)
F Correction flag (See table 1.)
OE Offset E (normally 0, not used)
OF Offset F (normally 0, not used)
A/B Group. 0–group A, 1–group B
B0, B1 Block bits. 00–1st block, 01–2nd block, 10–3rd block, 11–4th block
D0 to D15 Output data

Table 1. Error and correction flags

noitacidnIEF

rorreoN00

detcerrocrorrE01

elbatcerroctoN1

×

Note

× = don’t care

No.3932–5/9

LC7073, 7073M

Figure 2. Serial output data format and timing

CKPOL Input Read Delay

CKPOL is read 1 ms after a reset as shown in figure 3.

Figure 3. CKPOL input read delay

No.3932–6/9

LC7073, 7073M

COREN and DSTCTL Input Read

COREN and DSTCTL are monitored at intervals of one input clock cycle, and their logic states can be changed at any
time. During sync detection, a change in input state occurs if either pin remains steady for four successive clock intervals
as shown in figure 4.

Figure 4. Input read during sync detection

After sync detection a change in input state occurs if either COREN or DSTCTL remains steady for four successive input
data blocks as shown in figure 5.

Figure 5. Input read after sync detection

Design Notes

Oscillator specifications are shown in table 2 and figure 6. Oscillator stabilization delay is shown in figure 7. Reset input
circuitry is shown in figure 8. Supply rise time versus RES delay is shown in figure 9.

Table 2. Oscillator capacitor values

epytrotanoserzHM42C,1C

GM00.4ASC-ataruM %01±Fp03

M0.4RBK-arecoyK %01±Fp03

OSC1

C1 C2

Ceramic

resonator

OSC2

Figure 6. Oscillator circuit

V

DD

4.5V
0V

OSC

t

CFS

t

is the oscillator stabilization time

CFS

Figure 7. Oscillator stabilization delay

No.3932–7/9

LC7073, 7073M

V

DD

RES

V

DD

＋

C=0.1µF

Figure 8. Reset input

V

DD

4.5V
RES

Oscillator stabilization
time (10 to 100 ms)

Start point

0.8V

1.125V
(0.25VDDmin)

DD

Figure 9. Supply rise time vs. reset delay

A minimum delay of 10 ms should be allowed for oscillator stabilization. A 10 to 100 ms reset delay is generated using
a 0.1 µF reset capacitor, C. A larger capacitor should be used if the supply rise time is longer.

Figure 10. System block diagram

Device Comparison

The LC7070N, LC7070M and LC7071NM have identical basic functions, pinouts and input/output timing to those of the
LC7073 and LC7073M. Their respective packages and output circuitry are compared in table 3.

Table 3. Device comparison

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N0707CLPIDnip-81

MN0707CLPFMnip-81
MN1707CLPFMnip-81

M3707CLPFMnip-81

niard-nepO

srotsisnartSOMgnisuelop-metoT3707CLPIDnip-81

The differences in output data format between the LC7070N/LC7070NM/LC7071NM and LC7073/LC7073M are as
follows.

Offset Words E and F

The LC7070N/LC7070NM/LC7071NM recognizes offset words E and F and performs group sync detection. The LC7073/
LC7073M does not recognize offset words E and F–it only detects A, B, C, C’ and D.

Input Data Bits

If all data bits are 0, the LC7070N/LC7070NM/LC7071NM only recognizes offset word E. The LC7073/LC7073M does
not recognize the offset word E block. No sync detection occurs if all input data bits are 0. Once data cutoff has been
determined, output data stops and the sync cutoff sequence begins.

No.3932–8/9

LC7073, 7073M

Sync Detection Method

The LC7070N/LC7070NM/LC7071NM searches for 5 consecutive blocks in the correct sequence within each group of
12 blocks. The LC7073/LC7073M searches for 2 consecutive blocks in the correct sequence within each group of 3
blocks.

Data Output After Sync Detection

The LC7070N/LC7070NM/LC7071NM starts data output with the first block (offset A) directly after the last block in the
sync detection group. If sync detection occurs during the first block (offset A), the LC7073/LC7073M starts data output
with the second block (offset B). If sync detection occurs during the second or third block (offset B or C), and finishes
before the end of the fourth block (offset D), the LC7073/LC7073M starts data output with the first block (of fset A) of the
second group.

Sync Error

A sync error occurs if no offset word is detected for more than fi v e consecuti v e blocks. This applies to both the LC7070N/
LC7070NM/LC7071NM and LC7073/LC7073M.

Error Correction

In error-correction mode, an error of less than 5 bits is corrected to an accuracy of 5 bits. This applies to both the
LC7070N/LC7070NM/LC7071NM and the LC7073/LC7073M.

Precaution

Note that the solder-dip method should not be used for the LC7073M (MFP).

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of July, 2001. Specifications and information herein are subject to
change without notice.

PS No.3932–9/9