Sanyo LC66PG5XX Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

EPROM-Mountable Type 4-bit Microcomputer

Evaluation Chip for The LC665XX Series

Microcomputers

Ordering number:ENN2648

LC66PG5XX

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC66PG5XX is an EPROM-mountable type 4-bit mi­crocomputer for developing and evaluating programs writ­ten for the CMOS 4-bit single-chip LC665XX series mi­crocomputers. Either 2764 or 27128 type EPROM can be
mounted on the LC66PG5XX. The LC66PG5XX with the
EPROM mounted can carry out the same functions as those
of the LC665XX series microcomputers. Therefore, you
can evaluate programs developed for application products
controlled by the LC665XX series microcomputers by in­corporating the LC66PG5XX into the applications before
the programs are masked in the ROMs.

Features

• Either 2764 or 27128 type EPROM can be mounted.

• Shrink type 64-pin configuration compatible with the
LC665XX series microcomputers. Note that pull-up re­sistors need to be externally added.

• Options provided for selecting functions.
Options allowing the user to select output signal lev el for
ports 0, 1 and 8 at the initial reset or to specify whether
the watchdog timer function is employed by setting ex­ternal pin levels

• Instruction cycle time 0.92 to 10 microseconds.

• +5V single power source.

Pin assignment

The LC66PG5XX has the 28-pin soket and 14-pin soket
on the top face of the package. It also has the shrink type
64-pin terminals on the bottom face of the package. The
28-pin soket is used for mounting the EPROM containing
the programs and 14-pin soket for selecting functions by
options (input/output options not included). The shrink type
64-pin terminals are compatible with the LC665XX series
microcomputers.

N3001TN (KT)/7317KI, TS No.2648–1/14

LC66PG5XX

Configurations of the LC665XX series microcomputers

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yticapacMAR215 4× 215 4× 215 4× 215 4× 215 4× 215 4×

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S46PID

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←←←
←←←

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Notes on use

The LC66PG5XX is a product for developing and evaluating programs for the LC665XX series microcomputers. Keep
always in mind the following considerations when using the LC66PG5XX.

1. The operating conditions are different from those of the production mask ROM . It is not recommended that the

LC66PG5XX is used under the environmental conditions including high temperature and terrible humidity.

2. The electric characteristics are not the same as those of the production mask ROM. To evaluate strictly the electric

characteristics at the interface with external circuits, use the recommended electric characteristics values of the pro­duction mask ROM.

3.The discrepancy in internal circuit pattern configuration between the LC66PG5XX and the production mask ROM

results in the following differences between them.

•Differrent initial values are set in RAMs at power ON.

•Differrent noise figures (NF) are recorded. That is, the static noise intensity of the LC66PG5XX is dif ferent from that

of the production mask ROM. Keep it always in mind.

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External dimension

No.2648–2/14

Overview of terminal function

Terminal

name

P01
P02
P03

output

I/OP00

Input/output port P00 to P03

•Data input and output in 4-bit units or in 1­bit units.

•P00 to P03 used for controlling HALT mode.

LC66PG5XX

FunctionInput/

LC66PG5XX output

format

•Nch OD output •Pull-up MOS or Nch OD

Option

(production chip)

(open drain) output

•Output level at initial
reset

At initial

reset

H or L

(optional)

P11
P12
P13

P21/SO0
P22/SCK0
P23/INT0

P31/POUT0
P32/POUT1

Input/output port P10 to P13

I/OP10

•Data input and output in 4-bit units or in 1­bit units.

Input/output port P20 to P23

I/OP20/SI0

•Data input and output in 4-bit units or in 1­bit units.

•P20 also used as SI0 terminal for serial
input.

•P21 also used as SO0 for serial output.

•P22 also used as SCK0 for serial clock
signal input/output.

•P23 also used as INT0 terminal for INT0
interrupt request input . In addition, it is
used for timer 0 event count input and pulse
width measurement input.

Input/output port P30 to P32

I/OP30/INT1

•Data input and output in 3-bit units or in 1­bit units.

•P30 also used as INT1 terminal for INT1
interrupt request signal.

•P31 also used for burst pulse signal output
from timer 0.

•P32 also used for burst pulse signal output
from timer 1 and PWM signal output.

•Nch OD output •Pull-up MOS or Nch OD
output

•Output level at initial
reset

•Nch OD output •CMOS or Nch OD
output

•Nch OD output •CMOS or Nch OD
output

H or L

(optional)

H

H

P41
P42
P43

HOLD mode control input.

IP33/HOLD –––

•When HOLD=L, HOLD mode to be set by
the HOLD instruction.

•During HOLD mode "ON", restart up to the
CPU by applying "H"-level signal to the
HOLD terminal.

•Also used as input port P33 if used together
with port P30 to P32.

•CPU not to be reset even if "L"-level signal
is applied to the RES terminal with the
P33/HOLD set to "L". The output level of the
P33/HOLD terminal at power ON must not
be set "L"on your application products.

I/OP40

Input/output port P40 to P43

•Data input and output in 4-bit units and 1-bit
units.

•Also used for data input/output in 8-bit units
if jointly used with port P50 to P53.

•Used for ROM data output in 8-bit units if
jointly used with port P50 to P53.

•Nch OD output •Pull-up MOS or Nch OD
output

H

Continued on next page

No.2648–3/14

Continued from preceding page

Terminal

name

Input/

output

Function

LC66PG5XX

LC66PG5XX output

format

Option

(production chip)

At initial

reset

P51
P52
P53

P61/SO1
P62/SCK1
P63/PIN1

P71
P72
P73

P80
P81
P82
P83

Input/output port P50 to P53

I/OP50

•Data input/output in 4-bit units and 1-bit
unit.

•Used for input/output in 8-bit units if jointly
used with port P40 to P43.

•Used for ROM data output in 8-bit units if
jointly used with port P40 to P43.

Input/output port P60 to P63

I/OP60/SI1

•Data input/output in 4-bit units and 1-bit
units.

•P60 terminal also used as terminal SI1 for
serial input.

•P61 terminal also used as terminal SO1 for
serial output.

•P62 terminal also used as terminal SCK1
for serial clock signal input/output.

•P63 terminal also used for event count input
to timer 1.

Output port P70 to P73

OP70

•Data output in 4-bit units and in 1-bit units.

•The contents of output latch circuit to be
input with input-related instructions.

O

Output port P80 to P83

•Data output in 4-bit units and in 1-bit units.

•The contents of output latch circuit to be
input with input-related instructions.

•Pch OD output option available.

•Nch OD output •Pull-up MOS or Nch OD
output

•Nch OD output •CMOS or Nch OD
output

•Nch OD output •Pull-up MOS or Nch OD
output

•Pch OD output •CMOS or Pch OD
output

•Output level at the initial
reset

H

H

H

H or L

(optional)

P91/INT3
P92/INT4
P93/INT5

PA1
PA2
PA3

PB1
PB2
PB3

I/OP90/INT2

Input/output port P90 to P93

•Data input and output in 4-bit units and in 1­bit units.

•P90 also used as the INT2 terminal for INT2
interrupt request input.

•P91 also used as the INT3 terminal for INT3
interrupt request input.

•P92 also used as the INT4 terminal for INT4
interrupt request input.

•P93 also used as the INT5 terminal for INT5
interrupt request input.

Output port PA0 to PA3

OPA0

•Data output in 4-bit units and in 1-bit units.

•The contents of output latch circuit to be
input with input-related instructions.

Output port PB0 to PB3

OPB0

•Data output output in 4-bit units and in 1-bit
units.

•The contents of output latch circuit to be
input with input-related instructions.

•Nch OD output •CMOS or Nch OD
output

•Nch OD output •Pull-up MOS or Nch OD
output

•Nch OD output •Pull-up MOS or Nch OD
output

Continued on next page

H

H

H

No.2648–4/14

Continued from preceding page

Terminal

name

PC1
PC2/VREF0
PC3/VREF1

output

I/OPC0

LC66PG5XX

FunctionInput/

Input/output port PC0 to PC3

•Data input and output in 4-bit units and in
1-bit units.

•PC2 also used as the VREF0 terminal for
reference voltage input.

•PC3 also used as the VREF1 terminal for
reference voltage input.

LC66PG5XX output

format

•Nch OD output •CMOS or Nch OD

Option

(production chip)

output

At initial

reset

H

H

PD1/CMP1
PD2/CMP2
PD3/CMP3

PE1/TRB

OSC1
OSC2

IPD0/CMP0

Input port PD0 to PD3

•Can be selected as comparator input
terminals on programs.

PD0 : reference voltage input (VREF0).
PD1 to PD3 : reference voltage input

(VREF1)

•PD0, PD1 (PD2 to PD3) selectable as
comparator input ports on programs in this
unit.

Input port

IPE0/TRA

•Selectable as three-state input port on
programs.

Terminals for system clock oscillator

I

O

externally added.

•Leave OSC2 open and close OSC1 for
external clock signal input when external
clock mode is selected.

IRES

Terminal for system reset signal input.

•CPU to be initialized when P33/HOLD="H"
plus "L" level voltage is applied to the RES
terminal.

ITEST

Terminal for CPU test signal input.

•Always connected to VSS during operation.

– – Normal input

– – Normal input

–

•Ceramic resonator
oscillation, RC (resistor
and capacitor) or
external clock selection.

–

–––

–––

V

DD

V

SS

–

Power source terminal

–––

No.2648–5/14