Sanyo LC66356B Specifications
Ordering number : EN4677
93098HA (OT) / 83194TH (OT) B8-0696 No. 4677-1/23
LC66354B, 66356B, 66358B
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Four-bit Single-Chip Microcontrollers
On-Chip 4 K/6 K/8 K-byte ROM
CMOS LSI
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC66354B, LC66356B and LC66358B are 42-pin
package four-bit CMOS microcontrollers that integrate on
a single chip all functions required in a control
microcontroller, including ROM, RAM, I/O ports, serial
interfaces, comparator inputs, three-value inputs, timers
and an interrupt system. These products differ from the
earlier LC66358A series in their power supply voltage
range and operating speed specifications.
Features and Functions
• ROM (with 4 K-, 6 K- and 8 K-byte capacities) and
RAM (512 4-bit digits) on chip
• LC66000 series compatible instruction set
(128 instructions)
• A total of 36 I/O port pins
• Two eight-bit serial interfaces that can be connected in
cascade to form a 16-bit interface
• Instruction cycle time: 0.92 to 10 µs (3 to 5.5 V)
The earlier LC66358A series had instruction cycle times
of from 1.96 to 10 µs (at 3 to 5.5 V) and from 3.92 to
10 µs (at 2.2 to 5.5 V).
• Powerful timer and prescaler functions
Time limit timer, event counter, pulse width measurement
and square wave output using a 12-bit timer.
Time limit timer, event counter, PWM output and
square wave output using an 8-bit timer.
Time base function using a 12-bit prescaler.
• Powerful interrupt system with eight interrupts and eight
vector locations
External interrupts: three interrupts and three vector
locations
Internal interrupts: five interrupts and five vector
locations
• Flexible I/O functions
Comparator inputs, three-value inputs, 20 mA drive
outputs, 15 V withstand voltage, pull-up or open-drain
option switching
• Runaway detection function (watchdog timer) option
• Eight-bit I/O function
• Power reduction functions using halt and hold modes
• Packages: DIP42S, QIP48E (QFP48E)
• Evaluation LSI: used together
— LC66599 (evaluation chip) + EVA850/800-
TB6630X
— LC66E308 (on-chip EPROM microcontroller)
Series Structure
Note: * Under development
Pin Assignments
We recommend using reflow soldering methods to mount the QFP package version.
Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is
immersed in a solder bath (solder dip or spray techniques) are used.
No. 4677-2/23
LC66354B, 66356B, 66358B
Product name Pins ROM capacity RAM capacity Package Features
LC66304A/306A/308A 42, 48 4 K/6 K/8 K bytes 512 W DIP42S QFP48E
Normal version
LC66404A/406A/408A 42, 48 4 K/6 K/8 K bytes 512 W DIP42S QFP48E
4.0 to 6.0 V/0.92 µs
LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 K bytes 512 W DIP64S QFP64A
LC66354A/356A/358A 42, 48 4 K/6 K/8 K bytes 512 W DIP42S QFP48E
Low-voltage version
LC66354S/356S/358S
*
44 4 K/6 K/8 K bytes 512 W QFP44M
2.2 to 5.5 V/3.92 µs
LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 K bytes 512 W DIP64S QFP64E
LC66354B/356B/358B 42, 48 4 K/6 K/8 K bytes 512 W DIP42S QFP48E
Low-voltage, high-speed
LC66556B/558B
*
64 6 K/8 K bytes 512 W DIP64S QFP64E version
LC66562B/566B 64 12 K/16 K bytes 512 W DIP64S QFP64E
3.0 to 5.5 V/0.92 µs
LC66E308 42, 48 EPROM, 8 K bytes 512 W DIC42S (window) QFC48 (window)
LC66P308 42, 48 OTPROM, 8 K bytes 512 W DIP42S QFP48E
LC66E408 42, 48 EPROM, 8 K bytes 512 W DIC42S (window) QFC48 (window)
Evaluation window and OTP
LC66P408 42, 48 OTPROM, 8 K bytes 512 W DIP42S QFP48E
versions
LC66E516 64 EPROM 16 K bytes 512 W DIC64S (window) QFC64 (window)
4.5 to 5.5 V/0.92 µs
LC66P516 64 OTPROM 16 K bytes 512 W DIP64S QFP64E
Top view
System Block Diagram
Differences between the LC66354B, LC66356B and LC66358B and the LC6630X Series
Note: 1. An RC oscillator cannot be used with the LC66354B, LC66356B and LC66358B.
2. In addition, there are differences in the output currents, comparator input voltages and other aspects.
For details, refer to the individual catalogs for the LC66308A, LC66E308 and the LC66P308.
3. These points require care when using the LC66E308 or LC66P308 for evaluation purposes.
No. 4677-3/23
LC66354B, 66356B, 66358B
Parameter
LC6630X series
LC6635XB series
(including the LC66599 evaluation chip)
System Differences
65536 cycles 16384 cycles
• Hardware wait time (number of cycles)
At 4 MHz (Tcyc = 1 µs): About 64 ms At 4 MHz (Tcyc = 1 µs): About 16 ms
when HOLD mode is cleared
• Value of timer 0 on reset
The value FFO is loaded. The value FFC is loaded.
(including the value after HOLD mode is cleared)
Main differences in product characteristics
LC66304A, 66306A, 66308A
3.0 to 5.5 V/0.92 to 10 µs
• Operating power supply voltage/operating speed
4.0 to 6.0 V/0.92 to 10 µs
LC6635XA, 2.2 to 5.5 V/3.92 to 10 µs,
(cycle time)
LC66E308, 66P308
3.0 to 5.5 V/1.96 to 10 µs
4.5 to 5.5 V/0.92 to 10 µs
SANYO: QFP48E
[LC66354B, 66356B, 66358B]
SANYO: DIP42S
[LC66354B, 66356B, 66358B]
Package Dimensions
unit: mm
3025B-DIP42S
unit: mm
3156-QFP48E
Pin Function Overview
No. 4677-4/23
LC66354B, 66356B, 66358B
Pin I/O Overview Output drive type Option Value on reset
P00
P01
P02
P03
P10
P11
P12
P13
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
P30/INT1
P31/POUT0
P32/POUT1
P33/HOLD
P40
P41
P42
P43
I/O
I/O
I/O
I/O
I
I/O
I/O ports P00 to P03
• Input or output in 4-bit or 1-bit units
• P00 to P03 have control functions in
HALT mode.
I/O ports P10 to P13
• Input or output in 4-bit or 1-bit units
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input
SI0 pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0
interrupt request, the timer 0 event
counter and pulse width
measurement input.
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1
interrupt request.
• P31 is also used for square wave
output from timer 0.
• P32 is also used for square wave
output from timer 1 and PWM
output.
Hold mode control input
• Hold mode is entered if a HOLD
instruction is executed when HOLD
is low.
• When in hold mode, the CPU is
reactivated by setting HOLD to the
high level.
• P33 can also be used as an input
port along with P30 to P32.
• When P33/HOLD is low, the CPU
will not be reset by a low level on
RES. Therefore, RES cannot be
used in applications that set
P33/HOLD low when power is first
applied.
I/O ports P40 to P43
• Input or output in 3-bit or 1-bit units
• I/O in 8-bit units when used in
conjunction with P50 to P53
• Output of 8-bit ROM data when
used in conjunction with P50 to P53
• P-channel: pull-up MOS
type
• N-channel: intermediate
sink current type
• P-channel: pull-up MOS
type
• N-channel: intermediate
sink current type
• P-channel: CMOS type
• N-channel: intermediate
sink current type (+15 V
withstand voltage in OD)
• P-channel: CMOS type
• N-channel: intermediate
sink current type (+15 V
withstand voltage in OD)
• P-channel: pull-up MOS
type
• N-channel: intermediate
sink current type (+15 V
withstand voltage in OD)
• Either with pull-up MOS
or n-channel OD output
• Reset output level
• Either with pull-up MOS
or n-channel OD output
• Reset output level
• Either CMOS or n-channel
OD output
• Either CMOS or n-channel
OD output
• Either with pull-up MOS
or n-channel OD output
High or low level (option)
High or low level (option)
H
H
H
Continued on next page.
Continued from preceding page.
Note: Pull-up MOS output:........A pull-up MOS transistor is connected to the output circuit.
CMOS output:.................Complementary output
OD output:.......................Open drain output
No. 4677-5/23
LC66354B, 66356B, 66358B
Pin I/O Overview Output drive type Option Value on reset
P50
P51
P52
P53/INT2
P60/SI1
P61/SO1
P62/SCK1
P63/PIN1
PC2/VREF0
PC3/VREF1
PD0/CMP0
PD1/CMP1
PD2/CMP2
PD3/CMP3
PE0/TRA
PE1/TRB
OSC1
OSC2
RES
TEST
V
DD
V
SS
I/O
I/O
I/O
I
I
I
O
I
I
I/O ports P50 to P53
• Input or output in 4-bit or 1-bit units
• I/O in 8-bit units when used in
conjunction with P40 to P43
• Output of 8-bit ROM data when
used in conjunction with P40 to P43
• P53 is also used for the INT2
interrupt request.
I/O ports P60 to P63
• Input or output in 4-bit or 1-bit units
• P60 is also used as the serial input
SI1 pin.
• P61 is also used as the serial output
SO1 pin.
• P62 is also used as the serial clock
SCK1 pin.
• P63 is also used as the timer 1
event counter input.
I/O ports PC2 and PC3
• Output in 4-bit or 1-bit units
• PC2 is also used as the VREF0
comparator comparison voltage pin.
• PC3 is also used as the VREF1
comparator comparison voltage pin.
Dedicated input ports PD0 to PD3
• Can be switched to use as comparator inputs under program control.
The PD0 comparison voltage is
VREF0.
The PD1 to PD3 comparison
voltage is VREF1.
Comparisons can be specified in
units of PD0, PD2, and PD2 and
PD3 together.
Dedicated input ports
• Can be switched to function as threevalue inputs under program control.
System clock oscillator external
connection
When an external clock is used, leave
OSC2 open and input the clock signal
to OSC1.
System reset input
The CPU is initialized if a low level is
input to RES when the P33/HOLD pin
is high.
CPU test pin
This pin must be connected to V
SS
during normal operation.
Power supply connections
• P-channel: pull-up MOS
type
• N-channel: intermediate
sink current type (+15 V
withstand voltage in OD)
• P-channel: CMOS type
• N-channel: intermediate
sink current type (+15 V
withstand voltage in OD)
• P-channel: CMOS type
• N-channel: intermediate
sink current type
• Either with pull-up MOS
or n-channel OD output
• Either CMOS or n-channel
OD output
• Either CMOS or n-channel
OD output
• Selection of either
ceramic oscillator or
external clock input.
H
H
H
Normal input
Normal input
User Option Types
1. Port 0 and 1 reset time output level option
The output levels of ports 0 and 1 can be selected from the following two options in 4-bit units.
2. Oscillator circuit option
Note: There is no RC oscillator option.
3. Watchdog timer option
The presence or absence of a watchdog timer can be selected as an option.
4. Port output type option
• One of the following two output circuit options can be selected for each bit in ports P0, P1, P2, P3 (except for the
P33/HOLD pin), P4, P5. P6 and PC.
• The PD comparator inputs and the PE three-value inputs are selected in software.
No. 4677-6/23
LC66354B, 66356B, 66358B
Option Conditions and notes
High level output at reset time Ports 0 and/or 1 in 4-bit sets
Low level output at reset time Ports 0 and/or 1 in 4-bit sets
Option Circuit Conditions and notes
External clock
Ceramic oscillator
This input is a Schmitt specification input.
Option Circuit Conditions and notes
Open drain output
Built-in pull-up resistor output
P2, P3, P5 and P6 are Schmitt inputs.
P2, P3, P5 and P6 are Schmitt inputs.
CMOS outputs (P2, P3, P6 and PC) and pull-up MOS
outputs (P0, P1, P4 and P5) are differentiated according to
the drive capacity of the p-channel transistor.
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Note: 1. Applies to open drain output specification pins. The rating from the “other pin” entry applies for specifications other than the open drain output
specification.
2. Levels up to the free-running oscillation level are allowed for the oscillator input and output pins.
3. Inflow current
4. Outflow current (Applies to the pull-up output specification and CMOS output specification pins.)
5. We recommend using reflow soldering methods to mount the QFP package version.
Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is immersed in a solder bath
(solder dip or spray techniques) are used.
Allowable Operating Ranges at Ta = –30 to + 70°C, VSS= 0 V, VDD= 3.0 to 5.5 V unless otherwise specified
Note: 1. Applies to open drain specification pins. However, the rating for VIH(2) applies to the P33/HOLD pin. Ports P2, P3 and P6 cannot be used as input
pins when CMOS output specifications are used.
2. Applies to open drain specification pins.
3. When PE is used as a three-value input, V
IH
(4), VIMand VIL(4) apply. Port P3 cannot be used as input pins when CMOS output specifications
are used.
No. 4677-7/23
LC66354B, 66356B, 66358B
Parameter Symbol Applicable pins, notes Conditions Ratings Unit Note
Maximum supply voltage V
DD
max V
DD
–0.3 to +7.0 V
Input voltage
V
IN
(1) P2, P3 (except for the P33/HOLD pin), P4, P5, P6 –0.3 to +15.0 V 1
V
IN
(2) Other inputs –0.3 to VDD+ 0.3 V 2
Output voltage
V
OUT
(1) P2, P3 (except for the P33/HOLD pin), P4, P5, P6 –0.3 to +15.0 V 1
V
OUT
(2) Other outputs –0.3 to VDD+ 0.3 V 2
I
ON
P0, P1, P2, P3 (except for the P33/HOLD pin),
20 mA 3
P4, P5, P6, PC
Output current per pin
–IOP(1) P0, P1, P4, P5 2mA 4
–I
OP
(2) P2, P3 (except for the P33/HOLD pin), P6, PC 4 mA 4
ΣI
ON
(1) P0, P1, P2, P3, (except for the P33/HOLD pin), P40, P41 75 mA 3
Total pin current
ΣI
ON
(2) P5, P6, P42, P43, PC 75 mA 3
ΣI
OP
(1) P0, P1, P2, P3 (except for the P33/HOLD pin), P40, P41 25 mA 4
ΣI
OP
(2) P5, P6, P42, P43, PC 25 mA 4
Allowable power dissipation Pd max Ta = –30 to +70°C
DIP42S 600 mW
QFP48E 430 mW 5
Operating temperature Topr –30 to +70 °C
Storage temperature Tstg –55 to +125 °C
Parameter Symbol Applicable pins Conditions
Ratings
Unit Note
min typ max
Operating supply voltage V
DD
V
DD
0.92 ≤ Tcyc ≤ 10 µs 3.0 5.5 V
Memory hold supply voltage V
DD
(H) V
DD
In HOLD mode 1.8 5.5 V
P2, P3 (except for
With the output n-channel
V
IH
(1) the P33/HOLD pin),
transistor off
0.8 V
DD
13.5 V 1
P4, P5, P6
Input high level Voltage
V
IH
(2) P33/HOLD, RES, OSC1
With the output n-channel
0.8 V
DD
V
DD
V2
transistor off
V
IH
(3) P0, P1, PC, PD, PE
With the output n-channel
0.75 V
DD
V
DD
V3
transistor off
V
IH
(4) PE Using three-value input 0.8 V
DD
V
DD
V
Middle level input voltage V
IM
PE Using three-value input 0.4 V
DD
0.6 V
DD
V
Common mode input
V
CMM
(1) PD0, PC2
Using comparator input
1.5 V
DD
V
voltage range
V
CMM
(2) PD1, PD2, PD3, PC3 V
SS
VDD– 1.5 V
P2, P3 (except for
With the output n-channel
V
IL
(1) the P33/HOLD pin),
transistor off
0.2 V
DD
V1
P5, P6, RES, OSC1
Input low level voltage
V
IL
(2) P33/HOLD VDD= 1.8 to 5.5 V 0.2 V
DD
V
V
IL
(3)
P0, P1, P4, PC, PD, PE, With the output n-channel
V
SS
0.25 V
DD
V3
TEST transistor off
V
IL
(4) PE Using comparator input V
SS
0.2 V
DD
V
Operating frequency f
OP
0.4 4.35 MHz
(instruction cycle time) (T
CYC
) (10) (0.92) (µs)
Continued on next page.
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