Sanyo LC587008 Specifications

Ordering number : EN*4435A

63095HA (OT)/N1194JN/D1192JN No. 4435-1/29

Overview

The LC587004, LC587006 and LC587008 are 80-pin low­voltage CMOS 4-bit microprocessors that include LCD
drivers, 2 Kb RAM and 8, 12, or 16 KB ROM on chip.
These microprocessors correspond to the earlier LC5870
series with the 256 by 4-bit on-chip RAM expanded to a
512 by 4-bit capacity.

Applications

• System control and LCD display in CD players, cameras
and radio tuners

• System control and LCD display in miniature test
equipment and consumer health care products

• These microprocessors are optimal for products that
include LCD displays and, in particular, battery operated
products.

• Remote controllers for VCRs and audio equipment

Functions

• Program ROM: 8064 × 16 bits (LC587008), 6144 ×
16 bits (LC587006) and 4096 × 16 bits (LC587004)

• RAM: 512 × 4 bits on chip

• All instructions execute in a single cycle

• Cycle time and operating voltage ranges
— 2 µs cycle time: VDD= 2.8 to 6.0 V

10 µs cycle time: VDD= 2.2 to 6.0 V
122 µs cycle time: VDD= 2.0 to 6.0 V

• Rich set of HALT/HOLD mode clearing and interrupt
functions
— Eight HALT mode clearing functions
— Seven HOLD mode clearing functions
— Seven interrupt functions (all of which can be used

as external interrupts)

— Subroutines can be nested up to eight levels

(including interrupt handling)

— Built-in watchdog timer function

• Powerful hardware for improved processing capacity
— Built-in segment PLA and segment decoder: LCD

panel segments can be handled with no software
processing of the LCD driver outputs. Also, the LCD
drive pins can be switched to function as output

ports.
— Built-in 8-bit synchronous serial I/O circuit
— One 8-bit programmable timer (that can be used as

an event counter)
— One 8-bit programmable reload timer (that can be

used to generate a remote control carrier signal)
— The whole RAM area can be used as working area

(by using the RAM bank register)
— Built-in RAM data pointer
— Built-in clock oscillator and 15-bit divider (also used

to generate the LCD alternating frequency)

• Highly flexible LCD panel drive output pins (35 pins)

LCD panel ................Number of ...........Required

drive type...................segments ..............common pins

1/3 bias 1/4 duty........140 segments.......Four pins

1/3 bias 1/3 duty........105 segments.......Three pins

1/2 bias 1/4 duty........140 segments.......Four pins

1/2 bias 1/3 duty........105 segments.......Three pins

1/2 bias 1/2 duty........70 segments.........Two pins

Static..........................35 segments .........One pin

The LCD output pins can be switched to function as
general-purpose outputs.
— C-MOS type: Up to 35 pins
— P-channel type: Up to 35 pins
— N-channel type: Up to 35 pins

• These microprocessors allow the use of an oscillator
appropriate to the application system specifications.
— Crystal oscillator: 32 kHz, 65 kHz or 38 kHz (for the

time base, system clock or LCD alternating
frequency)

— Ceramic oscillator: 400 kHz to 4 Mhz (for the

system clock and the timers and serial counter)

— RC oscillator: 200 kHz to 1 MHz (for the system

clock and the timers and serial counter)

— External clock (for the system clock and the timers

and serial counter)

Preliminary

LC587008, 587006, 587004

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Single-Chip 4-Bit Microprocessors with LCD Driver,

2 Kb RAM, and 8, 12, or 16 KB ROM on chip

CMOS LSI

Features

• These microprocessors are the top end of the LC5870
series and have the following features.
Faster cycle times
— Cycle time: 2 µs for VDDbetween 4.5 and 6.0 V
— Cycle time: 10 µs for VDDbetween 2.2 and 6.0 V
Low power dissipation HALT mode (typical)
Continuous operation (typical)
— Ceramic filter (CF) 4 MHz (5.0 V) 600 µA 1.7 mA

(cycle time = 2 µs)

— Crystal oscillator 32 kHz (3.0 V, CF stopped) 4.0

µA 20 µA (cycle time = 122 µs)
Improved timer functions
— One 8-bit programmable timer (that can be used as

an event counter)
— One 8-bit programmable reload timer (that can be

used to generate a remote control carrier signal)
— Time base timer (for use as a clock)
— Watchdog timer
Improved standby functions
— Clock standby function (HALT mode), software

switching between low speed mode (low current)

and high speed mode
— Full standby mode (HOLD mode)
— HALT and HOLD modes can be cleared by external

interrupt pins, input ports (up to nine pins) and serial

I/O interrupts
Improved I/O functions
— External interrupt pins
— Up to 9 input and I/O pins that can clear HALT and

HOLD modes
— Up to 24 input ports with built-in software

controllable input resistors (either pull-up or pull-

down specified as mask options)
— Up to 25 input port pins with a built-in floating

prevention circuit
— LCD driver: four common pins and 35 segment pins
— General-purpose I/O ports: 20 pins (of which 12 are

p-channel open drain and 4 are n-channel open

drain)
— General-purpose inputs: five pins
— General-purpose outputs (type 1): four pins (LED

direct drive pins, one internal alarm signal output

pin and one carrier output pin)
— General-purpose outputs (type 2): 35 pins (when all

35 LCD segment port pins are switched over to

function as general-purpose outputs)
— Eight-bit serial I/O port: one set (three pins: input,

output and clock)

• Delivery formats: QFP80 (QIP80) and chip

Package Dimensions

unit: mm

3044B-QFP80A

No. 4435-2/29

LC587008, 587006, 587004

SANYO: QIP80A

[LC587008, 587006, 587004]

Pad Layout

Chip size: 5.12 mm × 5.29 mm
Pad size: 120 µm × 120 µm
Chip thickness: 480 µm (chip products)

Pin Assignments/Pad Names and Coordinates

Note: 1. Pin numbers are for QIP80 package products.

2. Connect the test pins (TST) to V

SS

.

3. Pad numbers 40 and 41 must be left open in the chip specification product.

4. Do not use dip-soldering techniques to mount the QIP80 package versions.

5. For chip products either connect the substrate to V

SS

or leave it open.

No. 4435-3/29

LC587008, 587006, 587004

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

24 1 V

DD

2234 –2319
25 2 CFIN 2234 –1883
26 3 CFOUT 2234 –1701
27 4 S1 2234 –1458
28 5 S2 Input 2234 –1212
29 6 S3 port 2234 –915
30 7 S4 2234 –669
31 8 K1 2234 –284
32 9 K2

I/O port

2234 –101
33 10 K3 2234 81
34 11 K4 2234 264
35 12 M1 2234 448
36 13 M2

I/O port

2234 631
37 14 M3 2234 814
38 15 M4 2234 997
39 16 N1 2234 1352
40 17 N2 Output 2234 1624
41 18 N3 port 2234 1895
42 19 N4 2234 2173
43 20 TST 1958 2449
44 21 Seg 1 1732 2449
45 22 Seg 2 1506 2449
46 23 Seg 3 1280 2449
47 24 Seg 4 1054 2449
48 25 Seg 5 874 2449
49 26 Seg 6 694 2449
50 27 Seg 7 514 2449
51 28 Seg 8 335 2449

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

52 29 Seg 9 155 2449
53 30 Seg 10 –24 2449
54 31 Seg 11 –204 2449
55 32 Seg 12 –384 2449
56 33 Seg 13 –564 2449
57 34 Seg 14 –744 2449
58 35 Seg 15 –923 2449
59 36 Seg 16 –1103 2449
60 37 Seg 17 –1283 2449
61 38 Seg 18 –1463 2449
62 39 Seg 19 –1643 2449
— 40 Test –1821 2449
— 41 Test –2001 2449
63 42 Seg 20 –2362 2449
64 43 Seg 21 –2362 2248
65 44 Seg 22 –2362 1649
66 45 Seg 23 –2362 1468
67 46 Seg 24 –2362 1288
68 47 Seg 25 –2362 1107
69 48 Seg 26 –2362 799
70 49 Seg 27 –2362 618
71 50 Seg 28 –2362 438
72 51 Seg 29 –2362 257
73 52 Seg 30 –2362 77
74 53 Seg 31 –2362 –103
75 54 Seg 32 –2362 –283
76 55 Seg 33 –2362 –464
77 56 Seg 34 –2362 –664

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

78 57 Seg 35 –2362 –824
79 58 COM4 –2362 –1139
80 59 COM3 –2362 –1564

1 60 COM2 –2362 –2319
2 61 COM1 –1912 –2319
3 62 CUP1 –1730 –2319
4 63 CUP2 –1549 –2319
5 64 RES –1327 –2319
6 65 INT –1145 –2319
7 66 SO1 –963 –2319
8 67 SO2 I/O port, –780 –2319

9 68 SO3 SIO port –597 –2319
10 69 SO4 –414 –2319
11 70 A1 –231 –2319
12 71 A2

I/O port

–48 –2319
13 72 A3 134 –2319
14 73 A4 317 –2319
15 74 P1 504 –2319
16 75 P2

I/O port

687 –2319
17 76 P3 870 –2319
18 77 P4 1053 –2319
19 78 XTOUT 1279 –2319
20 79 XTIN 1462 –2319
21 80 V

DD

2 1685 –2319

22 81 V

DD

1 1868 –2319

23 82 V

SS

2050 –2319

System Block Diagram

System Block Diagram for the LC587008, LC587006 and LC587004

RAM: Data memory
ROM: Program memory
DP: Data pointer register
BNK: Bank register
APG: RAM page flags
AC: Accumulator
ALU: Arithmetic and logic unit
B: B register
OPG: ROM page flag
PC: Program counter

IR: Instruction register
STS1: Status register 1
STS2: Status register 2
STS3: Status register 3
STS4: Status register 4
STS5: Status register 5
PLA: Segment data and strobe programmable logic

array

WAIT.C: Waiting time counter

No. 4435-4/29

LC587008, 587006, 587004

Pin Functions

No. 4435-5/29

LC587008, 587006, 587004

Pin I/O

QIP-80

Function Option At reset

Pin No.

V

DD

— 24

V

SS

— 23

VDD1 — 22
V

DD

2 — 21

CUP1 — 3
CUP2 — 4

CFIN Input 25

CFOUT Output 26

XTIN Input 20

XTOUT Output 19

S1 27
S2 28
S3

Input

29

S4 30

K1 31
K2 32
K3

I/O

33

K4 34

M1 35
M2

I/O

36
M3 37
M4 38

A1 11
A2

I/O

12
A3 13
A4 14

P1 15
P2

I/O

16
P3 17
P4 18

Power supply
LCD drive power supply

Switching pin used to supply the LCD drive voltage to the V

DD

1 and

V

DD

2 pins

• Connect a nonpolarized capacitor between CUP1 and CUP2 when
1/2 or 1/3 bias is used.

• Leave open when a bias other than 1/2 or 1/3 is used.

• CF specifications

• RC specifications

• External
specifications

• Not used

• The pull-up or pull­down resistors are
on.

Note: These pins go

to the floating
state when
reset is cleared.

• The pull-up or pull­down resistors are
on.

Note: These pins go

to the floating
state when
reset is cleared.

• Input mode

• Output latch data is
set high.

• 32k specifications

• 65k specifications

• 38k specifications

• Not used

• Transistors to hold
a low or high level

• Selection of either
pull-up or pull­down resistors

• Transistors to hold
a low or high level

• Selection of either
pull-up or pull­down resistors

The same as K1 toK4The same as K1 to

K4

The same as K1 to
K4

The same as K1 to
K4

The same as K1 to
K4

The same as K1 to
K4

System clock oscillator connections

• Ceramic resonator connection (CF specifications)

• RC component connection (RC specifications)

• External signal input pin (CFOUT is left open)
This oscillator is stopped by the execution of a STOP or SLOW
instruction.

Reference calculation (clock specifications, LCD alternating frequency),
system clock oscillator

• 32 kHz crystal resonator connection

• 65 kHz crystal resonator connection
This oscillator is stopped by the execution of a STOP instruction.

Input-only ports

• Input pins used to read data into RAM

• Built-in 7.8 ms and 1.95 ms chatter rejection circuits

• Built-in pull-up/pull-down resistors
Note: The 7.8 ms and 1.95 ms times are the times when ø0 is

32.768 kHz.

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits.
The selection of 7.8 or 1.95 ms is linked to that for the S ports.
Note: The 7.8 ms and 1.95 ms times are the times when ø0 is

32.768 kHz.

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• M4 is used as the external clock input pin in TM2 mode 3.
* The minimum period for the external clock is twice the cycle time.

• Built-in pull-up/pull-down resistors

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• Built-in pull-up/pull-down resistors

I/O ports
Function: The same as pins A1 to A4

Continued on next page.

Continued from preceding page.

No. 4435-6/29

LC587008, 587006, 587004

Continued on next page.

Pin I/O

QIP-80

Function Option At reset

Pin No.

SO1 7
SO2

I/O

8
SO3 9
SO4 10

N1 39
N2

Output

40
N3 41
N4 42

INT Input 6

RES Input 5

TST Input 43

I/O ports
Function: The same as for pins A1 to A4
Pins SO1 to SO3 area also used for the serial interface.

• Use of these pins in serial mode can be selected under program
control.

• Pin functions: SO1: Serial input pin

SO2: Serial output pin

SO3: Serial clock pin
The serial clock pin can be switched between internal and external,
and between rising edge output and falling edge output.

• Transistors to hold
a low or high level

• Selection of either
pull-up or pull­down resistors

• Internal serial clock
divisor selection

I 1/1
II 1/2
III 1/4

The same as for K1
to K4

The output levels on
pins N1 to N4 can be
specified as an option.

• Pins N1 to N4
output circuit type:

I CMOS
II N-channel

open drain

• Pins N1 to N4
output level

I High level
II Low level

• Transistors to hold
a low or high level

• Selection of either
pull-up or pull­down resistors

• Signal conversion
(rising/falling)
selection

* Only when the

input resistor open
specification is
selected

• LCD driver/
general-purpose
output switching

• LCD drive type
switching
— STATIC
— 1/2 bias – 1/2

duty

— 1/2 bias – 1/3

duty

— 1/2 bias – 1/4

duty

— 1/3 bias – 1/3

duty

— 1/3 bias – 1/4

duty

• General-purpose
output circuit
switching
— CMOS
— P-channel

open drain

— N-channel

open drain

• Output latch control
in standby modes

• LCD drive
— All segments on
— All segments off
*: Determined by

mask options

• General purpose
outputs
— High level
— Low level
*: Determined by

mask options

Note: When a

combination of
LCD drive and
general­purpose
outputs, the
output state is

either:
— All lit/high level
— All off/low level.

• These pins go to
the static drive
mode during the
reset period.

Output-only ports

• Output pins used to output data from RAM

• An alarm signal can be output from pin N4. (Note that this is only
when the N4 output latch is low.)

• An alarm signal modulated at 1, 2 or 4 kHz can be output. (These
frequencies are output when ø0 is 32.768 kHz.)

• A carrier signal can be output from N3. (Note that this is only when
the N3 output latch is low.)

Input ports

• External interrupt request inputs

• Input pins used to read data into RAM

• Input detection can be performed on either rising or falling edges.

• Built-in pull-up/pull-down resistors

LSI internal reset input

• The reset input level can be selected to be either high or low.

• Built-in pull-up/pull-down resistors

• Note: The reset pulse must be at least 500 µs.

Test input

• QIP80 products: Connect to V

SS

.

• Chip products: Leave open or connect to V

SS

.

• LCD panel drive/general-purpose output

— LCD panel drive

I STATIC
II 1/2 bias – 1/2 duty
III 1/2 bias – 1/3 duty
IV 1/2 bias – 1/4 duty
V 1/3 bias – 1/3 duty
VI 1/3 bias – 1/4 duty

Types I to V can be specified as mask options.

— General-purpose output mode

I CMOS
II P-channel open drain
III N-channel open drain

Types I to III can be specified as mask options.

• LCD/general-purpose output control is handled by the segment PLA,

and thus program control is not required.

• These pins support output latch control on reset and in standby

states when the oscillators are stopped.

• Arbitrary combinations of LCD drive and general-purpose outputs can

be used.

Seg1,
Seg2 to
Seg35

Output

44,

45 to

78

Continued from preceding page.

Sample Application Circuit

LCD: 1/2 bias – 1/4 duty

No. 4435-7/29

LC587008, 587006, 587004

Pin I/O

QIP-80

Function Option At reset

Pin No.

COM1 2
COM2 1
COM3

Output

80

COM4 79

The static drive
waveform is output
during the reset
period.
* There are cases

where the
alternating
frequency stops for
the CF, RC and
external clock
specifications.
(These cases differ
depending on option
specifications.)

LCD panel drive common polarity outputs
The table below shows how these pins are used depending on the duty
used. (Values for alternating frequency reflect a typical specification of

32.768 MHz for ø0.)

Note: A cross (

✕ ) indicates that the pin is not used with that duty type.

Static duty 1/2 duty 1/3 duty 1/4 duty

COM1

o o o o

COM2 ✕ o o o
COM3 ✕ ✕ o o
COM4 ✕ ✕ ✕ o

Alternation

32 Hz 32 Hz 42.7 Hz 32 Hz

frequency

Oscillator Circuit Options

No. 4435-8/29

LC587008, 587006, 587004

Option Circuit configuration Note

RC and Xtal

CF and Xtal

• 400 kHz (CF)

• 4 MHz (CF)

RC

• The cycle time is four times the f1 period.

• The divider outputs (ø1 to ø15) are used as
the time base, the LCD drive waveform
generation clock, the S and K port
chattering rejection clock and for other
functions.

• OSC1 is stopped when a SLOW instruction
is executed.

• The cycle time is four times n times the f1
period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as
the time base, the LCD drive waveform
generation clock, the S and K port
chattering rejection clock and for other
functions.

• OSC1 is stopped when a SLOW instruction
is executed.

• The cycle time is four times the f1 period.

• The divider outputs (ø1 to ø15) are used as
the LCD drive waveform generation clock,
the S and K port chattering rejection clock
and for other functions.

Continued on next page.

Continued from preceding page.

No. 4435-9/29

LC587008, 587006, 587004

Option Circuit configuration Note

CF

• 400 kHz

• 4 MHz

Xtal

External input

• The cycle time is four times n times the f1
period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as
the LCD drive waveform generation clock,
the S and K port chattering rejection clock
and for other functions.

• The cycle time is four times the f2 period.

• The divider outputs (ø1 to ø15) are used as
the time base, the LCD drive waveform
generation clock, the S and K port
chattering rejection clock and for other
functions.

• The cycle time is four times n times the f1
period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as
the LCD drive waveform generation clock,
the S and K port chattering rejection clock
and for other functions.

Crystal Oscillator Circuit Options

Input Port Options

No. 4435-10/29

LC587008, 587006, 587004

Option Circuit configuration Note

32 kHz oscillator

5 kHz oscillator
38 kHz oscillator

The resistor Rd (200 kΩ typical) for use with a
32 kHz oscillator is built in.

• The cycle time is four times n times the f1
period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as
the time base, the LCD drive waveform
generation clock, the S and K port
chattering rejection clock and for other
functions.

• OSC1 is stopped when a SLOW instruction
is executed.

Option Circuit configuration Note

Selection of either the

• Built-in pull-up
resistor, or the

• Built-in pull-down
resistor option

Selection of high or
low level hold
transistor

The following ports are switched at the same
time

• S1 to S4, K1 to K4, M1 to M4, P1 to P4 SO1
to SO4 and A1 to A4

At reset: The resistors are on during the reset

period.
The resistors are turned off when
reset is cleared.

Options: Either A or B can be selected.

One of A and B must be selected.

When the hold transistors used option is
selected:

• Used to reduce the current flowing in the
pull-up or pull-down resistors when, for
example, a push switch is used for S1 or a
slide switch is used for S2.

• For input open specification versions, the
resistors are turned on before the input is
read, the input state is read and then the
resistors are turned off. If the input is
floating at this point the high or low level
hold transistor operates to hold the value
read.

When the hold transistors unused option is
selected:

• Use with the pull-up or pull-down resistor in
the on state.

• Select hold transistors unused when
connecting to external control signals and
the connections will never be floating

Combination examples

Type 1 2 3 4
Pull-up resistor (A) On On
Pull-down resistor (B) On On
High level hold transistor (C) On
Low level hold transistor (D) On

INT Pins

RES Pin

Pins N1 to N4

No. 4435-11/29

LC587008, 587006, 587004

Option Circuit configuration Note

Pull-up resistor, pull­down resistor or
resistor open selection

High or low level hold
transistor selection

Rising edge or falling
edge detection
selection

Built-in resistor selection

• Pull-up resistor used

• Pull-down resistor used

• Used open

Input signal level hold transistor selection

• High level hold transistor used

• Low level hold transistor used

• Level hold transistors unused

Signal change edge detection switching

• Change on rising signal

• Change on falling signal

Option Circuit configuration Note

Pull-up resistor, pull­down resistor or
resistor open and
reset level selection

Built-in resistor and polarity selection

• Pull-up resistor connected, low level reset

• Pull-down resistor connected, high level
reset

• Resistors open, low level reset

• Resistors open, high level reset

Option Circuit configuration Note

N-channel/CMOS
selection

• Selection of CMOS or n-channel open drain
circuit type

• Pins N1 to N4 can be specified
independently

• The output level during reset can be
specified.
— High level
— Low level

Fifteen-Stage Divider Overflow Time

K Input Port Options

No. 4435-12/29

LC587008, 587006, 587004

Option Circuit configuration Note

• 1000 ms/250 ms

• 500 ms/125 ms

A 15-stage (15-bit) divider is provided on chip
to count the reference time.
One of two types of divider overflow detection
can be selected as a mask option and a
further selection of two types can be made
under program control. One of these mask
options must be specified.

Option Circuit configuration Note

Pull-up/pull-down
resistor selection

When the pull-up/pull-down resistor selection
is made, the K port input detection switching
gate is switched accordingly.
A: When all of K1 to K4 are high and even

one pin goes low a signal is applied to the
edge detection circuit. (Applies to the pull­up specifications.)
Note: When even one of the K1 to K4 pins

is low, the edge detection circuit will
not operate for any combination of
high or low values on the other pins.

B: The opposite of item A

Mask Option Overview

1. Port resistor selection (ports S, K, P, M, A and SO)

• Pull-up resistor specification

• Pull-down resistor specification

2. S port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

3. K port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

4. M port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

5. P port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

6. A port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

7. SO port high or low level hold transistors

• Level hold transistors used

• No level hold transistors

8. INT pin resistor selection and signal edge selection

• Pull-up resistor (negative edge)

• Pull-down resistor (positive edge)

• Open (negative edge)

• Open (positive edge)

9. INT pin level hold transistor selection

• Low or high level hold transistors used

• No low or high level hold transistors

10. RES pin

• Pull-up resistor (low level reset)

• Pull-down resistor (high level reset)

• Open (low level reset)

• Open (high level reset)

11. N1 pin

• N-channel open drain type

• CMOS type

12. N2 pin

• N-channel open drain type

• CMOS type

13. N3 pin

• N-channel open drain type

• CMOS type

No. 4435-13/29

LC587008, 587006, 587004

14. N4 pin

• N-channel open drain type

• CMOS type

15. N port initial level

• High level

• Low level

16. OSC specifications

• CF only (ceramic filter)

• RC only (resistor and capacitor oscillator)

• Crystal only (32 to 65 kHz crystal oscillator)

• CF + crystal

• RC + crystal

• External + crystal

17. CF/External

• 400 kHz or 800 kHz

• 1 MHz, 2 MHz or 4 MHz

18. Crystal oscillator

• 32 kHz

• 65 kHz

• 38 kHz

19. Fifteen-bit counter overflow

• ø0/2048 or ø/8192

• ø0/4096 or ø0/16384

20. Serial I/O internal clock period

• Cycle time × 1 × 2

• Cycle time × 2 × 2

• Cycle time × 4 × 2

21. LCD driver

• Static

• 1/2 bias – 1/2 duty

• 1/2 bias – 1/3 duty

• 1/2 bias – 1/4 duty

• 1/3 bias – 1/3 duty

• 1/3 bias – 1/4 duty

22. LCD alternating frequency

• Slow

• Typical

• Fast

23. Internal reset circuit

• Selection

• Disabled

24. Segment ports at reset
LCD drive pins

• All on

• All off
CMOS, p/n-channel type pins

• High level

No. 4435-14/29

LC587008, 587006, 587004

Internal Register Functions

No. 4435-15/29

LC587008, 587006, 587004

Symbol R/W Function

Initialization
value at reset

PC

ROM

RAM

—

R/O

R/W

Program counter
The PC is a 13-bit counter that indicates the address in program memory (ROM) of the next instruction to execute.
Normally the PC is incremented on every instruction cycle in the range 000H to 1F7FH. (Addresses in the range 1F80
to 1FFF are reserved for testing and cannot be used by user programs.) However, data values are loaded into the PC
by the execution of branch and subroutine instructions and on the occurrence of interrupts or an initial reset. The table
below describes the data loaded for these operations.

Page: the ROM page flags, which take 2048 locations as a single page

The page is specified with the MROPF and SROPF instructions.

P00 to P10: Bits in the instruction code (i.e., immediate data)

Program memory
The ROM memory consists of 4096 x 16 bits (4 kwords or 8 kbytes) in the LC587004, 6144 x 16 bits (6 kwords or 12
kbytes) in the LC587006 and 8064 x 16 bits (8 kwords or 16 kbytes) in the LC587008. ROM hold user programs to be
executed.

Data memory
These microprocessors provide an on-chip RAM that consists of 512 × 4 bits (2 Kb). This RAM is accessed as two
256 × 4-bit pages.
RAM addresses can be specified in four ways as listed below.

• Directly specified at 00H to FFH (immediate addressing)

• Indirect specification using the 8-bit data pointer.

• Indirect specification by the 4-bit RAM bank register multiplied by 10H plus immediate data in the range 0 to FH.

• Indirect specification by the 4-bit RAM bank register multiplied by 10H plus 8H plus immediate data in the range 0 to
FH.

Writing to RAM is always performed through the accumulator.

PC

PC12 PC11 PC10

PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Operation
Initializing reset 0 0 0 0 0 0 0 0 0 0 0 0 0

INT pin external interrupt

0 0 0 0 0 0 0 1 0 0 0 0 0

S/K pin external interrupt

0 0 0 0 0 0 0 1 0 1 0 0 0

Timer 1 or timer 2 internal

0 0 0 0 0 0 0 1 1 0 0 0 0

interrupt
Serial counter internal interrupt

0 0 0 0 0 0 0 1 1 1 0 0 0

or SO4 pin external interrupt
Unconditional jump (JMP) Page P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Conditional jump

(BAB0, BAB1, BAB2, BAB3, Page P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
BAZ, BANZ, BCH, BCNH)

Call instruction (CALL) Page P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Return instruction (RTS, RTSR) CALL address + 1

Undefined

Continued on next page.

Continued from preceding page.

No. 4435-16/29

LC587008, 587006, 587004

Symbol R/W Function

Initialization
value at reset

RAM

AC

B

DP

R/W

R/W

R/W

R/W

Note: In case B, data pointer RAM address specification is illegal if the RAM address specification (the DPH

immediate data) has the same value as the RAM bank register (BNK). In this case immediate specification is
allowed.
Example: If an IPS 10H instruction is executed when the data pointer flag is set, DPH is 5H, DPL is 3 H and the

RAM bank register (BNK) is 1H, then the contents of the S port will be written to RAM location 10H.

Example: If BNK and DPH differ, then the following operation will be performed.

If an IPS 10H instruction is executed when DPF is 1, DPH is 5, DPL is 3 and BNK is 4, then the
contents of the S port will be written to RAM location 53H.

Accumulator

B register

This register is used in combination with RAM as a pair for output to the LCD ports and for timer 2, serial counter and
data pointer I/O.

Data pointer

The data pointer register functions as a data pointer when the data pointer flag (DPF) is set, allowing control of the on­chip RAM.

Undefined

Undefined

Undefined

Undefined

Continued on next page.

Continued from preceding page.

No. 4435-17/29

LC587008, 587006, 587004

Symbol R/W Function

Initialization
value at reset

STACK

BNK

APG

TIM

TIM1
TIM2

R/W

R/W

R/W

R/W

Stack pointer
The stack consists of eight 14-bit registers and thus can be set to a depth of up to eight levels.
The stack pointer is incremented by CALL instructions and interrupts, and decremented by RTS, RTSR and POP
instructions.

P0 to P11: Program counter (PC)
DPF: Data pointer flag

Bank register
The bank register is a 4-bit register that divides RAM (from 00H to FFH) into 16 sections and is used in moving RAM
data, immediate operations and setting the data pointer.

Example: ADD*_5,10.....If BNK is 6 then the operation performed will be: RAM(65H) + 10 → AC → RAM(65H).

RAM page flags
The RAM page flags consist of 2 bits that allow RAM to be expanded in 256 4-bit pages to a total of 1024 4-bit
locations.
Note: Pages 2 and 3 cannot be used by the LC587004, LC587006 and LC587008.

Timer counters
The timers consist of 8-bit down counters. (timer 1 and timer 2)
Timer setting is performed in 8-bit units for immediate data. (timer 1 and timer 2)
Reading and writing the lower 4 bits of a timer counter is performed through a RAM location. (timer 2 only)
Reading and writing the upper 4 bits of a timer counter is performed using the B register. (timer 2 only)

01H

00H

00H

Undefined

Continued on next page.

Continued from preceding page.

No. 4435-18/29

LC587008, 587006, 587004

Symbol R/W Function

Initialization
value at reset

SIO

OPG

STS1

STS2

R/W

R/W

R/O

R/W

Serial counter
The serial counter is an 8-bit shift register.
Reading and writing the lower 4 bits of the serial counter is performed through a RAM location.
Reading and writing the upper 4 bits of the serial counter is performed using the B register.

ROM page flags
The ROM page flags consist of 2 bits that allow ROM to be expanded in 2048 16-bit pages to a total of 8063 16-bit
locations.
In the LC587004 the legal values are 0 and 1, in the LC587006 the legal values are 0 to 2 and in the LC587008 the
legal values are 0 to 3.
(The operation when an illegal value is used is undefined.)

Status register 1 (STS1)
Status register 1 is a 4-bit register whose bits are used as shown below.

Status register 2 (STS2)
Status register 2 is a 4-bit register that is used for serial counter control and state confirmation.

ICF: High when the internal clock is used
OSELF: High when the SO2 pin is set to the high impedance state (Z).

Low when SO2 is set to the CMOS or n-channel open drain state.
SIOF: High when used as serial I/O
CSTF: High on serial counter start

Low during serial counter operation

Undefined

00H

00H

00H

Continued on next page.

Continued from preceding page.

No. 4435-19/29

LC587008, 587006, 587004

Symbol R/W Function

Initialization
value at reset

STS3

STS4

STS5

R/O

R/O

R/O

Status register 3 (STS3)
Status register 3 is a 4-bit register that is used to confirm the HALT and STOP clear conditions.

SCF0: Set to 1 if there was a signal change on the INT pin.
SCF1: Set to 1 if there was a signal change on the K port.
SCF2: Set to 1 if any of the flags in STS4 is set.
SCF3: Set to 1 if there was a signal change on the S port.
Note: SCF0 is used when enabled by an SF2-1 instruction.

SCF1 and SCF3 are used when enabled by an SSW instruction.

Status register 4 (STS4)
Status register 4 is a 4-bit register that is used to confirm the HALT and STOP clear conditions.

SCF4: Divider overflow
SCF5: Timer 1 underflow
SCF6: Timer 2 underflow
SCF7: Serial counter overflow or signal change on SO4

Status register 5 (STS5)
Status register 5 is a 4-bit register whose bits are used as shown below.

Bits 0 and 1: These bits are always 0 and cannot be used.
INTIN: Reflects in the input data on the INT pin.
STBF: Strobe flag for the segment port

(Set to 1 for 00 to 0F and to 0 for 10 to 1E.)

00H

00H

00H

Specifications

The electrical characteristics specified here are provisional and subject to change.

Absolute Maximum Ratings at VSS= 0 V, Ta = 25°C

Allowable Operating Ranges at VSS= 0 V, Ta = –30 to +70°C

Note: In the state where the CF/RC oscillator and/or the crystal oscillator are completely stopped and the internal circuits are completely stopped.

No. 4435-20/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

V

DD

–0.3 +7.0 V

Maximum supply voltage V

DD

1 –0.3 V

DD

V

V

DD

2 –0.3 V

DD

V

V

I

(1) Allowed in the specified circuit (Figure 1), XTIN, CFIN Allowed up to the generated voltage

Maximum input voltage

V

I

(2)

S1 to S4, K1 to K4, P1 to P4, SO1 to SO4, A1to A4,RES,

–0.3 VDD+ 0.3 V

INT, TST, (With the K, P, M, SO and ports in input mode)

VO(1)

Allowed in the specified circuit (Figure 1), XTOUT,

Allowed up to the generated voltage

CFOUT

Maximum output voltage

K1 to K4, P1 to P4, SO1 to SO4, A1 to A4, N1 to N4,

V

O

(2) CUP1, CUP2, Seg1 to Seg35, COM1 to COM4 –0.3 VDD+ 0.3 V

(With the K, P, M, SO and A ports in output mode)

VO(3) Open drain specifications, N1 to N4 (N ch) –0.3 +13 V

I

O

(1)

N1 to N4

0 +15 mA

I

O

(2)

Per pin

–10 0 mA

Output pin current

I

O

(3)

K1 to K4, P1 to P4, M1 to M4, SO1 to SO4,

0 5 mA

I

O

(4)

A1 to A4

–5 0 mA

Σ I

O

(1)

Total current K1 to K4, P1 to P4, M1 to M4, SO1 to

70 mA

Σ I

O

(2)

for all pins SO4, A1 to A4, N1 to N4, Seg1 to Seg35

–70 mA
Allowable power dissipation Pd max QIP80 flat package 500 mW
Operating temperature Topg –30 +70 °C
Storage temperature Tstg –55 +125 °C

Parameter Symbol Conditions min typ max Unit

LCD unused specifications: V

DD

1 = VDD2 = V

DD

2.0 6.0 V

Supply voltage V

DD

Static specifications: VDD1 = VDD2 = V

DD

2.0 6.0 V

1/2 bias specifications: V

DD

1 = VDD2 ≈ 2 × 1/2 V

DD

2.8 6.0 V

1/3 bias specifications: V

DD

1 ≈ 2 × 1/3 VDD,

2.8 6.0 V

V

DD

2 ≈ 1/3 V

DD

Hold supply voltage V

HD

Voltage required to hold the contents of RAM and

2.0 V

DD

V

the registers*

Input high level voltage VIH1 0.7 V

DD

V

DD

V

Input low level voltage VIL1 0 0.3 V

DD

V

Input high level voltage V

IH

2

RES pin

0.75 V

DD

V

DD

V

Input low level voltage V

IL

2 0 0.25 V

DD

V

Input high level voltage V

IH

3

CFIN pin

0.75 V

DD

V

DD

V

Input low level voltage V

IL

3 0 0.25 V

DD

V

Operating frequency 1 fopg1 V

DD

= 2.0 to 6.0 V, 32 kHz

XTIN/XTOUT crystal

32 33 kHz

Operating frequency 2 fopg2 V

DD

= 2.2 to 6.0 V. 38 kHz

oscillator

37 39 kHz

Operating frequency 3 fopg3 V

DD

= 2.2 to 6.0 V, 65 kHz 60 70 kHz

Operating frequency 4 fopg4 V

DD

= 2.2 to 6.0 V 190 810 kHz

Operating frequency 5 fopg5 V

DD

= 2.5 to 6.0 V

CFIN/CFOUT CF specifications

190 1200 kHz

Operating frequency 6 fopg6 V

DD

= 2.5 to 6.0 V 190 2300 kHz

Operating frequency 7 fopg7 V

DD

= 2.8 to 6.0 V 190 4200 kHz

Operating frequency 8 fopg8 V

DD

= 4.0 to 6.0 V, CFIN/CFOUT RC specifications 100 1500 kHz

Operating frequency 9 fopg9 V

DD

= 2.0 to 6.0 V, CFIN/CFOUT EXT specifications 190 800 kHz

V

DD

= 3.0 to 6.0 V, O1/SO3 pins (in serial mode),

Operating frequency 10 fopg10

Rising and falling edges on the input signals and

DC 200 kHz

clock waveform of the SO1/SO3 pins (in serial mode)
must be 10 µs or less.

S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4,
A1 to A4, INT, (With the K, P, M, SO and ports in input
mode)

Electrical Characteristics at VDD= 2.5 to 3.2 V, VSS= 0 V, Ta = –30 to +70°C

Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.

No. 4435-21/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

R

IN

1 A VIN= 0.2 VDD, low level hold transistor* Figure 2 60 300 1200 kΩ

R

IN

1 B VIN= VDD, pull-down resistor* Figure 2 30 150 500 kΩ

R

IN

1 C VIN= 0.8 VDD, high level hold transistor* Figure 2 60 300 1200 kΩ

R

IN

1 D VIN= VSS, pull-up resistor* Figure 2 30 150 500 kΩ

R

IN

2 A VIN= 0.2 VDD, the INT pin low level hold transistor 60 300 1200 kΩ

R

IN

2 B VIN= VDD, The INT pin pull-down resistor 300 1500 5000 kΩ

R

IN

2 C VIN= 0.8 VDD, the INT pin high level hold transistor 60 300 1200 kΩ

R

IN

2 D VIN= VSS, the INT pin pull-up resistor 300 1500 5000 kΩ

R

IN

3 VIN= VDD, the RES pin pull-down resistor 10 30 50 kΩ

R

IN

4 VIN= VSS, the RES pin pull-up resistor 10 30 50 kΩ

R

IN

5 VIN= VDD, the TST pin pull-down resistor 60 250 1000 kΩ

R

IN

1 A

V

IN

= 0.2 VDD, low level hold transistor*

80 300 1200 kΩ

Figure 2

Input resistance

RIN1 B VIN= VDD, pull-down resistor* Figure 2 40 150 500 kΩ
R

IN

1 C

V

IN

= 0.8 VDD, high level hold transistor*

80 300 1200 kΩ

Figure 2

R

IN

1 D VIN= VSS, pull-up resistor* Figure 2 40 150 500 kΩ

R

IN

2 A

V

IN

= 0.2 VDD, the INT pin low level hold

80 300 1200 kΩ

transistor V

DD

= 2.5 V

R

IN

2 B VIN= VDD, the INT pin pull-down resistor 400 1500 5000 kΩ

R

IN

2 C

V

IN

= 0.8 VDD, the INT pin high level hold

80 300 1200 kΩ

transistor

R

IN

2 D VIN= VSS, the INT pin pull-up resistor 400 1500 5000 kΩ

R

IN

3 VIN= VDD, the RES pin pull-down resistor 10 30 50 kΩ

R

IN

4 VIN= VSS, the RES pin pull-up resistor 10 30 50 kΩ

R

IN

5 VIN= VDD, the TST pin pull-down resistor 80 250 1000 kΩ

Output high level voltage V

OH

(1) IOH= –500 µA

N1 to N4

VDD– 0.5 V

Output low level voltage V

OL

(1) IOL= 1.0 mA 0.5 V

Output high level voltage V

OH

(2)

I

OH

= –400 µA K1 to K4, P1 to P4, M1 to M4, SO1 to

V

DD

– 0.5 V

SO4, A1 to A4 (with the K, P, M, SO

Output low level voltage V

OL

(2) IOL= 400 µA and A ports in output mode) 0.5 V

Output off leakage current  I

OFF

 VOH= 10.5 V N1 to 4 (open specifications), Figure 10 1.0 µA
Segment port output impedances
[In CMOS output port mode]
Output high level voltage V

OH

(3) IOH= –100 µA

Seg1 to Seg35

VDD– 0.5 V

Output low level voltage V

OL

(3) IOL= 100 µA 0.5 V
[In p-channel open-drain output port mode (See Figure 11.)]
Output high level voltage V

OH

(3) IOH= –100 µA

Seg1 to Seg35

VDD– 0.5 V

Output off leakage current  I

OFF

 VOL= V

SS

1.0 µA
[In n-channel open-drain output port mode (See Figure 11.)]
Output low level voltage V

OL

(3) IOL= 100 µA

Seg1 to Seg35

0.5 V
Output off leakage current  I

OFF

 VOH= V

DD

1.0 µA
[Static drive]
Output high level voltage V

OH

(4) IOH= –20 µA, Seg1 to Seg35 VDD– 0.2 V

Output low level voltage V

OL

(4) IOL= 20 µA 0.2 V

Output high level voltage V

OH

(5) IOH= –100 µA, COM1 VDD– 0.2 V

Output low level voltage V

OL

(5) IOL= 100 µA 0.2 V

Electrical Characteristics at VDD= 3.0 to 4.5 V, VSS= 0 V, Ta = –30 to +70°C

Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.

No. 4435-22/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

R

IN

1 A VIN= 0.2 VDD, low level hold transistor* Figure 2 35 200 800 kΩ

R

IN

1 B VIN= VDD, pull-down resistor* Figure 2 15 80 300 kΩ

R

IN

1 C VIN= 0.8 VDD, high level hold transistor* Figure 2 35 200 800 kΩ

R

IN

1 D VIN= VSS, pull-up resistor* Figure 2 15 80 300 kΩ

R

IN

2 A VIN= 0.2 VDD, the INT pin low level hold transistor 35 200 800 kΩ

R

IN

2 B VIN= VDD, The INT pin pull-down resistor 150 800 3000 kΩ

R

IN

2 C VIN= 0.8 VDD, the INT pin high level hold transistor 35 200 800 kΩ

R

IN

2 D VIN= VSS, the INT pin pull-up resistor 150 800 3000 kΩ

R

IN

3 VIN= VDD, the RES pin pull-down resistor 10 30 50 kΩ

R

IN

4 VIN= VSS, the RES pin pull-up resistor 10 30 50 kΩ

R

IN

5 VIN= VDD, the TST pin pull-down resistor 25 130 500 kΩ

R

IN

1 A

V

IN

= 0.2 VDD, low level hold transistor*

40 200 800 kΩ

Figure 2

Input resistance

RIN1 B VIN= VDD, pull-down resistor* Figure 2 20 80 300 kΩ
R

IN

1 C

V

IN

= 0.8 VDD, high level hold transistor*

40 200 800 kΩ

Figure 2

R

IN

1 D VIN= VSS, pull-up resistor* Figure 2 20 80 300 kΩ

R

IN

2 A

V

IN

= 0.2 VDD, the INT pin low level hold

V

DD

= 40 300 800 kΩ

transistor

3.0 to 4.0 V

R

IN

2 B VIN= VDD, the INT pin pull-down resistor 200 800 3000 kΩ

R

IN

2 C

V

IN

= 0.8 VDD, the INT pin high level hold

40 200 1200 kΩ

transistor

R

IN

2 D VIN= VSS, the INT pin pull-up resistor 200 800 3000 kΩ

R

IN

3 VIN= VDD, the RES pin pull-down resistor 10 30 50 kΩ

R

IN

4 VIN= VSS, the RES pin pull-up resistor 10 30 50 kΩ

R

IN

5 VIN= VDD, the TST pin pull-down resistor 30 130 500 kΩ

Output high level voltage V

OH

(1) IOH= –500 µA

N1 to N4

VDD– 0.5 V

Output low level voltage V

OL

(1) IOL= 1.0 mA 0.5 V

Output high level voltage V

OH

(2)

I

OH

= –400 µA K1 to K4, P1 to P4, M1 to M4, SO1 to

V

DD

– 0.5 V

SO4, A1 to A4 (with the K, P, M, SO

Output low level voltage V

OL

(2) IOL= 400 µA and A ports in output mode) 0.5 V

Output off leakage current  I

OFF

 VOH= 10.5 V N1 to 4 (open specifications), Figure 10 1.0 µA
Segment port output impedances
[In CMOS output port mode]
Output high level voltage V

OH

(3) IOH= –100 µA

Seg1 to Seg35

VDD– 0.5 V

Output low level voltage V

OL

(3) IOL= 100 µA 0.5 V
[In p-channel open-drain output port mode (See Figure 11.)]
Output high level voltage V

OH

(3) IOH= –100 µA

Seg1 to Seg35

VDD– 0.5 V

Output off leakage current  I

OFF

 VOL= V

SS

1.0 µA
[In n-channel open-drain output port mode (See Figure 11.)]
Output low level voltage V

OL

(3) IOL= 100 µA

Seg1 to Seg35

0.5 V
Output off leakage current  I

OFF

 VOH= V

DD

1.0 µA
[Static drive]
Output high level voltage V

OH

(4) IOH= –20 µA, Seg1 to Seg35 VDD– 0.2 V

Output low level voltage V

OL

(4) IOL= 20 µA 0.2 V

Output high level voltage V

OH

(5) IOH= –100 µA, COM1 VDD– 0.2 V

Output low level voltage V

OL

(5) IOL= 100 µA 0.2 V
[1/2 bias drive]
Output high level voltage V

OH

(4) IOH= –20 µA

Seg1 to Seg35 V

DD

– 0.2 0.2 V

Output low level voltage V

OL

(4) IOL= 20 µA
Output high level voltage V

OH

(5) IOH= –100 µA VDD– 0.2 V

Output middle level voltage V

OM

IOH= –100 µA

COM1 to COM4 V

DD

/2 – 0.2 VDD/2 + 0.2 V

I

OL

= 100 µA

Output low level voltage V

OL

(5) IOL= 100 µA 0.2 V

Continued on next page.

Continued from preceding page.

No. 4435-23/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

[1/3 bias drive: About 1/10 of the rating for V

DD

= 4.5 to 6.0 V]

Supply leakage current I

LEK

(1) VDD= 3.0 V, Ta = 25°C, Figure 3 0.2 1.0 µA
Supply leakage current I

LEK

(2) VDD= 3.0 V, Ta = 50°C, Figure 3 1.0 5.0 µA

V

DD

= 3.0 V

Input leakage current I

OFF

VIN= V

DD

1.0 µA

VIN= V

SS

–1.0 µA

Output voltage 1 VDD1-(1)

V

DD

= 3.0 V, C1 = C2 = 0.1 µF, VDD1 = VO,

1.3 1.5 1.7 V

1/2 bias, fopg = 32.768 kHz, Figure 4

 I

DD

 1-1

V

DD

= 3.0 V,

4.0 8.0 µA

Supply current 1

Ta = 25°C

 I

DD

 1-2

V

DD

= 3.0 V,

20 µA

Ta = 50°C

 I

DD

 2-1

V

DD

= 3.0 V,

6.0 10 V

Supply current 2

Ta = 25°C

 I

DD

 2-2

V

DD

= 3.0 V,

30 µA

Ta = 50°C

 I

DD

 3-1

V

DD

= 3.0 V,

150 300 µA

Supply current 3

Ta = 25°C

 I

DD

 3-2

V

DD

= 3.0 V,

500 µA

Ta = 50°C

Oscillator start voltage  V

STT

 T

STT

≤ 5 s 2.2 V

Oscillator hold voltage  V

HOLD

 2.0 6.0 V

Oscillator start time  T

STT

 VDD= 2.2 V 5 s

Oscillator stability ∆f

V

DD

= 2.95 to

3 ppm

3.05 V

Oscillator start voltage  V

STT

 T

STT

≤ 5 s 2.4 V

Oscillator hold voltage  V

HOLD

 2.2 6.0 V

Oscillator start time  T

STT

 VDD= 2.4 V 5 s

Oscillator start voltage  V

STT

 T

STT

≤ 30 ms 2.4 V

Oscillator hold voltage  V

HOLD

 2.2 6.0 V

Oscillator start time  T

STT

 VDD= 2.4 V 30 ms

Oscillator start voltage  V

STT

 T

STT

≤ 30 ms 2.4 V

Oscillator hold voltage  V

HOLD

 2.2 6.0 V

Oscillator start time  T

STT

 VDD= 2.4 V 30 ms

Oscillator correction capacitance Cd V

DD

= 3.0 V, XTOUT pin (built-in) 16 20 24 pF

CF oscillator specifications,
using an 800 kHz ceramic filter,
Ccg = Ccd = 220 pF or 100 pF, Figure 7

CF oscillator specifications,
using a 400 kHz ceramic filter,
Ccg = Ccd = 330 pF, Figure 7

Crystal oscillator specifications,
using a 38 or 65 kHz crystal,
XCg = 10 pF, CI ≤ 25 kΩ, Figure 6

Crystal oscillator specifications,
using a 32 kHz crystal,
Cg = 20 pF, CI ≤ 25 kΩ, Figure 6

CF oscillator specifications,
CF: 400 kHz, Ccg = Ccd = 330 pF,
HALT mode, Figure 7

Crystal oscillator specifications, crystal:
38 or 65 kHz, Cg = 10 pF, CI = 25 kΩ,
HALT mode, Figure 6, LCD = 1/3 bias

Crystal oscillator specifications, crystal:
32 kHz, Cg = 20 pF, CI = 25 kΩ, HALT
mode, Figure 6, LCD = 1/3 bias

S1 to S4, K1 to K4, P1 to P4, M1 to M4,
SO1 to SO4, A1 to A4, INT, RES (with
the K, P, M, SO and A ports in input
mode, and with open specifications for
the INT and RES pins)

Electrical Characteristics at VDD= 4.5 to 6.0 V, VSS= 0 V, Ta = –30 to +70°C

Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.

No. 4435-24/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

R

IN

1 A VIN= 0.2 VDD, low level hold transistor* Figure 2 30 120 500 kΩ

R

IN

1 B VIN= VDD, pull-down resistor* Figure 2 10 50 200 kΩ

R

IN

1 C VIN= 0.8 VDD, high level hold transistor* Figure 2 30 120 500 kΩ

R

IN

1 D VIN= VSS, pull-up resistor* Figure 2 10 50 200 kΩ

R

IN

2 A VIN= 0.2 VDD, the INT pin low level hold transistor 30 120 500 kΩ

Input resistance R

IN

2 B VIN= VDD, The INT pin pull-down resistor 100 500 2000 kΩ

R

IN

2 C VIN= 0.8 VDD, the INT pin high level hold transistor 30 120 500 kΩ

R

IN

2 D VIN= VSS, the INT pin pull-up resistor 100 500 2000 kΩ

R

IN

3 VIN= VDD, the RES pin pull-down resistor 10 30 50 kΩ

R

IN

4 VIN= VSS, the RES pin pull-up resistor 10 30 50 kΩ

R

IN

5 VIN= VDD, the TST pin pull-down resistor 20 70 300 kΩ
Output high level voltage V

OH

(1) IOH= –5.0 mA

N1 to N4

VDD– 0.5 V

Output low level voltage V

OL

(1) IOL= 10.0 mA 0.5 V
Output high level voltage V

OH

(2) IOH= –1.0 mA VDD– 0.5 VDD– 0.2 V

Output low level voltage VOL(2) IOL= 2.0 mA 0.2 0.5 V

Output off leakage current  I

OFF

 VOH= 10.5 V 1.0 µA

Segment port output impedances
[In CMOS output port mode]
Output high level voltage V

OH

(3) IOH= –500 µA

Seg1 to Seg35

VDD– 0.5 VDD– 0.2 V

Output low level voltage V

OL

(3) IOL= 500 µA 0.5 V
[In p-channel open-drain output port mode (See Figure 11.)]
Output high level voltage V

OH

(4) IOH= –500 µA

Seg1 to Seg35

VDD– 0.5 VDD– 0.2 V

Output off leakage current  I

OFF

 VOL= V

SS

1.0 µA
[In N-channel open-drain output port mode (See Figure 11.)]
Output low level voltage V

OL

(4) IOL= 500 µA

Seg1 to Seg35

0.2 0.5 V

Output off leakage current  I

OFF

 VOH= V

DD

1.0 µA
[Static drive]
Output high level voltage V

OH

(4) IOH= –40 µA

Seg1 to Seg35

VDD– 0.2 V

Output low level voltage V

OL

(4) IOL= 40 µA 0.2 V

Output high level voltage V

OH

(6) IOH= –400 µA

COM1

VDD– 0.2 V

Output low level voltage V

OL

(6) IOL= 400 µA 0.2 V
[1/2 bias drive]
Output high level voltage V

OH

(4) IOH= –40 µA

Seg1 to Seg35

VDD– 0.2 V

Output low level voltage V

OL

(4) IOL= 40 µA 0.2 V
Output high level voltage V

OH

(6) IOH= –400 µA VDD– 0.2 V

Output middle level voltage V

OM

2-1

I

OH

= –400 µA

COM1 to COM4 V

DD

/2 – 0.2 VDD/2 + 0.2 V

I

OL

= 400 µA

Output low level voltage V

OL

(6) IOL= 400 µA 0.2 V
[1/3 bias drive]
Output high level voltage V

OH

(4) IOH= –40 µA VDD– 0.2 V

V

OM

1-1 IOH= –40 µA

2 V

DD

/3 2 VDD/3

V

Output middle level voltage Seg1 to Seg35

– 0.2 + 0.2

V

OM

1-2 IOL= 40 µA VDD/3 – 0.2 VDD/3 + 0.2 V

Output low level voltage V

OL

(4) IOL= 40 µA 0.2 V
Output high level voltage V

OH

(6) IOH= –400 µA VDD– 0.2 V

V

OM

2-1 IOH= –400 µA

2 V

DD

/3 2 VDD/3

V

Output middle level voltage COM1 to COM4

– 0.2 + 0.2

V

OM

2-2 IOL= 400 µA VDD/3 – 0.2 VDD/3 + 0.2 V

Output low level voltage V

OL

(6) IOL= 400 µA 0.2 V

K1 to K4, P1 to P4, M1 to M4, SO1 to
SO4, A1 to A4 (with the K, P, M, SO
and A ports in output mode),
N1 to N4 (open specifications)
Figure 10

Continued on next page.

Continued from preceding page.

No. 4435-25/29

LC587008, 587006, 587004

Parameter Symbol Conditions min typ max Unit

I

OP

-1

V

DD

= 3 V, Ta = 25°C, 32 kHz crystal oscillator,

20 30 µA

LCD = 1/3 bias, Figure 6

I

OP

-2

V

DD

= 5 V, Ta = 25°C, 32 kHz crystal oscillator,

40 60 µA

LCD = 1/3 bias, Figure 6

Operating current

I

OP

-3 VDD= 3 V, Ta = 25°C, 400 kHz, CF oscillator, Figure 6 240 300 µA

I

OP

-4 VDD= 5 V, Ta = 25°C, 400 kHz, CF oscillator, Figure 6 620 780 µA

I

OP

-5 VDD= 3 V, Ta = 25°C, 1 MHz, CF oscillator, Figure 6 350 480 µA

I

OP

-6 VDD= 5 V, Ta = 25°C, 1 MHz, CF oscillator, Figure 6 850 1200 µA

I

OP

-7 VDD= 5 V, Ta = 25°C, 4 MHz, CF oscillator, Figure 6 1700 2500 µA

Supply leakage current I

LEK

(1) VDD= 6.0 V, Ta = 25°C, Figure 3 0.2 1.0 µA
Supply leakage current I

LEK

(2) VDD= 6.0 V, Ta = 50°C, Figure 3 1.0 5.0 µA

V

DD

= 6.0 V µA

Input leakage current I

OFF

VIN= V

DD

1.0 µA

VIN= V

SS

–1.0 µA

Output voltage 2 VDD1-(2)

V

DD

= 5.0 V, C1 = C2 = 0.1 µF, Figure 4,

V

DD

1 = V

O

2.4 2.5 2.6 V

1/2 bias, fopg = 32.768 kHz

Output voltage 3 V

DD

1-(3)

V

DD

= 5.0 V, C1 = C2 = 0.1 µF, Figure 4,

V

DD

1 = VO, 1.4 1.67 1.8 V

V

DD

2-(3)

1/3 bias, fopg = 32.768 kHz

VDD2 = V

O

3.1 3.33 3.5 V

 I

DD

 1-1

V

DD

= 5.0 V,

15 30 µA

Supply current 1

Ta = 25°C

 I

DD

 1-2

V

DD

= 5.0 V,

50 µA

Ta = 50°C

 I

DD

 2-1

V

DD

= 5.0 V,

15 30 µA

Supply current 2

Ta = 25°C

 I

DD

 2-2

V

DD

= 5.0 V,

50 µA

Ta = 50°C

 I

DD

 3-1

V

DD

= 5.0 V,

400 600 µA

Supply current 3

Ta = 25°C

 I

DD

 3-2

V

DD

= 5.0 V,

600 µA

Ta = 50°C

 I

DD

 4-1

V

DD

= 5.0 V,

450 650 µA

Supply current 4

Ta = 25°C

 I

DD

 4-2

V

DD

= 5.0 V,

700 µA

Ta = 50°C

 I

DD

 5-1

V

DD

= 5.0 V,

500 700 µA

Supply current 5

Ta = 25°C

 I

DD

 5-2

V

DD

= 5.0 V,

750 µA

Ta = 50°C

 I

DD

 6-1

V

DD

= 5.0 V,

700 900 µA

Supply current 6

Ta = 25°C

 I

DD

 6-2

V

DD

= 5.0 V,

1000 µA

Ta = 50°C

Oscillator correction capacitance Cd V

DD

= 5.0 V, XTOUT pin (built-in) 16 20 24 pF

CF oscillator specifications,
CF: 4000 kHz, Ccg = Ccd = 33 pF,
HALT mode, Figure 8

CF oscillator specifications,
CF: 2000 kHz, Ccg = Ccd = 33 pF,
HALT mode, Figure 8

CF oscillator specifications,
CF: 1000 kHz, Ccg = Ccd = 100 pF,
HALT mode, Figure 8 or 220 pF

CF oscillator specifications,
CF: 400 kHz, Ccg = Ccd = 330 pF,
HALT mode, Figure 7

Crystal oscillator specifications,
crystal: 38 or 65 kHz, Cg = 10 pF,
C1 = 25 kΩ, HALT mode, Figure 6,
LCD = 1/3 bias

Crystal oscillator specifications,
crystal: 32 kHz
Cg = 20 pF, C1 = 25 kΩ, HALT mode,
Figure 6, LCD = 1/3 bias

S1 to S4, K1 to K4, M1 to M4, SO1 to
SO4, A1 to A4, INT, RES (with the K, P,
M, SO and A ports in input mode and
with open specifications for the INT and
RES pins)

Figure 1-1 Oscillator Circuit (XT pins) Figure 1-2 Oscillator Circuit (CF pins)

Figure 2 S, K, P, M, SO and A Port Input Circuit Configuration

Recommended Ceramic Filters

No. 4435-26/29

LC587008, 587006, 587004

Manufacturer Murata Mfg. Co., Ltd. Kyocera Corporation

Item

Catalog No. Ccg (pF) Ccd (pF) Catalog No. Ccg (pF) Ccd (pF)

Frequency
400 kHz CSB400P 330 330 KBR-400B 330 330
800 kHz CSB800J 220 220 KBR-800H 100 100
1 MHz CSB1000J 220 220 KBR-1000H/Y 100 100
2 MHz CSA2.00MG, CST2.00MG 33 (built-in) 33 (built-in) KBR-2.0MS 33 33

4 MHz CSA4.00MG, CSA4.00MGW 33 (built-in) 33 (built-in)

KBR-4.0MSA/MCA,

33 (built-in) 33 (built-in)

KBR-4.0MKS/MWS

Figure 3 Supply Leakage Test Circuit

Figure 4 Output Voltage Test Circuit

• Stopped state

• S-port input resistors: on state

• I/O ports: output mode, all data values high

• RES and INT pins: built-in resistor specifications, open
state

• Currents due to external components connected to the
LCD ports are not included.

• Crystal frequency: between 32 and 65 kHz

• CF frequency: 200 kHz to 4 MHz

• Crystal frequency: 32 kHz

• C1, C2 and C3: 0.1 µF

Figures 4 and 5

• LCD ports: open

• CF frequency: 200 kHz to 4 MHz

Figure 5 Output Voltage Test Circuit

Figure 7 Supply Current Test Circuit

Figure 9 Supply Current Test Circuit

Figure 6 Supply Current Test Circuit

Figure 8 Supply Current Test Circuit

Figure 10 Supply Current Test Circuit

No. 4435-27/29

LC587008, 587006, 587004

Figure 11 Segment Pin Open Drain Circuit Configurations

Figure 13 Serial I/O Timing

(in external clock mode)

Figure Initial Reset Timing

Figure 14 Timer 1 and Timer 2

External Clock Input Timing

(external clock mode, pins M3 and M4)

No. 4435-28/29

LC587008, 587006, 587004

Figure 12 Sample RC Oscillator Frequency Characteristics

PS No. 4435-29/29

LC587008, 587006, 587004

This catalog provides information as of June, 1995. Specifications and information herein are subject to change
without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.