Sanyo LC587008 Specifications

Ordering number : EN*4435A

63095HA (OT)/N1194JN/D1192JN No. 4435-1/29

Overview

The LC587004, LC587006 and LC587008 are 80-pin lowvoltage CMOS 4-bit microprocessors that include LCD drivers, 2 Kb RAM and 8, 12, or 16 KB ROM on chip. These microprocessors correspond to the earlier LC5870 series with the 256 by 4-bit on-chip RAM expanded to a 512 by 4-bit capacity.

Applications

• System control and LCD display in CD players, cameras and radio tuners

• System control and LCD display in miniature test equipment and consumer health care products

• These microprocessors are optimal for products that include LCD displays and, in particular, battery operated products.

• Remote controllers for VCRs and audio equipment

Functions

• Program ROM: 8064 × 16 bits (LC587008), 6144 × 16 bits (LC587006) and 4096 × 16 bits (LC587004)

• RAM: 512 × 4 bits on chip

• All instructions execute in a single cycle

• Cycle time and operating voltage ranges — 2 µs cycle time: VDD= 2.8 to 6.0 V

10 µs cycle time: VDD= 2.2 to 6.0 V 122 µs cycle time: VDD= 2.0 to 6.0 V

• Rich set of HALT/HOLD mode clearing and interrupt functions — Eight HALT mode clearing functions — Seven HOLD mode clearing functions — Seven interrupt functions (all of which can be used

as external interrupts)

— Subroutines can be nested up to eight levels

(including interrupt handling)

— Built-in watchdog timer function

• Powerful hardware for improved processing capacity — Built-in segment PLA and segment decoder: LCD

panel segments can be handled with no software processing of the LCD driver outputs. Also, the LCD drive pins can be switched to function as output

ports. — Built-in 8-bit synchronous serial I/O circuit — One 8-bit programmable timer (that can be used as

an event counter) — One 8-bit programmable reload timer (that can be

used to generate a remote control carrier signal) — The whole RAM area can be used as working area

(by using the RAM bank register) — Built-in RAM data pointer — Built-in clock oscillator and 15-bit divider (also used

to generate the LCD alternating frequency)

• Highly flexible LCD panel drive output pins (35 pins)

LCD panel ................Number of ...........Required

drive type...................segments ..............common pins

1/3 bias 1/4 duty........140 segments.......Four pins

1/3 bias 1/3 duty........105 segments.......Three pins

1/2 bias 1/4 duty........140 segments.......Four pins

1/2 bias 1/3 duty........105 segments.......Three pins

1/2 bias 1/2 duty........70 segments.........Two pins

Static..........................35 segments .........One pin

The LCD output pins can be switched to function as general-purpose outputs. — C-MOS type: Up to 35 pins — P-channel type: Up to 35 pins — N-channel type: Up to 35 pins

• These microprocessors allow the use of an oscillator appropriate to the application system specifications. — Crystal oscillator: 32 kHz, 65 kHz or 38 kHz (for the

time base, system clock or LCD alternating frequency)

— Ceramic oscillator: 400 kHz to 4 Mhz (for the

system clock and the timers and serial counter)

— RC oscillator: 200 kHz to 1 MHz (for the system

clock and the timers and serial counter)

— External clock (for the system clock and the timers

and serial counter)

Preliminary

LC587008, 587006, 587004

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Single-Chip 4-Bit Microprocessors with LCD Driver,

2 Kb RAM, and 8, 12, or 16 KB ROM on chip

CMOS LSI

Features

• These microprocessors are the top end of the LC5870 series and have the following features. Faster cycle times — Cycle time: 2 µs for VDDbetween 4.5 and 6.0 V — Cycle time: 10 µs for VDDbetween 2.2 and 6.0 V Low power dissipation HALT mode (typical) Continuous operation (typical) — Ceramic filter (CF) 4 MHz (5.0 V) 600 µA 1.7 mA

(cycle time = 2 µs)

— Crystal oscillator 32 kHz (3.0 V, CF stopped) 4.0

µA 20 µA (cycle time = 122 µs) Improved timer functions — One 8-bit programmable timer (that can be used as

an event counter) — One 8-bit programmable reload timer (that can be

used to generate a remote control carrier signal) — Time base timer (for use as a clock) — Watchdog timer Improved standby functions — Clock standby function (HALT mode), software

switching between low speed mode (low current)

and high speed mode — Full standby mode (HOLD mode) — HALT and HOLD modes can be cleared by external

interrupt pins, input ports (up to nine pins) and serial

I/O interrupts Improved I/O functions — External interrupt pins — Up to 9 input and I/O pins that can clear HALT and

HOLD modes — Up to 24 input ports with built-in software

controllable input resistors (either pull-up or pull-

down specified as mask options) — Up to 25 input port pins with a built-in floating

prevention circuit — LCD driver: four common pins and 35 segment pins — General-purpose I/O ports: 20 pins (of which 12 are

p-channel open drain and 4 are n-channel open

drain) — General-purpose inputs: five pins — General-purpose outputs (type 1): four pins (LED

direct drive pins, one internal alarm signal output

pin and one carrier output pin) — General-purpose outputs (type 2): 35 pins (when all

35 LCD segment port pins are switched over to

function as general-purpose outputs) — Eight-bit serial I/O port: one set (three pins: input,

output and clock)

• Delivery formats: QFP80 (QIP80) and chip

Package Dimensions

unit: mm

3044B-QFP80A

No. 4435-2/29

LC587008, 587006, 587004

SANYO: QIP80A

[LC587008, 587006, 587004]

Pad Layout

Chip size: 5.12 mm × 5.29 mm Pad size: 120 µm × 120 µm Chip thickness: 480 µm (chip products)

Pin Assignments/Pad Names and Coordinates

Note: 1. Pin numbers are for QIP80 package products.

2. Connect the test pins (TST) to V

3. Pad numbers 40 and 41 must be left open in the chip specification product.

4. Do not use dip-soldering techniques to mount the QIP80 package versions.

5. For chip products either connect the substrate to V

or leave it open.

No. 4435-3/29

LC587008, 587006, 587004

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

24 1 V

2234 –2319 25 2 CFIN 2234 –1883 26 3 CFOUT 2234 –1701 27 4 S1 2234 –1458 28 5 S2 Input 2234 –1212 29 6 S3 port 2234 –915 30 7 S4 2234 –669 31 8 K1 2234 –284 32 9 K2

I/O port

2234 –101 33 10 K3 2234 81 34 11 K4 2234 264 35 12 M1 2234 448 36 13 M2

I/O port

2234 631 37 14 M3 2234 814 38 15 M4 2234 997 39 16 N1 2234 1352 40 17 N2 Output 2234 1624 41 18 N3 port 2234 1895 42 19 N4 2234 2173 43 20 TST 1958 2449 44 21 Seg 1 1732 2449 45 22 Seg 2 1506 2449 46 23 Seg 3 1280 2449 47 24 Seg 4 1054 2449 48 25 Seg 5 874 2449 49 26 Seg 6 694 2449 50 27 Seg 7 514 2449 51 28 Seg 8 335 2449

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

52 29 Seg 9 155 2449 53 30 Seg 10 –24 2449 54 31 Seg 11 –204 2449 55 32 Seg 12 –384 2449 56 33 Seg 13 –564 2449 57 34 Seg 14 –744 2449 58 35 Seg 15 –923 2449 59 36 Seg 16 –1103 2449 60 37 Seg 17 –1283 2449 61 38 Seg 18 –1463 2449 62 39 Seg 19 –1643 2449 — 40 Test –1821 2449 — 41 Test –2001 2449 63 42 Seg 20 –2362 2449 64 43 Seg 21 –2362 2248 65 44 Seg 22 –2362 1649 66 45 Seg 23 –2362 1468 67 46 Seg 24 –2362 1288 68 47 Seg 25 –2362 1107 69 48 Seg 26 –2362 799 70 49 Seg 27 –2362 618 71 50 Seg 28 –2362 438 72 51 Seg 29 –2362 257 73 52 Seg 30 –2362 77 74 53 Seg 31 –2362 –103 75 54 Seg 32 –2362 –283 76 55 Seg 33 –2362 –464 77 56 Seg 34 –2362 –664

Pin Pad

Symbol

Coordinates

No. No.

Xµm Yµm

78 57 Seg 35 –2362 –824 79 58 COM4 –2362 –1139 80 59 COM3 –2362 –1564

1 60 COM2 –2362 –2319 2 61 COM1 –1912 –2319 3 62 CUP1 –1730 –2319 4 63 CUP2 –1549 –2319 5 64 RES –1327 –2319 6 65 INT –1145 –2319 7 66 SO1 –963 –2319 8 67 SO2 I/O port, –780 –2319

9 68 SO3 SIO port –597 –2319 10 69 SO4 –414 –2319 11 70 A1 –231 –2319 12 71 A2

I/O port

–48 –2319 13 72 A3 134 –2319 14 73 A4 317 –2319 15 74 P1 504 –2319 16 75 P2

I/O port

687 –2319 17 76 P3 870 –2319 18 77 P4 1053 –2319 19 78 XTOUT 1279 –2319 20 79 XTIN 1462 –2319 21 80 V

2 1685 –2319

22 81 V

1 1868 –2319

23 82 V

2050 –2319

System Block Diagram

System Block Diagram for the LC587008, LC587006 and LC587004

RAM: Data memory ROM: Program memory DP: Data pointer register BNK: Bank register APG: RAM page flags AC: Accumulator ALU: Arithmetic and logic unit B: B register OPG: ROM page flag PC: Program counter

IR: Instruction register STS1: Status register 1 STS2: Status register 2 STS3: Status register 3 STS4: Status register 4 STS5: Status register 5 PLA: Segment data and strobe programmable logic

array

WAIT.C: Waiting time counter

No. 4435-4/29

LC587008, 587006, 587004

Pin Functions

No. 4435-5/29

LC587008, 587006, 587004

Pin I/O

QIP-80

Function Option At reset

Pin No.

— 24

— 23

VDD1 — 22 V

2 — 21

CUP1 — 3 CUP2 — 4

CFIN Input 25

CFOUT Output 26

XTIN Input 20

XTOUT Output 19

S1 27 S2 28 S3

Input

S4 30

K1 31 K2 32 K3

I/O

K4 34

M1 35 M2

I/O

36 M3 37 M4 38

A1 11 A2

I/O

12 A3 13 A4 14

P1 15 P2

I/O

16 P3 17 P4 18

Power supply LCD drive power supply

Switching pin used to supply the LCD drive voltage to the V

1 and

2 pins

• Connect a nonpolarized capacitor between CUP1 and CUP2 when 1/2 or 1/3 bias is used.

• Leave open when a bias other than 1/2 or 1/3 is used.

• CF specifications

• RC specifications

• External specifications

• Not used

• The pull-up or pulldown resistors are on.

Note: These pins go

to the floating state when reset is cleared.

• The pull-up or pulldown resistors are on.

Note: These pins go

to the floating state when reset is cleared.

• Input mode

• Output latch data is set high.

• 32k specifications

• 65k specifications

• 38k specifications

• Not used

• Transistors to hold a low or high level

• Selection of either pull-up or pulldown resistors

• Transistors to hold a low or high level

• Selection of either pull-up or pulldown resistors

The same as K1 toK4The same as K1 to

The same as K1 to K4

System clock oscillator connections

• Ceramic resonator connection (CF specifications)

• RC component connection (RC specifications)

• External signal input pin (CFOUT is left open) This oscillator is stopped by the execution of a STOP or SLOW instruction.

Reference calculation (clock specifications, LCD alternating frequency), system clock oscillator

• 32 kHz crystal resonator connection

• 65 kHz crystal resonator connection This oscillator is stopped by the execution of a STOP instruction.

Input-only ports

• Input pins used to read data into RAM

• Built-in 7.8 ms and 1.95 ms chatter rejection circuits

• Built-in pull-up/pull-down resistors Note: The 7.8 ms and 1.95 ms times are the times when ø0 is

32.768 kHz.

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits. The selection of 7.8 or 1.95 ms is linked to that for the S ports. Note: The 7.8 ms and 1.95 ms times are the times when ø0 is

32.768 kHz.

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• M4 is used as the external clock input pin in TM2 mode 3. * The minimum period for the external clock is twice the cycle time.

• Built-in pull-up/pull-down resistors

I/O ports

• Input pins used to read data into RAM

• Output pins used to output data from RAM

• Built-in pull-up/pull-down resistors

I/O ports Function: The same as pins A1 to A4

Continued on next page.

Continued from preceding page.

No. 4435-6/29

LC587008, 587006, 587004

Continued on next page.

Pin I/O

QIP-80

Function Option At reset

Pin No.

SO1 7 SO2

I/O

8 SO3 9 SO4 10

N1 39 N2

Output

40 N3 41 N4 42

INT Input 6

RES Input 5

TST Input 43

I/O ports Function: The same as for pins A1 to A4 Pins SO1 to SO3 area also used for the serial interface.

• Use of these pins in serial mode can be selected under program control.

• Pin functions: SO1: Serial input pin

SO2: Serial output pin

SO3: Serial clock pin The serial clock pin can be switched between internal and external, and between rising edge output and falling edge output.

• Transistors to hold a low or high level

• Selection of either pull-up or pulldown resistors

• Internal serial clock divisor selection

I 1/1 II 1/2 III 1/4

The same as for K1 to K4

The output levels on pins N1 to N4 can be specified as an option.

• Pins N1 to N4 output circuit type:

I CMOS II N-channel

open drain

• Pins N1 to N4 output level

I High level II Low level

• Transistors to hold a low or high level

• Selection of either pull-up or pulldown resistors

• Signal conversion (rising/falling) selection

* Only when the

input resistor open specification is selected

• LCD driver/ general-purpose output switching

• LCD drive type switching — STATIC — 1/2 bias – 1/2

duty

— 1/2 bias – 1/3

duty

— 1/2 bias – 1/4

duty

— 1/3 bias – 1/3

duty

— 1/3 bias – 1/4

duty

• General-purpose output circuit switching — CMOS — P-channel

open drain

— N-channel

open drain

• Output latch control in standby modes

• LCD drive — All segments on — All segments off *: Determined by

mask options

• General purpose outputs — High level — Low level *: Determined by

mask options

Note: When a

combination of LCD drive and generalpurpose outputs, the output state is

either: — All lit/high level — All off/low level.

• These pins go to the static drive mode during the reset period.

Output-only ports

• Output pins used to output data from RAM

• An alarm signal can be output from pin N4. (Note that this is only when the N4 output latch is low.)

• An alarm signal modulated at 1, 2 or 4 kHz can be output. (These frequencies are output when ø0 is 32.768 kHz.)

• A carrier signal can be output from N3. (Note that this is only when the N3 output latch is low.)

Input ports

• External interrupt request inputs

• Input pins used to read data into RAM

• Input detection can be performed on either rising or falling edges.

• Built-in pull-up/pull-down resistors

LSI internal reset input

• The reset input level can be selected to be either high or low.

• Built-in pull-up/pull-down resistors

• Note: The reset pulse must be at least 500 µs.

Test input

• QIP80 products: Connect to V

• Chip products: Leave open or connect to V

• LCD panel drive/general-purpose output

— LCD panel drive

I STATIC II 1/2 bias – 1/2 duty III 1/2 bias – 1/3 duty IV 1/2 bias – 1/4 duty V 1/3 bias – 1/3 duty VI 1/3 bias – 1/4 duty

Types I to V can be specified as mask options.

— General-purpose output mode

I CMOS II P-channel open drain III N-channel open drain

Types I to III can be specified as mask options.

• LCD/general-purpose output control is handled by the segment PLA,

and thus program control is not required.

• These pins support output latch control on reset and in standby

states when the oscillators are stopped.

• Arbitrary combinations of LCD drive and general-purpose outputs can

be used.

Seg1, Seg2 to Seg35

Output

44,

45 to

Continued from preceding page.

Sample Application Circuit

LCD: 1/2 bias – 1/4 duty

No. 4435-7/29

LC587008, 587006, 587004

Pin I/O

QIP-80

Function Option At reset

Pin No.

COM1 2 COM2 1 COM3

Output

COM4 79

The static drive waveform is output during the reset period. * There are cases

where the alternating frequency stops for the CF, RC and external clock specifications. (These cases differ depending on option specifications.)

LCD panel drive common polarity outputs The table below shows how these pins are used depending on the duty used. (Values for alternating frequency reflect a typical specification of

32.768 MHz for ø0.)

Note: A cross (

✕ ) indicates that the pin is not used with that duty type.

Static duty 1/2 duty 1/3 duty 1/4 duty

COM1

o o o o

COM2 ✕ o o o COM3 ✕ ✕ o o COM4 ✕ ✕ ✕ o

Alternation

32 Hz 32 Hz 42.7 Hz 32 Hz

frequency

Oscillator Circuit Options

No. 4435-8/29

LC587008, 587006, 587004

Option Circuit configuration Note

RC and Xtal

CF and Xtal

• 400 kHz (CF)

• 4 MHz (CF)

• The cycle time is four times the f1 period.

• The divider outputs (ø1 to ø15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

• OSC1 is stopped when a SLOW instruction is executed.

• The cycle time is four times n times the f1 period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

• OSC1 is stopped when a SLOW instruction is executed.

• The cycle time is four times the f1 period.

• The divider outputs (ø1 to ø15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

Continued on next page.

Continued from preceding page.

No. 4435-9/29

LC587008, 587006, 587004

Option Circuit configuration Note

• 400 kHz

• 4 MHz

Xtal

External input

• The cycle time is four times n times the f1 period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

• The cycle time is four times the f2 period.

• The divider outputs (ø1 to ø15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

• The cycle time is four times n times the f1 period. (Note: n is 2.)

• The divider outputs (ø1 to ø15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.

+ 20 hidden pages