Sanyo LC4132C Specifications

Ordering number : ENN*6477

CMOS IC

LC4132C

Dot Matrix STN LCD Segment Driver

Overview

The LC4132C is a segment driver for large-scale dot matrix LCDs. The LC4132C latches 240 bits of display data sent from the controller (in 4- or 8-bit parallel units) and generates the LCD drive signals. The LC4132C and the LC4102C common driver form a chip set that can drive a large-screen LCD panel.

Features

•CMOS (p-substrate) high voltage process

•LCD drive voltage: 36 V

•Logic system supply voltage: 2.7 to 5.5 V

•fcp max: 12 MHz (VDD = 5 V ±10%), 10 MHz (V DD = 2.7 to 4.5 V)

•Slim chip

•Can be switched between 4-bit an 8-bit parallel input.

•Output direction switching

•Display off function that holds the LCD drive voltages at fixed levels.

•Display duty: 1/160 to 1/480

•Supports COG (chip on glass) mounting. (Gold bump pads are used.)

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

51200RM (OT) No. 6477-1/12

LC4132C

Block Diagram

O1

O2

O3

O4

O238

O239

O240

V0

V2

4 Level LCD Drive Circuit (240 bits)

V3

V5

Output Control

VDDH

Level Shifter

DISP

M

2nd Latch (240 bits)

LOAD

	BS	1st Latch (8 bits × 30)
	D0	Address Decoder
	to
		Bits Control
	D7
	CP	Address Counter
	R/L
	EIO1	Chip Disable & Latch Control

V0

V2

V3

V5

VDDH

VDD VSS

EIO2

No. 6477-2/12

LC4132C

The electrical characteristics listed below apply when packaged in the Sanyo PGA-208 package.

Absolute Maximum Ratings at VSS = 0 V

Parameter	Symbol		Conditions		Ratings		Unit
				min	typ	max
	VDD max	VDD		–0.3		7.0	V
Maximum supply voltage	VDDH max	VDDH		–0.3		40.0	V
	VSS max	VSS		–0.3		0.3	V
	VIN	*1		–0.3		VDD + 0.3	V
Input voltage	V0, V2	V0, V2 *2		VDDH – 7.0		VDDH + 0.3	V
	V3	V3 *2		–0.3		VSS + 7.0	V
	V5	V5 *2		–0.3		0.3	V
Operating temperature	Topr			–20		+75	°C
Storage temperature	Tstg			–55		+125	°C

Notes: 1. D0 to D7, LOAD, CP, R/L, DISP, M, EIO1, EIO2, BS

2. The following relationships must hold for V0, V2, V3, and V5: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.

Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V

Parameter	Symbol		Conditions		Ratings		Unit
				min	typ	max
	VDD	VDD		2.7		5.5	V
Supply voltage	VDDH	VDDH		20		36	V
	VSS	VSS			0		V
Input high-level voltage	VIH	*3		0.8 VDD		VDD	V
Input low-level voltage	VIL	*3		0		0.2 VDD	V
	V0, V2	V0, V2 *4		VDDH – 7.0		VDDH	V
Input voltage	V3	V3 *4		0		VSSH + 7.0	V
	V5	V5 *1			0		V

Notes: 3. D0 to D7, LOAD, CP, R/L, M, DISP, BS, EIO1, EIO2

4. The following relationships must hold for V0, V2, V3, and V5: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.

At power on: The logic system power supply must be applied before the high-voltage system power supply. (Or they must both be applied at the same time.)

At power off: The high-voltage system power supply must be turned off before the logic system power supply. (Or they must both be turned off at the same time.)

VDD = 5 V ± 10%, Ta = –20 to +75°C, VSS = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	CP clock frequency	fcp	CP			12	MHz
	High-level load pulse width	tw (ldH)	LOAD	50			ns
	High-level clock pulse width	tw (cpH)	CP	20			ns
	Low-level clock pulse width	tw (cpL)	CP	20			ns
	LOAD/CP setup time	tsu (ld)	LOAD, CP	100			ns
	LOAD/CP hold time	tho (ld)	LOAD, CP	200			ns
	DATA/CP setup time	tsu (cp)	CP, D0 to D7	10			ns
	DATA/CP hold time	tho (cp)	CP, D0 to D7	10			ns
	EIO input setup time	tsu (ei)	CP, EIO1, EIO2	24			ns
	Clock rise time	tr	LOAD, CP *5			50	ns
	Clock fall time	tf	LOAD, CP *5			50	ns
	Note: 5. The clock rise time (tr) and the clock fall time (tf) must meet the conditions (1) and (2) shown below.
	1
	—— – tw (cph) – tw (cpl)
	fcp	(2) tr, tf ≤ 50 ns
	(1) tr, tf < ————————————
	2

No. 6477-3/12

LC4132C

VDD = 2.7 to 4.5 V, Ta = –20 to +75°C, VSS = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	CP clock frequency	fcp	CP			10	MHz
	High-level load pulse width	tw (ldH)	LOAD	50			ns
	High-level clock pulse width	tw (cpH)	CP	37			ns
	Low-level clock pulse width	tw (cpL)	CP	37			ns
	LOAD/CP setup time	tsu (ld)	LOAD, CP	100			ns
	LOAD/CP hold time	tho (ld)	LOAD, CP	350			ns
	DATA/CP setup time	tsu (cp)	CP, D0 to D7	35			ns
	DATA/CP hold time	tho (cp)	CP, D0 to D7	35			ns
	EIO input setup time	tsu (ei)	CP, EIO1, EIO2	30			ns
	Clock rise time	tr	LOAD, CP *6			50	ns
	Clock fall time	tf	LOAD, CP *6			50	ns
	Note: 6. The clock rise time (tr) and the clock fall time (tf) must meet the conditions (1) and (2) shown below.
	1
	—— – tw (cph) – tw (cpl)
	fcp	(2) tr, tf ≤ 50 ns
	(1) tr, tf < ————————————
	2

Electrical Characteristics at Ta = –20 to +75°C, VDD = 2.7 to 5.5 V, VSS = 0 V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input high-level voltage

IIH

VIN = VDD *7

5

µA

Input low-level voltage

I 1

V

IN

= V

SS

*7

–5

µA

IL

Output high-level voltage

VOH

IO = –0.4 mA: EIO1, EIO2

VDD – 0.4

VDD

V

Output low-level voltage

VOL

IO = 0.4 mA: EIO1, EIO2

VSS

0.4

V

VDDH = 36 V *8

Output on resistance

ROUT

V0 – VO = 0.5 V, V2 – VO = 0.5 V

1

3

kΩ

VO – V3 = 0.5 V, VO – V5 = 0.5 V

: O1 to O240

IDD

VDD = 2.7 to 5.5 V

5.0

mA

Current drain

IDDH

V

DD

= 2.7 to 5.5 V, V

DDH

= 32 V *9

3.0

mA

VDD = 5 V ±10%, VDDH = 36 V

3.0

mA

IST

*10

500

µA

Notes: 7. D0 to D7, LOAD, CP, R/L, M, DISP, EIO1, 2, BS

8.VO is the voltage applied by an on-state output, V0 = VDDH, V2 = 18/20 (VDDH – VSS), V3 = 2/20 (VDDH – VSS), V5 = VSS.

9.Measured when either LOAD = 28 kHz, CP = 10 MHz, and M = 75 Hz, or with no load and input at VIH = VDD or VIL = VSS.

10.The current drain in standby mode. Or when EIOn (input) = VDD.

No. 6477-4/12