Sanyo LC4104C-T2A Specifications
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC4104C-T2A is a segment driver IC for large-scale
dot matrix LCD displays. The LC4104C-T2A latches 160bits of display data transferred from the controller over a
4- or 8-bit parallel interface and generates the LCD drive
signals. In conjunction with the LC4102C-T2A common
driver, the LC4104C-T2A forms a chip set that can drive
large-screen LCD panels.
Features
• High-voltage CMOS (P-sub) process
• LCD drive voltage: 36 V
• Logic system power-supply voltage: 2.7 to 5.5 V
• Maximum fcp: 12 MHz (VDD= 5 V ±10%),
10 MHz (VDD= 2.7 to 4.5 V)
• Parallel input circuit can be switched between 4 and
8 bits.
• Output directionality switching
• DISPOFF function (Holds the LCD drive voltage at a
fixed level.)
• Display duty ratios: 1/160 to 1/480
• Package: TCP (Tape Carrier Package)
CMOS IC
Ordering number : ENN*6790
20702TN (OT) No. 6790-1/8
Preliminary
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
LCD Dot Matrix Segment Driver for STN Displays
LC4104C-T2A
Block Diagram
Specifications
The following electrical characteristics apply when sealed in a SANYO standard PGA-208 package.
Absolute Maximum Ratings at VSS= 0 V
Note: V0, V2, V3, and V5 must obey the following relationships: V
DDH
≥ V0 ≥V2 ≥ V
DDH
– 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.
No. 6790-2/8
LC4104C-T2A
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max –0.3 to +7 V
Maximum supply voltage V
DDH
max –0.3 to +40 V
Maximum supply voltage V
SS
max –0.3 to +0.3 V
Input voltage V
IN
D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2, BS –0.3 to VDD+ 0.3 V
Input voltage V0, V2 V0, V2 V
DDH
– 7 to V
DDH
+ 0.3 V
Input voltage V3 V3 –0.3 to V
SS
+ 7 V
Input voltage V5 V5 –0.3 to +0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
V0
V2
V3
VDDH
LOAD
BS
DISP
M
V5
V0
V2
V3
VDDH
V
DD
V
SS
EIO2
V5
O1
TEST
D0
D7
EIO1
CP
R/L
O2O3O4
O158
O159
O160
Output Control
4 Level LCD Drive Circuit (160bits)
Level Shifter
2nd Latch (160bits)
1st Latch (8bits × 20)
Address Decoder
Address Counter
—
A1367
Bits
Control
Chip Disable &
Latch Control
Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V
Note: V0, V2, V3, and V5 must obey the following relationships: V
DDH
≥ V0 ≥ V2 ≥ V
DDH
– 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.
At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the
same time.
At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the
same time.
Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V, VDD= 5 V ± 10%
Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below.
➀: tr, tf <
②: tr, tf ≤ 50 ns
Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V, VDD= 2.7 to 4.5 V
Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below.
➀: tr, tf <
②: tr, tf ≤ 50 ns
1
– tw (cph) – tw (cpl)
fcp
2
1
– tw (cph) – tw (cpl)
fcp
2
No. 6790-3/8
LC4104C-T2A
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage V
DD
2.7 5.5 V
Supply voltage V
DDH
14 36 V
Supply voltage V
SS
0 V
Input high-level voltage V
IH
D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,
0.8 V
DD
V
DD
V
EIO1, EIO2
Input low-level voltage V
IL
D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,
0 0.2 V
DD
V
EIO1, EIO2
Input voltage V0, V2 V0, V2 V
DDH
– 7 V
DDH
V
Input voltage V3 V3 0 V
SSH
+ 7 V
Input voltage V5 V5 0 V
Parameter Symbol Conditions
Ratings
Unit
min typ max
CP clock frequency fcp CP 12 MHz
High-level load pulse width tw (ldH) LOAD 50 ns
High-level clock pulse width tw (cpH) CP 20 ns
Low-level clock pulse width tw (cpL) CP 20 ns
LOAD/CP setup time tsu (ld) LOAD, CP 100 ns
LOAD/CP hold time tho (ld) LOAD, CP 200 ns
DATA/CP setup time tsu (cp) CP, D0 to D7 10 ns
DATA/CP hold time tho (cp) CP, D0 to D7 10 ns
EIO input setup time tsu (ei) CP, EIO1, EIO2 24 ns
Clock rise time tr LOAD, CP* 50 ns
Clock fall time tf LOAD, CP* 50 ns
Parameter Symbol Conditions
Ratings
Unit
min typ max
CP clock frequency fcp CP 10 MHz
High-level load pulse width tw (ldH) LOAD 50 ns
High-level clock pulse width tw (cpH) CP 37 ns
Low-level clock pulse width tw (cpL) CP 37 ns
LOAD/CP setup time tsu (ld) LOAD, CP 100 ns
LOAD/CP hold time tho (ld) LOAD, CP 200 ns
DATA/CP setup time tsu (cp) CP, D0 to D7 35 ns
DATA/CP hold time tho (cp) CP, D0 to D7 35 ns
EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns
Clock rise time tr LOAD, CP* 50 ns
Clock fall time tf LOAD, CP* 50 ns
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