Sanyo LC4104C-T2A Specifications

Ordering number : ENN*6790

CMOS IC

LC4104C-T2A

LCD Dot Matrix Segment Driver for STN Displays

Preliminary

Overview

The LC4104C-T2A is a segment driver IC for large-scale dot matrix LCD displays. The LC4104C-T2A latches 160bits of display data transferred from the controller over a 4- or 8-bit parallel interface and generates the LCD drive signals. In conjunction with the LC4102C-T2A common driver, the LC4104C-T2A forms a chip set that can drive large-screen LCD panels.

Features

•High-voltage CMOS (P-sub) process

•LCD drive voltage: 36 V

•Logic system power-supply voltage: 2.7 to 5.5 V

•Maximum fcp: 12 MHz (VDD = 5 V ±10%),

10 MHz (VDD = 2.7 to 4.5 V)

•Parallel input circuit can be switched between 4 and 8 bits.

•Output directionality switching

•DISPOFF function (Holds the LCD drive voltage at a fixed level.)

•Display duty ratios: 1/160 to 1/480

•Package: TCP (Tape Carrier Package)

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

20702TN (OT) No. 6790-1/8

LC4104C-T2A

Block Diagram

O1

O2

O3

O4

O158

O159

O160

V0

V0

V2

4 Level LCD Drive Circuit (160bits)

V2

V3

V3

V5

V5

Output Control

VDDH			Level Shifter

	DISP
	M
	LOAD		2nd Latch (160bits)
	BS		1st Latch (8bits × 20)
	D0	Bits	Address Decoder
	—
		Control
	D7
	CP		Address Counter
	R/L
	TEST
	EIO1		Chip Disable &
			Latch Control

VDDH

VDD

VSS

EIO2

A1367

Specifications

The following electrical characteristics apply when sealed in a SANYO standard PGA-208 package.

Absolute Maximum Ratings at VSS = 0 V

Parameter	Symbol	Conditions	Ratings	Unit
Maximum supply voltage	VDD max		–0.3 to +7	V
Maximum supply voltage	VDDH max		–0.3 to +40	V
Maximum supply voltage	VSS max		–0.3 to +0.3	V
Input voltage	VIN	D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2, BS	–0.3 to VDD + 0.3	V
Input voltage	V0, V2	V0, V2	VDDH – 7 to VDDH + 0.3	V
Input voltage	V3	V3	–0.3 to VSS + 7	V
Input voltage	V5	V5	–0.3 to +0.3	V
Operating temperature	Topr		–20 to +75	°C
Storage temperature	Tstg		–55 to +125	°C

Note: V0, V2, V3, and V5 must obey the following relationships: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.

No. 6790-2/8

LC4104C-T2A

Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	Supply voltage	VDD		2.7		5.5	V
	Supply voltage	VDDH		14		36	V
	Supply voltage	VSS			0		V
	Input high-level voltage	VIH	D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,	0.8 VDD		VDD	V
			EIO1, EIO2
	Input low-level voltage	VIL	D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,	0		0.2 VDD	V
			EIO1, EIO2
	Input voltage	V0, V2	V0, V2	VDDH – 7		VDDH	V
	Input voltage	V3	V3	0		VSSH + 7	V
	Input voltage	V5	V5		0		V

Note: V0, V2, V3, and V5 must obey the following relationships: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.

At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time.

At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the same time.

Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10%

Parameter				Symbol		Conditions		Ratings		Unit
							min	typ	max
CP clock frequency				fcp		CP			12	MHz
High-level load pulse width				tw (ldH)		LOAD	50			ns
High-level clock pulse width				tw (cpH)		CP	20			ns
Low-level clock pulse width				tw (cpL)		CP	20			ns
LOAD/CP setup time				tsu (ld)		LOAD, CP	100			ns
LOAD/CP hold time				tho (ld)		LOAD, CP	200			ns
DATA/CP setup time				tsu (cp)		CP, D0 to D7	10			ns
DATA/CP hold time				tho (cp)		CP, D0 to D7	10			ns
EIO input setup time				tsu (ei)		CP, EIO1, EIO2	24			ns
Clock rise time				tr		LOAD, CP*			50	ns
Clock fall time				tf		LOAD, CP*			50	ns
Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and below.
1		– tw (cph) – tw (cpl)
: tr, tf <	fcp
			2
: tr, tf ≤ 50 ns
Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V
Parameter				Symbol		Conditions		Ratings		Unit
							min	typ	max
CP clock frequency				fcp		CP			10	MHz
High-level load pulse width				tw (ldH)		LOAD	50			ns
High-level clock pulse width				tw (cpH)		CP	37			ns
Low-level clock pulse width				tw (cpL)		CP	37			ns
LOAD/CP setup time				tsu (ld)		LOAD, CP	100			ns
LOAD/CP hold time				tho (ld)		LOAD, CP	200			ns
DATA/CP setup time				tsu (cp)		CP, D0 to D7	35			ns
DATA/CP hold time				tho (cp)		CP, D0 to D7	35			ns
EIO input setup time				tsu (ei)		CP, EIO1, EIO2	30			ns
Clock rise time				tr		LOAD, CP*			50	ns
Clock fall time				tf		LOAD, CP*			50	ns

Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and below.

1		– tw (cph) – tw (cpl)
: tr, tf <	fcp
		2
: tr, tf ≤ 50 ns

No. 6790-3/8