Sanyo LC4102-T2A Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Overview

The LC4102C-T2A is a common driver for large-scale dot
matrix LCD panels. It includes a 160-bit bidirectional shift
register and 4-level LCD driver circuits. The number of
bits can be further increased by using the provided input
and output pins to connect multiple LC4102C-T2A in
cascade. The LC4102C-T2A and the LC4104C-T2A LCD
dot matrix segment driver IC form a large-screen LCD
panel driver chip set.

Features

• Fabricated in a CMOS (P-sub) high-voltage process.

• LCD drive voltage: 36 V

• Logic system power-supply voltage: 2.7 to 5.5 V

• fcp max: 2.5 MHz

• Bidirectional shift register

• The shift register can be split into two 80-bit registers.
(Two screens drivable)

• DISPOFF function that locks the drive voltages output
to the LCD at fixed levels.

• Display duty: 1/160 to 1/480

• Package: TCP (Tape Carrier Package)

CMOS IC

Ordering number : ENN*6789

20702TN (OT) No. 6789-1/8

Preliminary

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

LCD Dot Matrix Common Driver for STN Displays

LC4102C-T2A

Specifications

The electrical characteristics values shown below are for devices packaged in the SANYO standard PGA-208 package.

Absolute Maximum Ratings at VSS= 0

Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE

2. The voltages V0, V1, V4, and V5 must obey the relationships V

EE

≥ V0 ≥ V1 ≥ VEE– 7 V, and 7 V ≥ V4 ≥ V5 ≥ V

SSH

.

Parameter Symbol Applicable pins Ratings Unit

V

DD

max V

DD

–0.3 to +7.0 V

Supply voltage V

EE

max V

EE

–0.3 to +40.0 V

V

SSH

max V

SSH

–0.3 to +0.3 V

V

IN

*

1

–0.3 to VDD+ 0.3 V

Input voltage

V0, V1 V0, V1 *

2

VEE– 7.0 to VEE+ 0.3 V

V4 V4 *

2

–0.3 to VSS+ 7.0 V

V5 V5 *

2

–0.3 to +0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C

No. 6789-2/8

LC4102C-T2A

Allowable Operating Ranges at VSS= 0, Ta = –20 to +75°C

Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE

2. The voltages V0, V1, V4, and V5 must obey the relationships V

EE

≥ V0 ≥ V1 ≥ VEE– 7 V, and 7 V ≥ V4 ≥ V5 ≥ V

SSH

.
When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively,
turn both on at the same time.
When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively,
turn both off at the same time.

Parameter Symbol Applicable pins

Ratings

Unit

min typ max

V

DD

V

DD

2.7 5.5 V

Supply voltage V

EE

V

EE

14 36 V

V

SSH

V

SSH

0 V

Input high-level voltage V

IH

*

1

0.8 × V

DD

V

DD

V

Input low-level voltage V

IL

*

1

0 0.2 × V

DD

V

V0, V1 V0, V1 *

2

VEE– 7.0 V

EE

V

Input voltage V4 V4 *

2

0

V

SSH

+ 7.0

V

V5 V5 *

2

0 V

Electrical Characteristics at Ta = –20 to +75°C, VDD= 2.7 to 5.5 V, VSS= 0 V

Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE

2. V

OUT

is the voltage applied by on-state outputs. V0 = VEE, V1 = 19/20 (VEE– V

SSH

), V4 = 1/20 (VEE– V

SSH

), V5 = V

SSH

, V

SSH

= V

SS

3. VDD= 2.7 to 5.5 V, fCP= 50 kHz

4. f

DF

= 100 Hz, with no output load, VEE= 36 V, for a single data shift

Parameter Symbol Applicable pins

Ratings

Unit

min typ max

Input high-level current I

IH

VIN= VDD*

1

1

µA

Input low-level current I

IL

VIN= VSS*

1

–1

Output high-level voltage V

OH

IOH= –0.4 mA, DIO1, DIO160

0.8 × V

DD

V

DD

V

Output low-level voltage V

OL

IOL= 0.4 mA, DIO1, DIO160 V

SS

0.2 × V

DD

RON0 V

OUT

= V0 – 0.5 V *2, OUT1 to 160 1000

Output on resistance

RON1 V

OUT

= V1 – 0.5 V *2, OUT1 to 160 1000

Ω

RON4 V

OUT

= V4 + 0.5 V *2, OUT1 to 160 1000

RON5 V

OUT

= V5 + 0.5 V *2, OUT1 to 160 1000

Current drain 1 I

DD

VDD*3 200

µA

Current drain 2 I

DDH

VDD*4 500

Block Diagram

No. 6789-3/8

LC4102C-T2A

V0
V1
V4
V5

V

EE

VSSH

DI01

DISP

DF

V0

OUT160

OUT159

OUT158

OUT3

OUT2

OUT1

V1
V4
V5

LOAD

RS/LS

V

EE

VSSH

DIO160

V

DD

V

SS

DMIN

MODE

4 Level LCD Driver Circuit (160 bits)

Output Control

Level Shifter

Bidirectional Shift

Register (80 bits)

Bidirectional Shift
Registe (80 bits)

Shift

Control

A13673

Switching Characteristics at Ta = –20 to +75°C, VDD= 2.7 to 5.5 V, VSS= 0 V

Switching Characteristics

No. 6789-4/8

LC4102C-T2A

Parameter Symbol Conditions

Ratings

Unit

min typ max
Clock frequency fload LOAD 2.5 MHz
High-level clock pulse width twl LOAD 100
Input setup time tsu LOAD, DIOn, DMIN 100
Input hold time th LOAD, DIOn, DMIN 30
LOAD rising time tr LOAD 30

ns

LOAD falling time tf LOAD 30
DIO output delay time tpld LOAD, DIOn: 30 pF capacitance load 200
LOAD-on delay time tplo LOAD, OUTn: 100 pF capacitance load 1.0

µs

DF-on delay time tpdfo DF, OUTn: 100 pF capacitance load 1.0

t

LOAD

DIOn
DMIN

t

r

W1

t

su

t

f

0.8V

t

h

DD

0.2V

DD

DIO output

OUTn

DF

t

pld

t

plo

t

pdfo

A13674

Pin Functions

No. 6789-5/8

LC4102C-T2A

Symbol I/O Function

OUT1 to
OUT160

V0

V

EE

V

SSH

DISP

DF

LOAD
MODE
RS/LS

DIO1

DMIN

DIO160

V

DD

V

SS

O

I
I
I
I

–
–

I
I
I
I
I

I/O

I

I/O

——Logic system power supply

Logic system ground

LCD drive outputs

V0 level drive voltage input
V1 level drive voltage input
V4 level drive voltage input
V5 level drive voltage input

High-voltage block power supply
High-voltage block ground
LCD off function. All outputs will be held at a fixed V5 level when this pin is low.
Alternation input
Data shift pulse input (falling edge)
Data shift direction specification input

*: don’t care

DF Data DISP OUTn

L H H V0
H L H V1
L L H V4
H H H V5
* * L V5

MODE RS/LS Shift direction DIO1 DIO160 DMIN

L L OUT160 → OUT1 OUT IN *
L H OUT1 → OUT160 IN OUT *

H L

OUT160 → OUT81

OUT IN IN

OUT80 → OUT1

H H

OUT1 → OUT80

IN OUT IN

OUT81 → OUT160

*: don’t care (Must be fixed at low or high.)

V1

V5

V4

Pin Assignment

No. 6789-6/8

LC4102C-T2A

DUMMY

LC4102C-T2A

(CHIP TOP VIEW)

V

SSH

V

SSH

A13675

V

SSH

V

SS

V

SS

V

DD
RSLS
MODE

LOAD

DF
DISP

V

EE

V

EE

V

SSH
DIO160

DMIN
DIO1

V5

V5

V4

V4

V1

V1

V0

V0

OUT160
OUT159
OUT158

DUMMY

OUT3
OUT2

OUT1

Note: This figure shows the chip pattern surface as seen from abobe.

This figure dose not stipulate the TCP package.

Package Dimensions

unit: mm

LC4102C-T2A

No. 6789-7/8

LC4102C-T2A

2.45

4.45 MAX(Sealing area)

1.95(LSI)

0.8(P)

×

(25--1)=19.2

±

0.055 (W=0.34)

A=0.3

±

0.05

A

VSSH
V5

V4
V1

V0
VEE
VSSH
MODE
RSLS
VDD
DISP
DF
VSS
LOAD
VSS
DIO1
DMIN
DIO160
VSSH
VEE
V0
V1

V4
V5

VSSH

18.25 MAX(Sealing area)

16.25

±

0.05(Device hole)

15.75(LSI)

(Cu)

ø2.0

±

0.1

0.6 MAX

0.3 MAX

0.75 MAX

1.35 MAX

0.4

±

0.05

ø1.0

±

0.05

0.4

±

0.02

0.6

±

0.02

1.981

±

0.03

4.75(P)

×

4=19.0

±

0.05

4.75

±

0.03

1.2

±

0.05(SL)

2.0

±

0.05(SL)

8.0

±

0.1(SL)

4.0

±

0.1(SL)

R0.8

±

0.3(SR)

R0.5

±

0.05

0.6 MAX

0.6 MAX

10.3

±

0.05

3.7(

Cut line

)

8.5

±

0.3(SR)

1.7

±

0.3(SR)

1.2

±

0.05(SL) 6.7

±

0.05(SL)

1.2

±

0.05(SL) 4.9

±

0.05(SL)

15.0

19.8

±

0.1

19.8

±

0.1

1.7

±

0.1(SL)

1.7

±

0.1(SL)

12.55

±

0.1(SL)

12.55

±

0.1(SL)

23.6

±

0.05(SL)

24.0

±

0.055

0.14(P)

×

(162--1)=22.54

±

0.055 (W=0.09)

25.5(Cut line)

24.3

±

0.3(SR)

23.0

±

0.05(SL)

22.0

±

0.05(SL)

32.0

±

0.1

48.175

±

0.2

42.177

±

0.07

LSI chip

Flex hole

Device hole

Sealing area

PS No. 6789-8/8

LC4102C-T2A

This catalog provides information as of February, 2002. Specifications and information herein are subject
to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.