Sanyo LC3101 Specifications

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

CMOS IC

128K-Bit CMOS Mask ROM

Ordering number:ENN1542

LC3101

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Overview

The LC 3101 is a 128k-bit CMOS mask ROM that con­tains an interface connectable direct to the speech synthe­sizer IC LC8100. With one piece of this mask ROM, ap­proximately 100 seconds of speech synthesis can be at­tained. Since it also contains an interface connectable di­rect to an EPROM, speech synthesis can be attained by
using this mask ROM and an EPROM jointly.
A selection of 8-bit, 4-bit, or single-bit output data is al­lowed by means of external control. This mask ROM is
also suited for use in applications other than speech syn-

thesis.

Features

• ROM capacity : 128K bits

• Access time : 25.6µs typ (for operation at 200kHz typ).

• Cycle time : 30.6µs typ (for operation at 200kHz typ).

• Funciton
(1) Contains an interface to an EPROM.
(2) Contains an interface to the LC8100 (sepeech

synthesizer IC).

(3) Possible to select the bit length of output data.

8-bit data
4-bit data
Single-bit data

• Low power dissipation : CMOS

• Current drain :
2mA max (at operating mode).
1µA max (at nonoperating mode).

• Single +5V power supply.
+2.7 to 6.0V (supply voltage range).

• Package : DIP24

Package Dimensions

unit:mm

3014A-DIP42

[LC3101]

42

1

1.2 2.54

unit:mm

3025B-DIP42S

42

1

0.95

53.2

0.5

[LC3101]

37.9

0.48

22

13.8

15.24

21

4.25

5.1max

4.1

1.2

22

21

1.78

0.51min

SANYO : DIP42

13.8

15.24

4.25

5.1max

3.8

0.51min

1.15

SANYO : DIP42S

0.25

0.25

73101TN (KT)/7024KI, TS No.1542–1/14

LC3101

Pin Assignment

Equivalent Circuit Block Diagram

A0 to A3 : 18-bit address setting pins
ASTRB : A0 to A3 strobe pin
DREQ : ROM data request pin
DOUT : ROM data serial output pin
CT : Basic operation clock input pin
D0 to D7 : 8-bit input/output pins
MODE : DREQ pin input pulse count control pin
DSEL : Output bit length select pin
CE : Power-down control pin
EA0 to EA17 : 18-bit address output pins

Description of Operation of Internal Block

• ASTRB COUNTER : Block which internally sets address information applied in 5 steps from A0 to A3
pins.

• 18bit ADDRESS COUNTER : Address counter organized with 18 bits.

• READ PULSE COUNTER : Block which generates signal to operate address decoder, data selector.

• CHIP SELECT DECODER : Makes chip select signal with 214 to 217 bits or 18-bit address.

• 128kbit ROM MATRIX : ROM matrix cell organized with 128K bits.

• PARALLEL TO SERIAL : Shift register which serially outputs 8-bit parallel data to DOUT pin.

• I/O PORT : Selects input/output at D0 to D7 pins.

No.1542–2/14

Pin Description

.oNniPemaNniPtuptuo/tupnInoitcnuF

43BRTSAtupnI sserddatadehctalebot3Aot0AatadsesuachcihwlangisebortsgnittupnirofniP

53QERDtupnI.niptupnilangistseuqeratadMOR
63TUODtuptuO nipsiht,0018CLehthtiwnoitcnujnocnidesunehW.yllairesatadMORgnittuptuorofniP

73TCtupnI ehthtiwnoitcnujnocnidesunehW.edisniMORfokcolcnoitarepocisabgnittupnirofniP

83ECtupnI dnarewopfonoitacilpparetfayletaidemmiedisniCIfonoitazilaitinignillortnocrofniP

6VSS–.ylppusrewopfoV0otdetcennoC

82VDD–.ylppusrewopfoedis+otdetcennoC
9210/00tupnIVottessyawlA

7EDOMtupnI situo-daeratadMORnehW.nipQERDtasesluptupniforebmungnillortnocrofniP

8LESDtupnI 2,'H'ottessiLESDnehW.stib4nidemrofrepsituo-daeratadMORnehwdesU

90D

011D
212D
313D
414D
515D
616D
717D
72AVE/PEMtupnIVotdetcennocronepO
033A
132A
231A

330A
10AE
21AE
32AE
43AE
54AE

815AE

916AE

027AE

128AE

229AE

3201AE

4211AE

5221AE

6231AE

9341AE

0451AE

1461AE

2471AE

tuptuo/tupnI .stib8niatadgnittupnidnastib8niatadMORgnittuptuorofsniP

tupnI dettupnisinoitamrofnisserdda,edomgnittessserddatA.sserddatib-81gnittesrofsniP

tuptuO.sniptuptuosserddatib-81

LC3101

.edomgnittes

.'L'otECtes,tuo

.

SS

.0018CLehtfonipNIDotdetcennocsi

.0018CLehtfonipTCotdetcennocsinipsiht,0018CL

-daeratadMORronoitazisehtnysgnimrofreproF.)nwod-rewop(potsnoitarepolanretni

.'H'otEDOMtes,stib4rostib8nidemrofrep

.snip3D0Dotdettuptuoerastib

.

DD

.spets5nidrawnwodtibredro-hgihmorfstib4yb

situo-daeratadMORnehW.'L'otEDOMtes,tibelgnisaniyllairesdemrofrep

4

7

2ot

No.1542–3/14

LC3101

How to use the mask ROM and an EPROM jointly

The mask ROM and an external EPROM can be used jointly. Two selections of operation mode shown below are
available by high-order 4 bits (EA14 to EA17) of 18-bit address.

sniPedoMnoitarepO7Dot0D
)1(tuptuO .TUODdna7Dot0DsniptaderevilederastnetnocMORksamehT
)2(tupnI .TUODniptaderevilederadna7Dot0DsnipmorfnidaererastnetnoctuptuoMORPEehT

How to select the operation mode

The LC3101 contains a 4-bit chip select decoder (user option : Refer to “User mask”). Coincidence or uncoincidence
with high-order 4 bits (EA14 to EA17) of 18-bit address is detected to select the operation mode.

edoMnoitarepOredoceDtceleSpihCfostib41013CLfonoitarepO

)1(71AEot41AEhtiwecnedicnioCedomtuptuO:7Dot0DsniP

)2(71AEot41AEhtiwecnedicniocnUedomtupnI:7Dot0DsniP

Fig.1 shows the schematic diagram of the control section related to these operation modes. Fig. 2 shows the assign­ment of 256K-byte (128k bits × 16) that can be specified by 18-bit address.

Fig. 1 Schematic Diagram of Control Section

edomelbanedaerMORksaM

edomtibihnidaerMORksaM

Fig. 2 Address Space Assignement

No.1542–4/14

LC3101

ROM Data Readout Procedure

The following flowchart shows the outline of readout procedure. (1) to (7) give a more detailed description.

(1) Initialization of internal mode

There are 4 counter blocks (ASTRB counter, 18-bit ADDRESS counter, READ PULSE counter, DREQ counter)

inside the LC3101. Since initialization is required immediately after application of power, apply one ‘H’ level
pulse to CE pin. When CE is set to ‘L’ level, the power-down mode is released (refer to (7) ) and it is possible to
start readout any time.

(2) Setting of bit length of readout data

For the bit length of ROM data output, a selection of 3 lengths is allowed : 8 bits, 4 bits, and a single bit. For

controlling this selection, MODE, DSEL pins are used. The following Table shows 3 types of pin setting.

EDOM

LESD

'L'
'H'– )etoN(htgneltib-4

'L''H'

htgneltib-elgniS

)sisehtnyshceeps(

rohtgneltib-4rotib-8

)etoN(htgneltib-4

(Note) When DSEL is set to ‘L’, 20 to 23 bits are outputted at D0 to D3 pins.

When DSEL is set to ‘H’, 24 to 27 bits are outputted at D0 to D3 pins.

No.1542–5/14

LC3101

(3) Address setting

Apply 5 successive pulses to ASTRB pin. Synchronously with these pulses apply 18-bit address information to A0

to A3 pins from high-order bit downward by 4 bits in 5 steps. At this address setting mode DREQ pin must be set
to ‘L’ level. Shown below is the timing.

(Note) • “*”=don’t care.

• “2n”=Binary number at the nth bit to be set in address counter.

• For the numeric values of T

STRH

, T

STRL

, T

ADST

, T

, refer to Electrical Characteristics.

ADHS

Start of readout of set address data

Readout of ROM data starts at the falling of the 5th ASTRB pulse or the first (MODE=’H’) or the 8th (MODE=’L’)
DREQ pulse, and when access time T

has elapsed 20 bit is outputted at DOUT pin and 20 to 27 data are outputted

AC1

at D0 to D7 pins. (Refer to the following Timing Chart.)
Note) For the numeric value of T

, refer to Electrical Characteristics.

AC1

(4) Fetching of output data

As shown above, whenever access time T

has elapsed, data can be fetched from output ports DOUT or D0 to

AC1

D7 pins (Pin setting as shown in Table in (2) is required).

Counting one byte in a single bit from DOUT pin

Count a single bit (2n bit) from DOUT pin. To count the following single bit (2

n+1

bit), apply a shift clock to
DREQ pin. Shown below is Timing Chart.
For the numeric values of T

AC1

, T

DRQH

, T

, refer to Electical Characteristics.

SHFT

No.1542–6/14

LC3101

Counting one byte in 4-bits from D0 to D3 pins

In accordance with Table and (Note) in (2), fetch one byte from D0 to D3 pins by 4 bits in 2 steps. Shown below is
Timing Chart.

Counting one byte in 8 bits from D0 to D7 pins

Fetch 8 bits from D0 to D7 pins. Shown below is Timing Chart.

(5) Setting address again and counting data

(1) Timing for application of ASTRB pulse when address A is set and read out and then address B is set and read

out.

No.1542–7/14

LC3101

(2) Timing for application of ASTRB pulse when data is read out by application of DREQ signal (refer to (6)

below) and then address B is set and read out.

(6) Request of ROM data at the following address

When the signal shown below is applied to the IC, the IC begins to read out data at the address immediately

following the address at which preceding data is read out.

Falling of 8th DREQ pulse (MODE=’L’)
Falling of 1st DREQ pulse (MODE=’H’)

Shown below is Timing Chart.

Note) Apply ROM data request signal after T

For the numeric value of T

, refer to Electrical Characteristics.

CYCLE

or more has elapsed.

CYCLE

(7) Power-down mode

When the input at CE pin is set to ‘H’ level, the LC3101 enters power-down mode (each block inside the IC stops

its operation,with no unnecessary current dissipated.). At this mode, the IC inside becomes as follows and current
dissipation is reduced.

(1) Input at input ports (ASTRB, DREQ, A0 to A3) is inhibited.

(It should be noted that if input is floating, current drain increases.)
(2) Both address decoder and data selector in 128K-bit ROM matrix stop their internal operation.
(3) Output at 3-state output pins DOUT, D0 to D7 is floating or fixed. (The user can select either of the two. Refer

to “User mask”) When CE is set to ‘H’, in addition to reduction in current drain as mentioned above, 4 internal

counters (ASTRB COUNTER, 18-BIT ADDRESS COUNTER, READ PULSE COUNTER, DREQ

COUNTER) are initialized in readiness for readout after power-down mode release (CE=’L’).

No.1542–8/14

LC3101

User mask

(1) CHIP SELECT DECODER

User mask option which makes IC chip select signal (select, nonselect) with 214 to 217 bits of 18-bit addresses.

Shown below is the output modes including CE pin conditions.

'L'=EC)nwod-rewoP('H'=EC

tcelespihC

.snip

tcelesnonpihC

.ecnadepmi

7Dot0D,TUODmorfdettuptuosiATAD

hgihasahsnip7Dot0D,TUODtatuptuO

.ecnadepmi

)etoN(.dettuptuodnadleh

Note) In this case, the IC only, having CHIP SELECT DECODER whose 214 to 217 bits are all 0, outputs data and

all others have a high impedance.

(2) SW mask

SW mask controls output at DOUT, D0 to D7 output pins in the following two ways at power-down mode.
The user can select either of the two beforehand.
(i) Output at DOUT, D0 to D7 pins is set to a high impedance.
(ii)Data immediately before power-down mode is held and outputted.

Sample Application Circuit (1)

One word to one key correspondence

sisrucco'H'=ECerofebyletaidemmiataD

hgihasahsnip7Dot0D,TUODtatuptuO

No.1542–9/14

Sample Application Circuit (2)

CPU control : Edit and synthesis with CPU
(The mask ROM and a 64k-bit EPROM are used jointly.)

LC3101

Specifications

Absolute Maximum Ratings at Ta = 25˚C, VSS=0V

retemaraPlobmySsnoitidnoCsgnitaRtinU

egatlovylppusmumixaMV

egatlovtupnIV

egatlovtuptuOV

tnerructuptuOI

noitapissidrewopelbawollAxamdP07+ot03–=aT°C 002Wm

erutarepmetgnitarepOrpoT 07+ot03–

erutarepmetegarotSgtsT 521+ot55–

Allowable Operating Range at Ta = –30 to +70˚C, VSS=0V, VDD=4.5 to 6.5V

retemaraPlobmySsnoitidnoC

egatlovylppuSV

egatlovlevel-hgihtupnI

egatlovlevel-woltupnI

ycneuqerfkcolcgnitarepOf

htdiwesluplevel-hgihkcolcgnitarepOt

htdiwesluplevel-wolkcolcgnitarepOt

xamVDDnip 0.7+ot3.0–V

DD

NI

O

O

VDDnip5.40.55.6V

DD

VHI17Dot0DnahtrehtosniptupnillA
VHI2snip7Dot0D2.2V
VLI17Dot0DnahtrehtosniptupnillA
VLI2snip7Dot0D 6.0V

TC

HOw
LOw

sniptupnillAVot3.0–

sniptuptuollAVot3.0–

niprep,sniptuptuollA 0.2+ot0.2–Am

06+ot03–=aT,1.giF°C 051008069zHk

1.giF3.0sµ

1.giF74.0sµ

sgnitaR

nimpytxam

V7.0

DD

3.0+V

DD

3.0+V

DD

V3.0

DD

˚C
˚C

tinU

V

V

No.1542–10/14

LC3101

Electrical Characteristics at Ta = –30 to +70˚C, VDD=4.5 to 6.5V, VSS=0V

retemaraPlobmySsnoitidnoC

tnerruclevel-hgihtupnII

tnerruclevel-woltupnII

egatlovlevel-hgihtuptuOV

egatlovlevel-woltuptuOV

tnerrucegakaelFFOtuptuO

ecnaticapacniptupnIC

ecnatsiserpu-lluPR

niardtnerruC

I
I

I
I

AC Characteristics at Ta = –30 to +70˚C, VDD=4.5 to 6.5V, VSS=0V, RL=200kΩ, CP=50pF

retemaraPlobmySsnoitidnoC

emitputessserddAT

emitdlohsserddAT

htdiwesluplevel-hgihBRTSAT
htdiwesluplevel-wolBRTSAT
htdiwesluplevel-hgihQERDT

htdiwesluplevel-wolQERDT

noitarudeslupBRTSAT

noitarudeslupQERDT

1emitsseccaatadMORT
2emitsseccaatadMOR2CATf

DOTQERD

TUO

emitelcyCT

emityaledT

emityaled3-0DOTLESDT

VNIV=

HI
LI

HO
LO

1FFO
2FFO

I

pu

1DD
2DD

TSDA
DHDA
HRTS
LRTS
HQRD

LQRD

BRTSA

QERD

1CA

TFHS
LESD

ELCYC

DD

VNIV=

SS

I
I
VOV=
VOV=

f

f

Am3.0–=

HO

Am3.0= 6.0V

HO

DD
SS

3.giF3.0sµ

3.giF3.0sµ

3.giF5.1sµ

4.giF5.1sµ

TC
TC

6.giF6.0sµ

7.giF3.0sµ

TC

D,7Dot0D,

nip0.1Aµ

TUO

D,7Dot0D,

nip0.1–Aµ

TUO

10/00,AVE/PEMfoniphcaE020001kΩ

f,edomgnitarepotA

TC

2.giF,zHk069=0.2Am

05+ot03–=aT,edomgnitareponontA°2.giF,C0.1Aµ

1etoN,5.giF,.pytzHk002=0.62sµ
1etoN,5.giF,.pytzHk002=0.62sµ

1etoN,8.giF,.pytzHk002=6.03sµ

VDD6.0–

sgnitaR

nimpytxam

0.1Aµ

0.1–Aµ

501Fp

sgnitaR

nimpytxam

3.0sµ

3.0sµ

3.0sµ

3.0sµ

tinU

V

tinU

No.1542–11/14

Fig. 1 Input waveform at CT pin

Fig. 2

LC3101

IDD (1) Test Circuit (A) IDD (1) Test Circuit (B) IDD (2) Test Circuit

Fig. 3 Fig. 4

No.1542–12/14

Fig. 5 (1)

Fig. 5 (2)

LC3101

Fig. 6 Fig. 7

Fig. 8

Note 1 Use the following formulas to calculate TAC max, Tcycle max.

TAC max= +0.6µs Tcycle max= +0.6µs

5000

fCT (kHz)

6000

fCT (kHz)

No.1542–13/14

LC3101

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of July, 2001. Specifications and information herein are subject to
change without notice.

PS No.1542–14/14