Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CMOS IC
128K-Bit CMOS Mask ROM
Ordering number:ENN1542
LC3101
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Overview
The LC 3101 is a 128k-bit CMOS mask ROM that contains an interface connectable direct to the speech synthesizer IC LC8100. With one piece of this mask ROM, approximately 100 seconds of speech synthesis can be attained. Since it also contains an interface connectable direct to an EPROM, speech synthesis can be attained by
using this mask ROM and an EPROM jointly.
A selection of 8-bit, 4-bit, or single-bit output data is allowed by means of external control. This mask ROM is
also suited for use in applications other than speech syn-
thesis.
Features
• ROM capacity : 128K bits
• Access time : 25.6µs typ (for operation at 200kHz typ).
• Cycle time : 30.6µs typ (for operation at 200kHz typ).
• Funciton
(1) Contains an interface to an EPROM.
(2) Contains an interface to the LC8100 (sepeech
synthesizer IC).
(3) Possible to select the bit length of output data.
8-bit data
4-bit data
Single-bit data
• Low power dissipation : CMOS
• Current drain :
2mA max (at operating mode).
1µA max (at nonoperating mode).
• Single +5V power supply.
+2.7 to 6.0V (supply voltage range).
• Package : DIP24
Package Dimensions
unit:mm
3014A-DIP42
[LC3101]
42
1
1.2 2.54
unit:mm
3025B-DIP42S
42
1
0.95
53.2
0.5
[LC3101]
37.9
0.48
22
13.8
15.24
21
4.25
5.1max
4.1
1.2
22
21
1.78
0.51min
SANYO : DIP42
13.8
15.24
4.25
5.1max
3.8
0.51min
1.15
SANYO : DIP42S
0.25
0.25
73101TN (KT)/7024KI, TS No.1542–1/14
LC3101
Pin Assignment
Equivalent Circuit Block Diagram
A0 to A3 : 18-bit address setting pins
ASTRB : A0 to A3 strobe pin
DREQ : ROM data request pin
DOUT : ROM data serial output pin
CT : Basic operation clock input pin
D0 to D7 : 8-bit input/output pins
MODE : DREQ pin input pulse count control pin
DSEL : Output bit length select pin
CE : Power-down control pin
EA0 to EA17 : 18-bit address output pins
Description of Operation of Internal Block
• ASTRB COUNTER : Block which internally sets address information applied in 5 steps from A0 to A3
pins.
• 18bit ADDRESS COUNTER : Address counter organized with 18 bits.
• READ PULSE COUNTER : Block which generates signal to operate address decoder, data selector.
• CHIP SELECT DECODER : Makes chip select signal with 214 to 217 bits or 18-bit address.
• 128kbit ROM MATRIX : ROM matrix cell organized with 128K bits.
• PARALLEL TO SERIAL : Shift register which serially outputs 8-bit parallel data to DOUT pin.
• I/O PORT : Selects input/output at D0 to D7 pins.
No.1542–2/14
Pin Description
.oNniPemaNniPtuptuo/tupnInoitcnuF
43BRTSAtupnI sserddatadehctalebot3Aot0AatadsesuachcihwlangisebortsgnittupnirofniP
53QERDtupnI.niptupnilangistseuqeratadMOR
63TUODtuptuO nipsiht,0018CLehthtiwnoitcnujnocnidesunehW.yllairesatadMORgnittuptuorofniP
73TCtupnI ehthtiwnoitcnujnocnidesunehW.edisniMORfokcolcnoitarepocisabgnittupnirofniP
83ECtupnI dnarewopfonoitacilpparetfayletaidemmiedisniCIfonoitazilaitinignillortnocrofniP
6VSS–.ylppusrewopfoV0otdetcennoC
82VDD–.ylppusrewopfoedis+otdetcennoC
9210/00tupnIVottessyawlA
7EDOMtupnI situo-daeratadMORnehW.nipQERDtasesluptupniforebmungnillortnocrofniP
8LESDtupnI 2,'H'ottessiLESDnehW.stib4nidemrofrepsituo-daeratadMORnehwdesU
90D
011D
212D
313D
414D
515D
616D
717D
72AVE/PEMtupnIVotdetcennocronepO
033A
132A
231A
330A
10AE
21AE
32AE
43AE
54AE
815AE
916AE
027AE
128AE
229AE
3201AE
4211AE
5221AE
6231AE
9341AE
0451AE
1461AE
2471AE
tuptuo/tupnI .stib8niatadgnittupnidnastib8niatadMORgnittuptuorofsniP
tupnI dettupnisinoitamrofnisserdda,edomgnittessserddatA.sserddatib-81gnittesrofsniP
tuptuO.sniptuptuosserddatib-81
LC3101
.edomgnittes
.'L'otECtes,tuo
.
SS
.0018CLehtfonipNIDotdetcennocsi
.0018CLehtfonipTCotdetcennocsinipsiht,0018CL
-daeratadMORronoitazisehtnysgnimrofreproF.)nwod-rewop(potsnoitarepolanretni
.'H'otEDOMtes,stib4rostib8nidemrofrep
.snip3D0Dotdettuptuoerastib
.
DD
.spets5nidrawnwodtibredro-hgihmorfstib4yb
situo-daeratadMORnehW.'L'otEDOMtes,tibelgnisaniyllairesdemrofrep
4
7
2ot
No.1542–3/14
LC3101
How to use the mask ROM and an EPROM jointly
The mask ROM and an external EPROM can be used jointly. Two selections of operation mode shown below are
available by high-order 4 bits (EA14 to EA17) of 18-bit address.
sniPedoMnoitarepO7Dot0D
)1(tuptuO .TUODdna7Dot0DsniptaderevilederastnetnocMORksamehT
)2(tupnI .TUODniptaderevilederadna7Dot0DsnipmorfnidaererastnetnoctuptuoMORPEehT
How to select the operation mode
The LC3101 contains a 4-bit chip select decoder (user option : Refer to “User mask”). Coincidence or uncoincidence
with high-order 4 bits (EA14 to EA17) of 18-bit address is detected to select the operation mode.
edoMnoitarepOredoceDtceleSpihCfostib41013CLfonoitarepO
)1(71AEot41AEhtiwecnedicnioCedomtuptuO:7Dot0DsniP
)2(71AEot41AEhtiwecnedicniocnUedomtupnI:7Dot0DsniP
Fig.1 shows the schematic diagram of the control section related to these operation modes. Fig. 2 shows the assignment of 256K-byte (128k bits × 16) that can be specified by 18-bit address.
Fig. 1 Schematic Diagram of Control Section
edomelbanedaerMORksaM
edomtibihnidaerMORksaM
Fig. 2 Address Space Assignement
No.1542–4/14
LC3101
ROM Data Readout Procedure
The following flowchart shows the outline of readout procedure. (1) to (7) give a more detailed description.
(1) Initialization of internal mode
There are 4 counter blocks (ASTRB counter, 18-bit ADDRESS counter, READ PULSE counter, DREQ counter)
inside the LC3101. Since initialization is required immediately after application of power, apply one ‘H’ level
pulse to CE pin. When CE is set to ‘L’ level, the power-down mode is released (refer to (7) ) and it is possible to
start readout any time.
(2) Setting of bit length of readout data
For the bit length of ROM data output, a selection of 3 lengths is allowed : 8 bits, 4 bits, and a single bit. For
controlling this selection, MODE, DSEL pins are used. The following Table shows 3 types of pin setting.
EDOM
LESD
'L'
'H'– )etoN(htgneltib-4
'L''H'
htgneltib-elgniS
)sisehtnyshceeps(
rohtgneltib-4rotib-8
)etoN(htgneltib-4
(Note) When DSEL is set to ‘L’, 20 to 23 bits are outputted at D0 to D3 pins.
When DSEL is set to ‘H’, 24 to 27 bits are outputted at D0 to D3 pins.
No.1542–5/14
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