No. 5452-2/7
LB1955
Electrical Characteristics at Ta = 25°C, VCC= 12 V
Note: * is provided for when X is the peak value at the 60° position of the lower side of the UIN1 Hall amplifier input: THPG = 1.17X.
Parameter Symbol Conditions
Ratings
Unit
min typ max
[Power Supply]
Current drain I
CC
VC= 0 V, LCTR = 6 V 7.0 10.0 13.0 mA
IC internal power supply V
REF
4.75 5.0 5.25 V
[Output]
Output saturation voltage V
O(sat)
1
I
O
= 400 mA Sink side 0.4 V
V
C
= 5 V, Rf= 0 Ω Source side 1.5 V
Output saturation voltage 2 V
O(sat)
2
I
O
= 800 mA Sink side 0.7 V
V
C
= 5 V, Rf= 0 Ω Source side 2.0 V
3-phase output current ripple Ior I
O
= 100 mA, Rf = 0.47 Ω –5 +5 %
[Hall Amplifier]
Input offset voltage VHoff –20 +20 mV
Input bias current IHb
V
AGC
= 1.4 V
U
IN
10 µA
V
IN
, W
IN
5 µA
Common-mode input voltage range
V
HCM
2.2 5.0 V
[Control]
VC pin input bias current I
VCb
VC= 0 V –10 –1.3 µA
Control start voltage V
THVC
Rf= 0.47 Ω, IO≥ 10 mA
2.25 2.5 2.75 V
With the Hall input logic fixed
Open-loop control gain G
MVC
Rf= 0.47 Ω, ∆IO= 200 mA
0.72 0.9 1.08 A/V
With the Hall input logic fixed and VG shorted to RF
[PG]
PG Hall amplifier
V
PGoff
Design target –10 +10 mV
input offset voltage
Peak hold charge current I
SHCHG
(U, V, W) = (L, L, H) 30 µA
PG comparator threshold THPG Design target* 117 %
PG output high-level voltage V
PGH
4.5 5.2 V
PG leakage current I
LEAKPG
–10 0 +10 µA
[FG]
Back emf Schmitt input
V
SCHG
In the back emf Schmitt input increasing direction, Design target 100 mV
hysteresis width
In the back emf Schmitt input decreasing direction, Design target 0 mV
Ringing canceller Schmitt
V
SCHR
In the Schmitt input increasing direction, Design target 180 mV
input hysteresis width
In the Schmitt input decreasing direction, Design target –20 0 +20 mV
FG output high-level voltage V
FGH
FGR = 0 V 4.5 5.2 V
FG leakage current I
LEAKFG
–10 0 +10 µA
[TSD]
Thermal shutdown
TTSD Design target 180 °C
operating temperature
Thermal shutdown
∆TSD Design target 15 °C
temperature hysteresis width