Sanyo LB1923M Specifications

Ordering number : EN6067

Monolithic Digital IC

LB1923M

Power Brushless Motor Pre-Driver IC

for OA Equipment

Overview

including lock protection, current limiter, and

The LB1923M is a pre-driver IC that supports direct PWM drive and is appropriate for the power brushless motors used in office automation equipment. A motor drive circuit with the desired output capability (voltage and current characteristics) can be constructed by attaching a driver array at the IC output. The LB1923M includes on chip a speed control circuit that allows the motor speed to be varied using an external clock.

Features

•Direct PWM drive output

•Speed discriminator + PLL speed control circuit

•FG and integrating amplifiers

•Forward/reverse switching circuit

•Braking circuit (short braking)

•Speed lock detection output

•Full complement of on-chip protection circuits,

Specifications

Absolute Maximum Ratings at Ta = 25°C

thermal shutdown protection circuits.

Package Dimensions

unit: mm

3148-QFP44MA
					[LB1923M]
					13.2		1.6
					10.0
	1.6			1.0	0.8 0.35	1.0		0.2
				33		23
			34			22
13.2	10.0	1.0
		0.8					2.8max
		1.0	44			12
				1		11		0.1
								2.5
					11.6		0.8

SANYO: QIP44MA

Parameter	Symbol	Conditions	Ratings	Unit
Maximum supply voltage	VCC max		9	V
Maximum input current	IREG max	VREG pin	10	mA
Output current	IO max	UL, VL, and WL outputs	30	mA
Allowable power dissipation	Pd max		0.9	W
Operating temperature	Topr		–20 to +80	°C
Storage temperature	Tstg		–55 to +150	°C

Allowable Operating Ranges at Ta = 25°C

Parameter	Symbol	Conditions	Ratings	Unit
Supply voltage	VCC		4.4 to 7.0	V
Input current range	IREG	VREG pin (7 V)	1 to 5	mA
FG Schmitt output applied voltage	VFGS		0 to 8	V
FG Schmitt output current	IFGS		0 to 5	mA
Lock detection output current	ILD		0 to 20	mA

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

63099TH(OT) No. 6067-1/17

LB1923M

Allowable power dissipation, Pdmax – W

Pd max — Ta

1.2

1.0

0.9

0.8

0.6

0.504

0.4

0.2

0	0	20	40	60	80	100	120
–20

Ambient temperature, Ta – °C

Electrical Characteristics at Ta = 25°C, VCC = 6.3 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
		ICC1			42	60	mA
	Current drain	ICC2	In stop mode		10	20	mA
		ICC3	VCC = 5 V		38	55	mA
		ICC4	VCC = 5 V, In stop mode		8	18	mA
	Output saturation voltage	VO (sat)	UL, VL, WL output, IO = 20 mA		0.2	0.7	V
	Output current	IO	UH, VH, WH output, VOUT = 1.4 V	–20	–16	–12	mA
	Output leakage current	IO leak	UL, VL, WL output			100	µA
	Output off voltage	VO off	UH, VH, WH output			0.5	V
	[Hall Amplifier]
	Input bias current	IHB(HA)		–4	–1		µA
	Common-mode input voltage range	VICM		1.5		VCC – 1.5	V
	Hall input sensitivity	VIN(HA)		60			mVp-p
	Hysteresis	VIN(HA)		17	32	60	mV
	Input voltage low → high	VSLH		8	16	30	mV
	Input voltage high → low	VSHL		–30	–16	–8	mV
	[CR Oscillator]
	Output high-level voltage	VOH(CR)1		3.1	3.4	3.7	V
		VOH(CR)2	VCC = 5 V	2.4	2.7	3.0	V
	Output low-level voltage	VOL(CR)1		1.5	1.8	2.1	V
		VOL(CR)2	VCC = 5 V	1.1	1.4	1.7	V
	Oscillator frequency	f (CR)	R = 75 kΩ , C = 1500 pF		19		kHz
	Amplitude	V(CR)1		1.4	1.6	1.8	Vp-p
		V(CR)2	VCC = 5 V	1.1	1.3	1.5	Vp-p
	[CROCK Oscillator]
	Output high-level voltage	VOH(RK)1		3.2	3.5	3.8	V
		VOH(RK)2	VCC = 5 V	2.5	2.8	3.1	V
	Output low-level voltage	VOL(RK)1		0.8	1.1	1.4	V
		VOL(RK)2	VCC = 5 V	0.6	0.9	1.2	V
	External capacitor charge current	ICHG1		–17	–13	–9	µA
	External capacitor discharge current	ICHG2		9	13	17	µA
	Oscillator frequency	f (RK)	C = 0.068 µF		35		Hz
	Amplitude	V(RK)1		2.2	2.4	2.6	Vp-p
		V(RK)2	VCC = 5 V	1.7	1.9	2.1	Vp-p

Continued on next page.

No. 6067-2/17

LB1923M

Continued from preceding page.

	Parameter		Symbol	Conditions		Ratings		Unit
					min	typ	max
	[VCO Oscillator]
	Pin C output high-level voltage		VOH(C)1		4.1	4.3	4.6	V
			VOH(C)2	VCC = 5 V	3.2	3.4	3.6	V
	Pin C output low-level voltage		VOL(C)1		3.6	3.9	4.1	V
			VOL(C)2	VCC = 5 V	2.8	3.0	3.2	V
	Oscillator frequency		f (C)				1.0	MHz
	Amplitude		V(C)		0.2	0.4	0.6	Vp-p
	[Current Limiter Operation]
	Limiter		VRF		0.47	0.52	0.57	V
	[Thermal Shutdown Operation]
	Thermal shutdown operating temperature		TSD	Design target value	150	180		°C
	Hysteresis		TSD	Design target value		30		°C
	[VREG Pin]
	VREG pin voltage		VREG		6.7	7.1	7.4	V
	[FG Amplifier]
	Input offset voltage		VIO(FG)		–10		+10	mV
	Input bias current		IB(FG)		–1		+1	µA
	Output high-level voltage		VOH(FG)		VCC – 1.5	VCC – 1		V
	Output low-level voltage		VOL(FG)			1	1.5	V
	FG input sensitivity			Gain: 100×	3			mV
	Schmitt amplitude for the next stage				100	180	250	mV
	Operating frequency range						16	kHz
	Open-loop gain			f (FG) = 2 kHz	45	51		dB
	[FGS Output]
	Output saturation voltage		VO(FGS)	IO(FGS) = 2 mA		0.1	0.5	V
	Output leakage current		IL(FGS)	VO = VCC			10	µA
	[Speed Discriminator Output]
	Output high-level voltage		VOH(D)		VCC – 1.0	VCC – 0.7		V
	Output low-level voltage		VOL(D)			0.4	1.1	V
	[Speed Control PLL Output]
	Output high-level voltage		VOH(P)1		4.05	4.35	4.65	V
			VOH(P)2	VCC = 5 V	3.25	3.55	3.83	V
	Output low-level voltage		VOL(P)1		1.85	2.15	2.45	V
			VOL(P)2	VCC = 5 V	1.25	1.55	1.85	V
	[VCO PLL Output]
	Output high-level voltage		VOH(VCO)		5.3	5.6		V
	Output low-level voltage		VOL(VCO)			0.4	11	V
	[Lock Detection]
	Output saturation voltage		VOL(LD)	ILD = 10 mA		0.1	0.5	V
	Output leakage current		IL(LD)	VO = VCC			10	µA
	Lock range				–6.25		+6.25	%
	[Integrator]
	Input offset voltage		VIO(INT)		–10		+10	mV
	Input bias current		IB(INT)		–0.4		+0.4	µA
	Output high-level voltage		VOH(INT)		VCC – 1.2	VCC – 0.8		V
	Output low-level voltage		VOL(INT)			0.8	1.2	V
	Open-loop gain				60			dB
	Gain-bandwidth product					1.6		MHz
	Reference voltage		VB(INT)		–5%	VCC/2	5%	V
	[Filter Amplifier]
	Input bias current		IB(FIL)		–0.4		+0.4	µA
	Output high-level voltage		VOH(FIL)		VCC – 1.2	VCC – 0.8		V
	Output low-level voltage		VOL(FIL)			0.8	1.2	V
	Reference voltage		VB(FIL)1		–5%	2.0	+5%	V
			VB(FIL)2	VCC = 5 V	1.5	1.6	1.7	V

Continued on next page.

No. 6067-3/17

LB1923M

Continued from preceding page.

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	[S/S Pin]
	Output high-level voltage	VOH(S/S)		4.0		VCC	V
	Output low-level voltage	VOL(S/S)		0		1.5	V
	Hysteresis	VIN(S/S)1		0.35	0.45	0.55	V
		VIN(S/S)2	VCC = 5 V	0.24	0.34	0.44	V
	Pull-up resistance	RU(S/S)		45	63	85	kΩ
	[F/R Pin]
	Input high-level voltage	VIH(F/R)		4.0		VCC	V
	Input low-level voltage	VIL(F/R)		0		1.5	V
	Hysteresis	VIN(F/R)1		0.35	0.45	0.55	V
		VIN(F/R)2	VCC = 5 V	0.24	0.34	0.44	V
	Pull-up resistance	RU(F/R)		45	63	85	kΩ
	[BR Pin]
	Input high-level voltage	VIH(BR)		4.0		VCC	V
	Input low-level voltage	VIL(BR)		0		1.5	V
	Hysteresis	VIN(BR)1		0.35	0.45	0.55	V
		VIN(BR)2	VCC = 5 V	0.24	0.34	0.44	V
	Pull-up resistance	RU(BR)		45	63	85	kΩ
	[CLK Pin]
	Input high-level voltage	VIH(CLK)	Design target value	4.0		VCC	V
	Input low-level voltage	VIL(CLK)	Design target value	0		1.5	V
	Hysteresis	VIN(CLK)1	Design target value	0.35	0.45	0.55	V
		VIN(CLK)2	VCC = 5 V, Design target value	0.24	0.34	0.44	V
	Pull-up resistance	RU(CLK)		45	63	85	kΩ
	Input frequency	f (CLK)				16	kHz
	[N1 Pin]
	Input high-level voltage	VIH(N1)		4.0		VCC	V
	Input low-level voltage	VIL(N1)		0		1.5	V
	Hysteresis	VIN(N1)1		0.35	0.45	0.55	V
		VIN(N1)2	VCC = 5 V	0.24	0.34	0.44	V
	Pull-up resistance	RU(N1)		45	63	85	kΩ
	[N2 Pin]
	Input high-level voltage	VIH(N2)		4.0		VCC	V
	Input low-level voltage	VIL(N2)		0		1.5	V
	Hysteresis	VIN(N2)1		0.35	0.45	0.55	V
		VIN(N2)2	VCC = 5 V	0.24	0.34	0.44	V
	Pull-up resistance	RU(N2)		45	63	85	kΩ
	[Low Voltage Protection]
	Operating voltage	VSDL			3.75		V
	Release voltage	VSDH			4.0		V
	Hysteresis	VSD		0.15	0.25	0.35	V

Speed Discriminator Counts

N1	N2	Number of counts
High or open	High or open	64
High or open	L	256
L	High or open	128
L	L	512

No. 6067-4/17

LB1923M

Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN–.)

Item		F / R = L			F / R = H			Output
	IN1	IN2	IN3	IN1	IN2		IN3	Source	Sink
1	H	L	H	L	H		L	VH	UL
2	H	L	L	L	H		H	WH	UL
3	H	H	L	L	L		H	WH	VL
4	L	H	L	H	L		H	UH	VL
5	L	H	H	H	L		L	UH	WL
6	L	L	H	H	H		L	VH	WL

S/S Pin

High or open	Stop
L	Start

BRK Pin

High or open	Brake
L	Released

Pin Assignment

VREG		V		WH		WL		VH		VL		UH		UL		RF		IN3		IN3
		CC																–		+
33		32		31		30		29		28		27		26		25		24		23

CR 34

CROCK 35

R 36

C 37

(frame) GND 38

(frame) GND 39

(frame) GND 40

FILO 41

FILI 42

INTREF 43

TOC 44

1		2		3		4
OUT		IN		OUT		OUT
INT		INT		D		P

LB1923M

5		6		7
LD		BR		F/R

								22	IN2–
									IN2+
					21
									IN1–
					20
									IN1+
					19
					18				GND (frame)
					17				GND (frame)
					16				GND (frame)
									FGIN–
					15
									FGIN+
					14
									FGOUT
					13
					12				FGSOUT
8		9				11
				10
CLK		S/S		N1		N2			Top view

A11831

No. 6067-5/17

			LB1923M
	Pin Functions
	Pin	Pin No.		Function
	IN1+, IN1–	19, 20	Hall inputs for the phases
	IN2+, IN2–	21, 22
			The logic high level corresponds to the state VIN+ > VIN–.
	IN3+, IN3–	23, 24
	UH	27
	VH	29	Outputs. These are fixed-current source outputs.
	WH	31
	UL	26	The duty is controlled by the output pin PWM.
	VL	28
			These are open collector sink outputs.
	WL	30
	VCC	32	A capacitor must be inserted between this pin and ground to prevent noise entering the circuit.
	VREG	33	7-V shunt regulator output
	GND	16 to 18	Ground
		38 to 40
	CR	34	Used to set the PWM circuit oscillator frequency.
			Motor lock protection circuit. Reference signal oscillator connection. Used by the circuit that prevents incorrect
	CROCK	35	operation if the clock line is disconnected.
			A capacitor must be inserted between this pin and ground.
	R	36	VCO circuit. This pin sets the charge and discharge current. A resistor must be inserted between this pin and ground.
	C	37	VCO oscillator connection. A capacitor must be inserted between this pin and ground. Select a value for that capacitor
			such that the C pin oscillator frequency does not exceed 1 MHz.
	FILI	42	Inverting input to the VCO filter amplifier. This pin is connected to the VCO PLL through an (IC internal) 10-kW resistor.
	FILO	41	VCO filter amplifier output. This pin is connected to the VCO circuit internally.
	DOUT	3	Speed discriminator output. A low level is output when the motor is over speed.
	ROUT	4	PLL circuit output. Outputs the result of the phase comparison between 1/2fCLK and 1/2fFG.
	LD	5	Lock detection output. This is an open collector output.
			This pin outputs a low level when the motor speed is within the locked range (±6.25%).
	INTREF	43	Integrating amplifier noninverting input (the 1/2 VCC potential)
	INTIN	2	Integrating amplifier inverting input
	INTOUT	1	Integrating amplifier output
	TOC	44	Torque command input. Normally, this pin is connected to the INTOUT pin. Lowering the TOC pin potential increases
			the torque by changing the PWM signal duty for the UL, VL, and WL outputs.
	FGIN+	15	FG amplifier noninverting input (the 1/2 V	potential). A capacitor must be inserted between this pin and ground.
				CC
	FGIN–	14	FG amplifier inverting input
	FGOUT	13	FG amplifier output
	FGSOUT	12	FG amplifier (post-Schmitt) output. This is an open collector output.
	RF	25	Output current detection. A resistor must be inserted between this pin and ground.
			This resistor sets the maximum output current IOUT to be 0.5/Rf.
	S/S	9	Start/stop control input. Apply a low level for start, and either a high level or an open (high-impedance) state for start.
	F/R	7	Forward/reverse control input. Apply a low level for forward, and either a high level or an open (high-impedance) state
			for reverse.
	BR	6	Braking control input (short braking operation). Apply a low level for start, and either a high level or an open (high-
			impedance) state to brake the motor.
	CLK	8	External clock signal input. 10 kHz max.
	N1	10	Speed discriminator count value selection inputs
	N2	11

No. 6067-6/17