Sanyo LB1890M Specifications

Ordering number : EN4354

73098HA (OT)/20593TS A8-9675, 9414 No. 4354-1/8

Overview

The LB1890M is a 3-phase DD motor driver IC and is an
ideal FDD spindle motor driver for 3.5 inch applications.

Functions and Features

• Three phase total wave linear driver

• Eliminates need for output electrolytic capacitor
(however, depending on the motor, this may not apply)

• On-chip digital speed control

• Start/stop circuit

• Current limiter circuit

• On-chip index comparator (single HYS)

• On-chip index delay circuit

• AGC circuit

• Temperature protection circuit

Package Dimensions

unit: mm

3129-MFP36S

SANYO: MFP36S

[LB1890M]

LB1890M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

FDD Spindle Motor Driver

Monolithic Digital IC

Specifications

Absolute Maximum Ratings at Ta = 25°C

Allowable Operating Conditions at Ta = 25°C

Parameter Symbol Conditions Ratings Unit

Supply voltage range V

CC

4.2 to 6.5 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

CC

max 7.0 V

Maximum output current I

O

max1 t≤0.5 1.0 A

Steady Maximum output current I

O

max2 0.7 A
Allowable power dissipation Pd max Independent IC 1 W
Operating temperature Topr –20 to +80 °C
Storage temperature range Tstg –40 to +150 °C

LB1890M

No. 4354-2/8

Electrical Characteristics at Ta = 25°C, VCC= 5V

Note: *1) Marked values (*1) are guaranteed by the design itself and therefore do not require measurement.

*2) When hall-effect input becomes larger, kick-back occurs to the output waveform and for this reason, 200 m Vp-p or less is recommended.

Ratings

Parameter Symbol Conditions

min typ max

Unit Note

Current drain

I

CCO

1 VCC= 5.0V (Stop) 0.2 mA

ICC1 VCC= 5.0V (Steady) 20 30 mA

Time changeover bias current I

SL

0.4 mA

Time changeover input voltage 1 V

SLL

0 0.8 V

Time changeover input voltage 2 V

SLH

2.0 V

CC

V

S/S1 bias current I

S/S1

0.4 mA

S/S1 start voltage V

S/S1

2.0 V

CC

V

S/S1 stop voltage V

S/S1

0 0.8 V

S/S2 bias current I

S/S2

0.1 mA

S/S2 start voltage V

S/S2

0 0.8 V

S/S2 stop voltage V

S/S2

2.0 V

CC

V

Hall-effect bias amplifier input current I

HB

20 µA
In-phase input voltage range Vh 2.2 VCC– 0.7 V
Differential input voltage range Vdif 70 250 mVp-p *2
Input offset voltage Vho ±1.0 mV *1
Hall-Effect output voltage V

H

IH= 5mA 1.5 1.8 V

Leak current I

HL

Stop ±10 µA

Output saturation voltage

Vsat1 I

O

= 0.35A, VCC= 4.2V 1.2 1.4 V

(Sink plus source)

Vsat2 I

O

= 0.70A, VCC= 4.2V 1.5 2.0 V

Output leak current I

OL

±1.0 mA
Current limiter Vref1 0.27 0.30 0.33 V
Control amplifier voltage gain G

C

–6 dB

Voltage gain phase differential ▲▲G

C

±1 dB
Integrated amplifier internal reference voltage Vref2 VCC/2 V
Integrated amplifier bias current Iib ±1 µA

Integrated output voltage amplitude

Vi

+

Ii = –0.5 mA with reference of Vref2

0.75 V

Vi

–

Ii = 0.5 mA with reference of Vref2

–1.4 V
Gain band width 1000 kHz *1
FG amplifier input voltage V

FG

5 100 mVp-p

FG amplifier voltage gain G

FG

Open loop 60 dB *1
FG amplifier input offset VFG0 ±10 mV
FG amplifier internal reference voltage V

FGB

2.20 2.50 2.80 V

Schmitt hysteresis width

▲▲Vsh1 “H”

→ “L” 25 mV *1

▲▲Vsh2 “L” → “H” 25 mV *1

Schmitt input operation level Vsh 1 V

CC

–1 V
Speed disk recount number N 992
Disk recount out “L” level voltage V

DL

ID= –0.5mA 0.3 V

Disk recount out “H” level voltage V

DH

ID= 0.5mA VCC–0.4 V

Disk recount out leak current I

DI

±1.0 µA

Disk recount operation frequency F

D

1.0 MHz *1

Oscillation range F

OSC

1.0 MHz *1

Index bias current I

IDB

±10 µA

In-phase input voltage range V

ID

1.5 VCC–0.5 V

Hysteresis setting current range I

IDO

5 10 15 µA

Index output “L” level voltage V

IDL

VID= 5V 0.4 V

Index output “H” level voltage V

IDH

VID= 5V 4.5 V

Break-down voltage V

DLDC

VID= 5V 2.50 V

Delay output “L” level voltage V

DLL

VID= 5V 0.4 V

Delay output “H” level voltage V

DLH

VID= 5V 4.5 V
Excessive heat protected operating temperature TSD 150 180 °C *1
Hysteresis width ▲▲TSD 40 °C *1

LB1890M

No. 4354-3/8

Pin Assignment

Block Diagram

[Top view]

Unit (resistance: Ω, capacitance: F)

LB1890M

No. 4354-4/8

Pin Description

Pin No. Symbol Pin voltage Equivalent circuit Pin description

5 W

–

2.2V min • W-phase hall-effect input pin.

6 W

+

VCC–0.7V max W+> W–is established when logic is at an “H”

level.

7 V

–

• V-phase hall-effect input pin.8 V

+

V+> V–is established when logic is at an
“H” level.

9 U

–

• U-phase hall-effect input pin.

10 U

+

U+> U–is established when logic is at an
“H” level.

11 HB 1.5V typ • Minus pin for hall-effect bias.

(IH= 5mA) When stopped, switches open and hall-

effect bias severs.

12 FC • Frequency characteristics revision pin

By installing a capacitor between this pin
and GND, close-loop oscillation for the
current control system halts.

13 I

+

1.5V min • Index input pin.

14 I

–

VCC–0.5V max When the I+pin is at an “L” level, I1 operates

with the fixed current of I1 = 10 µA and when
at an “H” level, I1 does not flow

.
Hysteresis width is determined by the
resistor attached externally to the I+pin.

15 SL “L”: 0.8V max • Time changeover pin.

“H”: 2.0V min 1 : 1.2

“L” level : “H” level

17 X1 • Reference clock generating pin.

18 X2

19 GND • Ground pin.

Grounded as with pins 1 and 36.

Unit (resistance: Ω)

Continued on next page.

Continued from preceding page.

LB1890M

No. 4354-5/8

Pin No. Symbol Pin voltage Equivalent circuit Pin description

20 ID “L”: 0.4V max • Index pulse output pin.

“H”: 4.5V min
(When V

ID

equals 5 V)

21 DT1 • Pin connecting the external CR for the

delay time constant circuit.

22 DT2 • Break-down current setting pin for the

delay time constant circuit.

23 DTO “L”: 0.4V max • Index delay pulse output pin.

“H”: 4.5V min
(When V

ID

equals 5 V)

24 FG0 • FG amplifier output pin.

25 FG

–

• FG amplifier negative input pin.

26 FG

+

2.48V • FG amplifier positive input pin.
(When V

ID

Generates reference voltage within IC.

equals 5 V)

27 S/S1 “L”: 0.8V max • Start/stop changeover pin.

“H”: 2.0V min “H” level active.

28 S/S2 “L”: 0.8V max • Start/stop changeover pin.

“H”: 2.0V min “L” level active.

Unit (resistance: Ω)

Continued on next page.

LB1890M

No. 4354-6/8

Continued from preceding page.

Pin No. Symbol Pin voltage Equivalent circuit Pin description

29 DO • Speed discriminator output pin.

30 IAI • Integrated amplifier input pin.

31 IAO • Integrated amplifier output pin.

32 VID • Index pulse output and index delay pulse

output power supply pin.
For applications when VCCequals 5 V,
VCC= VID= 5 V.

33 V

CC

• Total power supply voltage pin except for
VID.
Voltage must be stable and free of ripple
and noise interference.

34 R

f

• Output current detection pin.
By installing an Rfresistor between this
pin and VCC, output current is detected as
voltage. Voltage detection at this pin
activates the current limiter.

35 U

OUT

• U-phase output pin.

36 Pow GND • Output transistor ground pin.

1 Sub GND • Ground pin.

Grounded as with pins 19 and 36.

2 V

OUT

• V-phase output pin.

3 W

OUT

• W-phase output pin.

4 AGC • AGC pin.

Controls hall-effect amplifier gain in
response to hall-effect input frequency.

Unit (resistance: Ω)

LB1890M

No. 4354-7/8

Truth Table

Source → Sink

Hall-Effect Input

U V W
1 V-phase → W-phase H H L
2 V-phase → U-phase L H L
3 W-phase → U-phase L H H
4 W-phase → V-phase L L H
5 U-phase → V-phase H L H
6 U-phase → W-phase H L L

When an “H” level exists for hall-effect input,

U+> U

–

V+> V

–

W+> W

–

Index and Timing Chart

When SL equals an “H” level,

• T’ ≈ 0.693CR6

• t’ ≈

CR6R7

{

0.405 + 1n

(

R6 – R7

)

}

R6 + R7 R6 – 2R7

When SL equals an “L” level,

• T’ ≈ 0.577CR6

• t’ ≈

CR6R7

{

0.522 + 1n

(

0.781R6 – R7

)

}

R6 + R7 R6 – 2R7

Using only the ID pulse involves shorting DT1 and DT2.

PS No. 4354-8/8

LB1890M

This catalog provides information as of July, 1998. Specifications and information herein are subject to change
without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.