Sanyo LB1871M Specifications

Page 1

Ordering number : EN4849

91494TH (OT) B8-1284, 1288 No. 4849-1/10

Overview

The LB1871 and LB1871M are three-phase brushless motor driver ICs that are optimal for LBP and LBF polygon mirror motor drive. The LB1871 and LB1871M are versions of the LB1870 and LB1870M in which the value of the divisor has been changed.

Functions and Features

• Single-chip implementation of all circuits required for LBP polygon mirror motor drive (speed control and driver circuits)

• Low motor drive noise level due to the current linear drive scheme implemented by these ICs. Also, small capacitors suffice for motor output oscillation suppression, with certain motors not requiring these capacitors at all.

• Extremely high rotational precision provided by PLL speed control.

• Built-in phase lock detector output

• Four motor speed modes set by switching the clock divider provided under internal clock/crystal oscillator operation. This supports 240, 300, 400 and 480 dpi.

• Use of an external clock allows arbitrary motor speeds.

• Built-in FG and integrating amplifiers

• Full set of built-in protection circuits, including current limiter, undervoltage protection, and thermal protection circuits.

Package Dimensions

unit: mm

3147A-DIP28HS

unit: mm

3129-MFP36SLF

SANYO: DIP28HS

[LB1871]

SANYO: MFP36SLF

[LB1871M]

LB1871, 1871M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Three-Phase Brushless Motor Driver

Monolithic Digital IC

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max 30 V

Maximum output current I

max T < 0.1 s 1.0 A

Allowable power dissipation (1)

Pd max1-1 Independent IC (DIP28HS) 3.0 W

Pd max1-2 Independent IC (MFP36SLF) 0.95 W Allowable power dissipation (2) Pd max2 With an arbitrarily large heat sink 20 W Operating temperature Topr –20 to +80 °C Storage temperature Tstg –55 to +150 °C

Page 2

Allowable Operating Conditions at Ta = 25°C

Electrical Characteristics at Ta = 25°C, VCC= 24 V

No. 4849-2/10

LB1871, 1871M

Parameter Symbol Conditions Ratings Unit

Supply voltage range V

20 to 28 V

6.3 V fixed voltage output current I

REG

0 to –15 mA

LD pin voltage V

0 to +28 V

FGS pin voltage V

FGS

0 to +28 V

LD pin output current I

0 to +10 mA

FGS pin output current I

FGS

0 to +5 mA

Parameter Symbol Conditions min typ max Unit

Current drain I

Stop mode 22 32 mA

[Output saturation voltage]: V

AGC

= 3.5 V

Source (1) Vsat

1-1IO

= 0.6 A, Rf= 0 Ω 1.8 2.5 V

Source (2) Vsat

1-2IO

= 0.3 A, Rf= 0 Ω 1.6 2.3 V

Sink (1) Vsat

2-1IO

= 0.6 A, Rf= 0 Ω 0.5 1.0 V

Sink (2) Vsat

2-2IO

= 0.3 A, Rf= 0 Ω 0.25 0.7 V

Output leakage current I

(LEAK) VCC= 28 V 100 µA [6.3 V fixed voltage output] Output voltage V

REG

5.8 6.3 6.8 V

Voltage variation ∆V

REG1VCC

= 20 to 28 V 200 mV

Load variation ∆V

REG2IO

= 0 to –10 mA 200 mV

Temperature coefficient ∆V

REG3

Design target value 0 mV/°C

Short circuit current ISV

REG

Design target value 70 mA [Hall input block] Input bias current I

(HA) 2 10 µA

Differential input range V

HIN

Sine wave input 50 350 mVp-p Common-mode input range V

ICM

Differential input: 50 mVp-p 3.5 VCC– 3.5 V Input offset voltage V

IOH

Design target value –20 +20 mV [Undervoltage protection] Operating voltage V

8.4 8.8 9.2 V

Hysteresis ∆V

0.2 0.4 0.6 V [Thermal protection] Thermal shutdown operating

TSD Design target value (junction temperature) 150 180 °C

temperature Hysteresis ∆TSD Design target value (junction temperature) 40 °C [Current limiter operation] Limiter V

0.52 0.58 0.63 V [FG amplifier] Input offset voltage V

(FG) Design target value –10 +10 mV

Input bias current I

(FG) –1 +1 µA

DC bias level V

(FG) –5% 1/2 V

REG

+5% V

Output high level voltage V

(FG) No external load V

REG

– 1.3 V

REG

– 0.8 V

Output low level voltage V

(FG) No external load 0.8 1.2 V [FG Schmitt block] Input hysteresis (high to low) V

SHL

0 mV

Input hysteresis (low to high) V

SLH

150 mV

Hysteresis V

FGL

100 200 mV

Input operating level V

FGSIL

400 mVp-p

Output saturation voltage V

FGS

(sat) I

FGS

= 4 mA 0.2 0.4 V

Output leakage current I

FGS

(LEAK) VCC= 28 V 10 µA

Continued on next page.

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Continued from preceding page.

No. 4849-3/10

LB1871, 1871M

Parameter Symbol Conditions min typ max Unit [Error amplifier] Input offset voltage V

(ER) Design target value –10 +10 mV

Input bias current I

(ER) –1 +1 µA

DC bias level V

(ER) –5% 1/2 V

REG

+5% V

Output high level voltage V

(ER) No external load V

REG

– 1.0 V

Output low level voltage V

(ER) No external load 1.0 V [Phase comparator output] Output high level voltage V

PDH

No external load V

REG

– 0.4 V

Output low level voltage V

PDL

No external load 0.4 V

Output source current I

VPD= V

REG/2

–0.6 mA

Output sink current I

–

VPD= V

REG/2

1.5 mA [Lock detector output] Output saturation voltage V

(sat) ILD= 5 mA 0.1 0.4 V

Output leakage current I

(LEAK) VCC= 28 V 10 µA [Drive block] Dead zone V

50 100 300 mV

Output idling voltage V

6 mV

Forward gain G

0.4 0.5 0.6

Reverse gain G

–

–0.6 –0.5 –0.4

Accelerate command voltage V

STA

5.0 5.6 V

Decelerate command voltage V

STO

0.8 1.5 V

Forward limiter voltage V

Rf= 22 Ω 0.58 V

Reverse limiter voltage V

–

Rf= 22 Ω 0.58 V [Reference signal block] Crystal oscillator frequency f

OSC

Crystal oscillator mode 1 8 MHz Low level pin voltage V

OSCLIOSC

= –0.5 mA 4.4 V

High level pin voltage I

OSCHVOSC

= V

OSCL

+ 0.3 V 0.5 mA [External clock input block] External input frequency f

CLK

External clock mode 500 7000 Hz

Input high level voltage V

(CLK) 3.5 V

REG

Input low level voltage V

(CLK) 0 +1.5 V

Input open voltage V

(CLK) 3.5 4.0 4.7 V

Hysteresis V

(CLK) 0.27 0.4 0.53 V

Input high level current I

(CLK) V (CLK) = V

REG

155 200 µA

Input low level current I

(CLK) V (CLK) = 0 V –400 –300 µA [N1 pin] Input high level voltage V

(N1) 3.5 V

REG

Input low level voltage V

(N1) 0 +1.5 V

Input open voltage V

(N1) 3.5 4.0 4.7 V

Input high level current I

(N1) V (N1) = V

REG

155 200 µA

Input low level current I

(N1) V (N1) = 0 V –400 –300 µA [N2 pin] Input high level voltage V

(N2) 4.0 V

REG

Input middle level voltage V

(N2) 2.0 3.0 V

Input low level voltage V

(N2) 0 +1.0 V

Input open voltage V

(N2) 3.5 4.0 4.7 V

Input high level current I

(N2) V (N2) = V

REG

155 200 µA

Input low level current I

(N2) V (N2) = 0 V –400 –300 µA [S/S pin] Input high level voltage V

(S/S) 3.5 V

REG

Input low level voltage V

(S/S) 0 +1.5 V Input open voltage V

(S/S) 3.5 4.0 4.7 V

Hysteresis V

(S/S) 0.27 0.4 0.53 V

Input high level current I

(S/S) V (S/S) = V

REG

155 200 µA

Input low level current I

(S/S) V (S/S) = 0 V –400 –300 µA

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Pin Assignments

No. 4849-4/10

LB1871, 1871M

(Top view)

Page 5

Pin Functions

Equivalent Circuit Block Diagram

No. 4849-5/10

LB1871, 1871M

Symbol Function Notes

IN1 to 3

Hall element input Taken as high when IN

> IN–, and as low otherwise.

IN1 to 3

–

OUT1 to 3 Outputs Capacitors are inserted between these pins and ground.

GND1 Sub-ground Output block ground. Connect to GND2. GND2 Ground Ground for circuits other than the output block.

Output current detection

Connect a small resistor between this pin and ground. Set the maximum output current so that I OUT = 0.58/R

Power supply

REG

Power supply stabilization output

Connect a capacitor between this pin and GND2. Internal circuit power supply stabilization.

OSC Crystal oscillator 8 MHz max

E. CLK External clock 7 kHz max

FC Control amplifier frequency correction Connect a capacitor between this pin and GND2.

EI Error amplifier input EO Error amplifier output LD Phase lock detector output On when the PLL phase is locked. This pin is an open collector output. PD Phase comparator output PLL phase comparator output

N1, N2 Divisor switching

S/S Start/stop

Start on low. Stop on high or open.

FGS FG pulse output

Pulse output following the FG Schmitt comparator. This pin is an open-collector output.

FG OUT FG amplifier output A minimum amplitude of 400 mVp-p is required.

FG IN

–

FG amplifier input

AGC AGC amplifier frequency characteristics correction Connect a capacitor between this pin and GND2.

Page 6

Sample Application Circuit

Clock Divisor Switching

Note: An open input is taken as a high level input.

PLL servo frequency = (crystal oscillator frequency)/(divisor)

Crystal Oscillator Usage

No. 4849-6/10

LB1871, 1871M

Pin N1 Pin N2 Divisor

H H 5120 (5

× 1 × 1024) L H 10240(5 × 2 × 1024) H L 8192 (4 × 2 × 1024) L L 6144 (3 × 2 × 1024)

— M EXT. CLK

Page 7

External Component Values (reference values)

Note: Use a crystal that has a ratio of at least 1:5 between the fundamental f0 impedance and the 3f0 impedance.

Three Phase Logic Truth Table

Columns H1 to H3 H: H

> H

–

L: H+< H

–

Columns OUT1 to OUT3 H: Source L: Sink

LB1871 Functional Description and External Components

1. Speed control circuit This IC provides high-precision stable motor control with minimal jitter by adopting a PLL speed control scheme. This PLL circuit compares the rising edge of the CLK signal with the falling edge of the FG Schmitt output and outputs that phase error. When an internal clock is used, the FG servo frequency is determined by the formula shown below. Thus the motor speed is determined by the number of FG pulses and the crystal oscillator frequency.

fFG(servo) = f

OSC

: Crystal oscillator frequency

N: Clock divisor

2. Three-phase full-wave current linear drive This IC adopts a three-phase full-wave current linear drive to hold motor noise to an absolute minimum. When switching the output transistor phase, it creates a two-phase excitation state, suppresses kickback, and smooths the output waveform. This suppresses motor noise. Note that since oscillation may occur with some motors, the capacitors C12, C13, and C14 (about 0.1 µF) are connected between the OUT pins and ground.

3. Current limiter circuit The current limiter circuit limits the current (i.e., the peak current) to a level determined by the formula I = 0.58/Rf. A scheme in which the output stage drive current is limited is adopted for the limiting operation. Therefore, the phase compensation capacitor C7 (about 0.1 µF) is inserted between FC and ground.

4. Grounding

GND1 (pin 11 in the LB1871, pin 5 in the LB1871M).........................................Output block ground (sub-ground)

GND2 (pin 28 in the LB1871, pins 1, 2, 17 to 20, 35, and 36 in the LB1871M)..Control circuit ground. GND1 and GND2 should be connected on the circuit board by the shortest distance that occurs in the pattern. Also, the Rfresistor R8 ground node and the GND1 and GND2 pattern line should be grounded to a single point on the connector.

No. 4849-7/10

LB1871, 1871M

Crystal (MHz) C1 (pF) C2 (pF) R (kΩ)

3 to 4 39 82 0.82 4 to 5 39 82 1.0 5 to 7 39 47 1.5

7 to 10 39 27 2.0

H1 H2 H3 OUT1 OUT2 OUT3

H L H L H M H L L L M H H H L M L H L H L H L M L H H H M L L L H M H L

Page 8

5. External interface pins

• LD pin

Output type: open collector Breakdown voltage: 30 V absolute maximum Saturation voltage manufacturing variation reference value (ILD= 10 mA): 0.10 to 0.15 V

• FGS pin

Output type: open collector Breakdown voltage: 30 V absolute maximum Saturation voltage manufacturing variation reference value (I

FGS

= 4 mA): 0.15 to 0.30 V A hysteresis comparator converts the FG amplifier output to a pulse signal to create the FGS output, which is used for speed monitoring. The pull-up resistor is not required if this pin is not used.

• S/S pin (start/stop pin)

Input type: A pnp transistor whose base is pulled up to the internal 6.3 V power supply through a 23 kΩ resistor, and is pulled down to ground through a 40 kΩ resistor. Threshold level (low → high): about 2.8 V Threshold level (high → low): about 2.4 V The LB1871 goes to stop mode with this pin in the open state.

• CLK input pin

• N1 pin

• N2 pin

Input type: The base of a pnp transistor is pulled up to the internal 6.3 V power supply through a 23 kΩ resistor, and is pulled down to ground through a 40 kΩ resistor. Threshold level (low → high): about 1.5 V Threshold level (high → low): about 3.6 V

6. FG amplifier R1 and R2 determine the FG amplifier gain, with the DC gain G being R2/R1. C2 and C3 determine the FG amplifier frequency characteristics, with R1 and C2 forming a high-pass filter and R2 and C3 forming a low-pass filter. Since a Schmitt comparator follows the FG amplifier directly, R1, R2, C2, and C3 must be chosen so that the FG amplifier output is at least 400 mVp-p. (It is desirable for the FG amplifier output to be set up to be between 1 and 3 V during steady state rotation.) The FG amplifier is often the cause when capacity becomes a problem in noise evaluation. One solution to that problem is to insert a capacitor of between 1000 pF and 0.1 µF between FG OUT pin and ground.

7. External capacitors

• C1

C1 is the AGC (automatic gain control) pin smoothing capacitor. This pin is an automatic gain control pin for holding the hall amplifier output amplitude fixed. This pin outputs the three-phase hall signal envelope, and is smoothed with a capacitor (about 0.1 µF) since it has ripple. When the hall input amplitude is small, the AGC pin potential will rise, and when the input amplitude is large, the AGC pin potential will fall.

• C10

C10 is required for fixed voltage power supply stability. Since the output from the 6.3 V fixed voltage power supply is supplied to all circuits within the IC, noise on this signal must be avoided. This power supply must be adequately stabilized so that malfunctions due to noise do not occur.

• C11

C11 is required for VCCstabilization. Since, just as with C10, noise must be avoided, this capacitor is provided to adequately stabilize the power supply. The length of the pattern lines used to connect capacitors C1, C10, and C11 between their respective pins and GND2 must be kept as short as possible. C10 and C11 require special care, since the pattern line length can easily influence their characteristics.

No. 4849-8/10

LB1871, 1871M

Page 9

8. Oscillator pin A crystal oscillator and an RC circuit is connected to the LB1871’s OSC pin. To avoid problems when selecting the oscillator and the capacitor and resistor values, confirm these values with the oscillator’s manufacturer. The pnp transistor and resistor circuit shown in the figure can be used to apply an external signal (of a few MHz) to the OSC pin.

fin = 1 to 8 MHz

Input signal level: High level voltage: 4.0 V minimum Low level voltage: 1.5 V maximum

It will be necessary to insert a capacitor of a certain size if there is overshoot or undershoot in the input waveform. Contact your Sanyo representative for more information on this point if necessary.

Use the LB1871 V

REG

output for the VDD= 6.3 V case.

9. IC internal power dissipation calculation example (calculated at VCC= 24 V, standard ratings)

• Power dissipation due to current drain

P1 = VCC× ICC= 24 V × 22 mA = 0.53 W

• Power dissipation when a –10 mA load current is drawn from the 6.3 V fixed voltage power supply.

P2 = (VCC– V

REG

) × I load = 17.7 V × 10 mA = 0.18 W

• Power dissipation due to the output drive current

(When IO= 0.1 A, the inter-coil voltage V Rm = Rm × IO, and the reverse voltage = 15 V)

P3 = (IO/100) × [(VCC– 0.7 V) + ((VCC– V Rm)/2) – 0.7 V] + V

/16 kΩ

= 1 mA × (23.3 V + 3.8 V) + 24 V2/16 kΩ = 0.06 W

• Power dissipation due to the output transistor

(When IO= 0.1 A, the inter-coil voltage V Rm = Rm × IO, and the reverse voltage = 15 V)

P4 = (VCC– V Rm) × IO= 9 V × 0.1 A = 0.9 W

Therefore, the IC’s total power dissipation is: In stop mode:

P = P1 + P2 = 0.71 W

In start mode (When IO= 0.1 A, the inter-coil voltage V Rm = Rm × IO, and the reverse voltage = 15 V)

P = P1 + P2 + P3 + P4 = 1.67 W

No. 4849-9/10

LB1871, 1871M

VDD= 6.3 V typ. (5.8 to 6.8 V) Ra = 4.7 kΩ Rb = 1.3 kΩ V

= 5.0 V typ. (4.5 to 5.5 V) Ra = 2.0 kΩ Rb = 1.0 kΩ

Page 10

PS No. 4849-10/10

LB1871, 1871M

10. Measuring the IC’s temperature rise

• Thermocouple measurement

When using a thermocouple for temperature measurement, attach the thermocouple to a heat sink fin. This temperature measurement technique is straightforward. However, a large measurement error occurs when the heat generation is not in a steady state.

• Measurement using IC internal diode characteristics

We recommend using the parasitic diode that exists between LD and ground in this IC. Remove the external resistor when measuring. (Sanyo data indicates that ILD= –1 mA, about –1.9 mV/°C, when the LD pin is high.)

11. Servo constants The servo constant calculation varies significantly with the motor used, and requires specialized know-how. Thus this should be handled by the motor manufacturer. Sanyo can provide the required IC characteristics data for servo constant calculation, and the motor manufacture should provide the frequency characteristics simulation data for the specified filter characteristics.

This catalog provides information as of July, 1998. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Sanyo LB1871M Specifications

Specifications and Main Features

Frequently Asked Questions

User Manual