SANYO LB11823M Datasheet

Ordering number : ENN7106

80102RM (OT) No. 7106-1/19

Overview

The LB11823M is a direct PWM drive predriver IC for
use with three-phase power brushless motors. The
LB11823M can implement a motor drive circuit with the
desired output capacity (voltage and current) by using
appropriate external transistors. Due to its built-in FG
amplifier and other features, this device is optimal for
motor drive in OA products that use power brushless
motors.

Functions and Features

• Three-phase bipolar drive

• Direct PWM drive

• Built-in FG amplifier and Schmitt comparator circuits

• Braking function (short-circuit braking)

• Built-in forward/reverse switching circuit

• Full complement of built-in protection circuits,
including current limiter, undervoltage protection
circuit, motor lockup protection circuit, and thermal
protection circuit.

• Can be controlled by either a command voltage or the
duty of an input PWM signal.

Package Dimensions

unit: mm

3129-MFP36SD

0.25

15.2

118

36

19

(0.8)

0.35

0.8

2.45max

(2.25)

0.1

7.9

9.2

10.5

0.65

SANYO: MFP36SD

[LB11823M]

LB11823M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Direct PWM Drive Brushless Motor Predriver

for OA Products

Monolithic Digital IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Parameter Symbol Conditions Ratings Unit

Supply voltage 1 V

CC

1 max VCC1 pin 14.5 V

Supply voltage 2 V

CC

2 max VCC2 pin 14.5 V

Supply voltage 3 V

CC

3 max VCC3 pin 20 V

Output current I

O

max Pins UL, VL, WL, UH, VH, WH 40 mA
RF pin applied voltage VRF max 4V
LVS pin applied voltage VLVS max 20 V
TOC pin applied voltage VTOC max V

CC

2V

VCTL pin applied voltage VCTL max 14.5 V

Specifications

Absolute Maximum Ratings at Ta = 25°C

Continued on next page.

No. 7106-2/19

LB11823M

Continued from preceding page.

Parameter Symbol Conditions Ratings Unit
Allowable power dissipation Pd max Independent IC 0.9 W
Operating temperature Topr –20 to +100 °C
Storage temperature Tstg –55 to +150 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply current 1 I

CC

1-1 15 21 mA

Supply current 2 I

CC

1-2 Stop mode 3.5 5 mA
Output block
Output voltage 1-1 V

OUT

1-1 Low level IO= 400 µA 0.1 0.3 V

Output voltage 1-2 V

OUT

1-2 Low level IO= 10 mA 0.8 1.1 V

Output voltage V

OUT

2 High level IO= –20 mA

VCC1 – 1.1 VCC1 – 0.9

V

Temperature coefficient 1-1 ∆V

OUT

1-1 Design target value*, Low level IO= 400 µA 0.2 mV/°C

Temperature coefficient 1-2 ∆V

OUT

1-2 Design target value*, Low level IO= 10 mA –1.5 mV/°C

Temperature coefficient 2 ∆V

OUT

2 Design target value*, High level IO= –20 mA 1.5 mV/°C
12 V Regulator-voltage output (12REG pin)
Output voltage V12REG V

CC

3 = 15 V, IO= –30 mA 11.7 12.1 12.6 V

Voltage regulation

∆12VREG1

VCC3 = 13.5 to 19 V, IO= –30 mA 150 300 mV

Load regulation

∆12VREG2

IO= –5 to –45 mA, VCC3 = 15 V 100 200 mV

Temperature coefficient

∆12VREG3

Design target value* 2 mV/°C
5 V Regulator-voltage output (VREG pin)
Output voltage VREG 4.7 5.0 5.3 V
Voltage regulation ∆VREG1 V

CC

1 = 8 to 13.5 V 40 100 mV
Load regulation ∆VREG2 IO = –5 to –20 mA 5 30 mV
Temperature coefficient ∆VREG3 Design target value* 0 mV/°C

Electrical Characteristics at Ta = 25°C, VCC1 = 12 V, VCC2 = VREG

Parameter Symbol Conditions Ratings Unit

Supply voltage range 1-1 V

CC

1-1 VCC1 pin 8 to 13.5 V

Supply voltage range 1-2 V

CC

1-2 VCC1 pin, with VCC1-VREG short-circuited 4.5 to 5.5 V

Supply voltage range 2 V

CC

2 VCC2 pin 4.5 to VCC1 V

Supply voltage range 3 V

CC

3 VCC3 pin 13.5 to 19 V

Output curent I

O

Pins UL, VL, WL, UH, VH, WH 30 mA
12V constant-voltage output current I12REG –50 mA
5V constant-voltage output current IREG –20 mA
HP pin applied voltage VHP 0 to 13.5 V
HP pin output current IHP 0 to 10 mA
FGS pin applied voltage VFGS 0 to 13.5 V
FGS pin output current IFGS 0 to 7 mA

Allowable Operating Range at Ta = 25°C

Continued on next page.

Note*: These items are design target values and are not tested.

No. 7106-3/19

LB11823M

Parameter Symbol Conditions

Ratings

Unit

min typ max
Hall Amplifier Block
Input bias current IHB (HA) –2 –0.5 µA
Common-mode input voltage range 1 VICM1 Hall device used 0.5

VCC1 – 2.0

V

Common-mode input voltage range 2 VICM2 For input one-side bias (Hall IC application) 0 V

CC

1 V
Hall input sensitivity 50 mVp-p
Hysteresis width ∆V

IN

(HA) 20 30 50 mV

Input voltage L

→ H VSLH (HA) 5 15 25 mV
Input voltage H → L VSHL (HA) –25 –15 –5 mV
VCTL pin
Input voltage 1 VCTL1 Output duty 0% 1.05 1.4 1.75 V
Input voltage 2 VCTL2 Output duty 100% 3.0 3.5 4.1 V
Input bias current 1 IB1 (CTL) VCTL = 0 V –80 –60 µA
Input bias current 2 IB2 (CTL) VCTL = 5 V 60 80 µA
PWM oscillator (PWM pin)
Output H level voltage

VOH(PWM)

2.75 3.0 3.25 V

Output L level voltage

VOL(PWM)

1.0 1.2 1.3 V
External C charge current ICHG VPWM = 2.1 V –60 –45 –30 µA
Oscillator frequency f (PWM) C = 1000pF 17.6 22 26.8 kHz
Amplitude V (PWM) 1.6 1.8 2.1 Vp-p
TOC pin
Input voltage 1 VTOC1 Output duty 0% 2.72 3.0 3.30 V
Input voltage 2 VTOC2 Output duty 100% 0.99 1.2 1.34 V
Input voltage 1L VTOC1L Design target value*, 0% with V

CC

2 = 4.7 V 2.72 2.80 2.90 V

Input voltage 2L VTOC2L Design target value*, 100% with V

CC

2 = 4.7 V 0.99 1.08 1.17 V

Input voltage 1H VTOC1H Design target value*, 0% with V

CC

2 = 5.3 V 3.08 3.20 3.30 V

Input voltage 2H VTOC2H Design target value*, 100% with V

CC

2 = 5.3 V 1.11 1.22 1.34 V
HP pin
Output saturation voltage VHPL I

O

= 7 mA 0.15 0.5 V

Output leakage current IHP leak V

O

= 13.5 V 10 µA
FGS pin
Output saturation voltage VFGS I

O

= 5 mA 0.15 0.5 V

Output leakage current IFGS leak V

O

= 13.5 V 10 µA
FG amplifier
Input offset voltage V

IO

(FG) –10 10 mV
Input bias current IB (FG) –1 1 µA
Output H level voltage V

OH

(FG) IFG0 = –0.2 mA

VREG – 1.2 VREG – 0.8

V

Output L level voltage V

OL

(FG) IFG0 = 0.2 mA 0.8 1.2 V

FG input sensitivity Gain 100-fold 3 mV

Continued from preceding page.

Continued on next page.

Note*: These items are design target values and are not tested.

No. 7106-4/19

LB11823M

Parameter Symbol Conditions

Ratings

Unit

min typ max

Common phase input voltage range VICM 1.2

VREG – 2.0

V
Next-stage Schmidt width 40 80 140 mV
Operation frequency range 10 kHz
Open loop GAIN f (FG) = 2 kHz 45 49 dB
CSD oscillator (CSD pin)
Output H level voltage V

OH

(CSD) 3.2 3.6 4.0 V

Output L level voltage V

OL

(CSD) 0.9 1.1 1.3 V
External C charge current ICHG1 –14 –10 –6 µA
External C discharge current ICHG2 7 11 15 µA
Oscillator frequency f (CSD) C = 0.01 µF 200 Hz
Amplitude V (CSD) 2.2 2.5 2.75 Vp-p
Current limiter circuit (RF pin)
Limiter voltage VRF 0.45 0.5 0.55 V
Low-voltage protection circuit (LVS pin)
Operating voltage VSDL 3.6 3.8 4.0 V
Release voltage VSDH 4.1 4.3 4.5 V
Hysteresis width ∆VSD 0.35 0.5 0.65 V
Thermal shutdown operation (Overheat protection circuit)
Thermal shutdown operating temperature TSD Design target value* (junction temperature) 125 145 165 °C
Hysteresis width ∆TSD Design target value* (junction temperature) 20 25 30 °C
PWMIN pin
Input frequency f (PI) 50 kHz
H level input voltage V

IH

(PI) 2.0 VREG V

L level input voltage V

IL

(PI) 0 1.0 V

Input open voltage V

IO

(PI)

VREG – 0.5

VREG V

Hysteresis width V

IS

(PI) 0.2 0.3 0.4 V

H level input current I

IH

(PI) VPWMIN = VREG –10 0 10 µA

L level input current I

IL

(PI) VPWMIN = 0 V –130 –96 µA
S/S pin
H level input voltage V

IH

(SS) 2.0 VREG V
L level input voltage V

IL

(SS) 0 1.0 V
Input open voltage V

IO

(SS)

VREG – 0.5

VREG V
Hysteresis width VIS (SS) 0.2 0.3 0.4 V
H level input current I

IH

(SS) VS/S = VREG –10 0 10 µA

L level input current I

IL

(SS) VS/S = 0 V –130 –96 µA
F/R pin
H level input voltage V

IH

(FR) 2.0 VREG V

L level input voltage V

IL

(FR) 0 1.0 V

Input open voltage V

IO

(FR)

VREG – 0.5

VREG V

Hysteresis width V

IS

(FR) 0.2 0.3 0.4 V

H level input current I

IH

(FR) VF/R = VREG –10 0 10 µA

L level input current I

IL

(FR) VF/R = 0 V –130 –96 µA

Continued from preceding page.

Continued on next page.

Note*: These items are design target values and are not tested.

No. 7106-5/19

LB11823M

Parameter Symbol Conditions

Ratings

Unit

min typ max
BR pin
H level input voltage V

IH

(BR) 2.0 VREG V

L level input voltage V

IL

(BR) 0 1.0 V

Input open voltage V

IO

(BR)

VREG – 0.5

VREG V

Hysteresis width V

IS

(BR) 0.2 0.3 0.4 V

H level input current I

IH

(BR) VBR = VREG –10 0 10 µA

L level input current I

IL

(BR) VBR = 0 V –130 –96 µA
REVSEL pin
H level input voltage

VIH(REVSEL)

2.0 VREG V

L level input voltage

VIL(REVSEL)

0 1.0 V

Input open voltage

VIO(REVSEL)

VREG – 0.5

VREG V

H level input current

IIH(REVSEL)

VREVSEL = VREG –10 0 10 µA

L level input current

IIL(REVSEL)

VREVSEL = 0 V –130 –96 µA

Continued from preceding page.

1.0

0.4

0.8

0.6

0.2

120100806040200–20

Pd max - Ta

Ambient temperature, Ta - °C

0.36W

0.9W

Allowable power dissipation, Pdmax - W

Independent IC

Note*: These items are design target values and are not tested.

No. 7106-6/19

LB11823M

Three-Phase logic Truth Table (IN = [H] indicates a condition in which IN+ > IN–.)

When the OFF mode is selected during reversing at the REVSEL pin, it is necessary to specify the Hall input condition.
With F/R = “L”, the condition in which the Hall input is entered in the order from 1 to 6 in the above table is considered
the forward rotation and that in the reverse order is considered reversing.
With F/R = “H”, the condition in which the Hall input is entered in the order from 6 to 1 in the above table is considered
the forward rotation and that in the reverse order is considered reversing.

When S/S and PWMIN pins are not used, set the input to the L level voltage.
When REVSEL and BR pins are not used, set the input to the H level voltage or the open condition.

Pin Assignment

F/R = L F/R = H Output

IN1 IN2 IN3 IN1 IN2 IN3 PWM —
1 H L H L H L VH UL
2 H L L L H H WH UL
3 H H L L L H WH VL
4 L H L H L H UH VL
5 L H H H L L UH WL
6 L L H H H L VH WL

S/S pin

Input condition Condition

H or open Stop

L Start

REVSEL pin

Input condition Condition

H or open —

L OFF mode for reversing

BR pin

Input condition Condition

H or open —

L Brake

PWMIN pin

Input condition Condition

H or open Output OFF

L Output ON

NCNC VREG

GND REVSEL HP F/R PWMIN

BR

33

313236 3435

S/S

CSD VCTL PWM

27 2628 24 2325 2129 2230

TOC 12REG VCC3 LVS VCC2

19

20

RF WH WL VH UH

LB11823M

987654321 10 11 12 13 14 15

UL VCC1 IN1+ IN1–VL

IN2+ IN2– IN3+ IN3– FG+

16 17

FG– FGOUT FGS

18