Sanyo LA7615 Specifications

Ordering number : ENN5841

91799RM (OT) No. 5841-1/39

Overview

The LA7615 is an NTSC color TV IC that supports computer control over an I2C bus. In addition to improved quality and increased functionality in color TV products, this IC supports the development of a TV set product line in software and the simplification of end product design. The provision of an I2C bus means that this product can also respond to desires for increased total manufacturing productivity, including improved automation of computer controlled production lines.

Functions

•I2C bus control, VIF, SIF, Y, C, and deflection circuits integrated on a single chip.

Features

• Pursuit of higher integration levels The LA7615 integrates VIF, SIF, luminance, chrominance, and deflection (horizontal and vertical synchronization) circuits, A/V switching, and power supply control on a single chip.

• Bus control for reduced external component counts and mechanical adjustment points All the LA7615 signal-processing circuits can be controlled and adjusted digitally over the I2C bus. All adjustments, both those required during manufacture and the user controls, can be controlled over the I2C bus, and both function selection and characteristics settings can be performed in software over the I2C bus. This increases flexibility in designing a product line of TV sets and also enhances productivity by allowing mixed production runs. While this device supports multifunction and good performance, it is also economical in that it achieves reduced power and reduced pin count.

Package Dimensions

unit: mm

3071-DIP64S

57.2

0.95 0.48 1.78 1.01

4.00.51min

5.0max

19.05

16.8

0.25

3.2

3364

321

SANYO: DIP64S

[LA7615]

LA7615

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Single-Chip NTSC Color TV IC

Monolithic Linear IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

No. 5841-2/39

LA7615

Parameter Symbol Conditions Ratings Unit

V2 max 9.6 V

Maximum supply voltage

V17 max 9.6 V V32 max 9.6 V

V60 max 9.6 V Maximum supply current I24 max 30 mA Allowable power dissipation Pd max Ta ≤ 65°C 1.5 W Operating temperature Topr –10 to +65 °C Storage temperature Tstg –55 to +150 °C

Specifications

Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions Ratings Unit

V2 7.6 V

Recommended supply voltage

V17 7.6 V V32 7.6 V V60 7.6 V

Recommended supply current I24 24 mA

V2 op 7.3 to 7.9 V

Operating supply voltage range

V17 op 7.3 to 7.9 V V32 op 7.3 to 7.9 V V60 op 7.3 to 7.9 V

Operating supply current range I24 op 20 to 30 mA

Operating Conditions at Ta = 25°C

Functional Description

<VIF/SIF Functions> In addition to a PLL synchronous detection system, the IF block also adopts a split system in which the VIF signal and the SIF signal are processed separately.

• Low-level VCO The LA7615 achieves a significant reduction in beat generation due to interference by lowering the VCO oscillator level from that used in earlier ICs.

• Adjustment-free VCO coil implemented using bus control By compensating for manufacturing variations in the VCO coil using bus control, the LA7615 eliminates coil adjustment from the manufacturing line.

• Built-in 4.5 MHz trap The LA7615 incorporates an on-chip trap that also provides a video equalizer function. Thus the number of external trap, inductor, and capacitor components is reduced.

• Built-in SIF FM detector: 4.5 MHz quadrature detection

• The video signal and FM demodulated signal levels can be controlled from the serial bus. The improved precision associated with controlling the output level over the serial bus makes it easier to design the interface with the following stage.

• Built-in buzz canceler Allows high performance to be maintained even during stereo reception.

• Built-in video switch (INT/EXT(AUX) switching circuit) Built-in AUX input switching circuit means that the dedicated switching ICs required can be reduced. Also, the ability to control this switch from the serial bus makes it easier to design the peripheral wiring pattern.

• Dedicated IF video signal output pin The provision of this pin makes it easier to design end products that support PIP and similar features.

<Luminance and Chrominance Circuits> These blocks have been designed to minimize the use of external components as much as possible. The filter circuits are now integrated on the same chip, and not only the adjustment circuits, but also the function selection and characteristics modifications functions can be controlled over the serial bus. As a result, basically all the signal processing from input to output can be performed with only the addition of the chrominance circuit VCO crystal and the APC filter circuit.

Furthermore, this IC also supports high image quality systems and responds to needs from a diverse range of end products.

• Two independent inputs for the luminance and chrominance signals and switching between the Y1/C1 and Y2/C2 inputs

• Video muting on/off switch

• Built-in filters (The filter f0 adjustment function can be used to select the filter characteristics.) Chrominance system: Bandpass filter (symmetric and asymmetric types) Luminance system: Color trap and delay line

• Built-in high image quality variable-type luminance system filter (color trap and delay line) Luminance filter mode selection (f0 adjustment) Four modes are provided: 3.58 MHz trap, 4.2 MHz trap, 5.0 MHz wide, and 10.0 MHz high band.

• Peaking (sharpness) control Aperture type control implemented using the delay line The emphasis frequency is automatically selected according to the f0 mode using the delay line. One of the four frequencies 2.2, 2.6, 3.0, or 4.9 MHz is emphasized according to which of the f0 modes (3.58 MHz trap, 4.2 MHz trap, 5.0 MHz wide, or 10.0 MHz high band) is used.

• Adaptive coring For low-level signals, the above peaking is suppressed to reduce the image contamination due to that peaking. The coring level is automatically adjusted according to the amplitude of the input signal.

• Black stretch circuit: Can be turned on or off under control of the serial bus interface.

• SYO (Selected luminance (Y) output) One of the Y1/Y2 inputs is selected, and that input signal is output as the sync separator circuit signal directly. However, the DC level of that signal is clamped at 1/2 VCC. Also, this signal can be used for closed captions or as a velocity modulation.

• Support for analog/digital OSD Amplitude level limiting is applied to digital input signals internally to the IC.

• Contrast and brightness controls

• ABL (automatic beam limiter) Three-pin system (IB IN, BRT ABL FILT, and CONTRAST ABL FILT pins), mode switching under control of serial bus data.

• R, G, and B output drive and bias adjustments

• Sub-bias (brightness) control The DC level of each of the R, G, and B signals can be adjusted over a 4-step (2-bit) range.

• Built-in chrominance bandpass filter Chrominance system filter mode selection: bandpass filter peaking/symmetric type selection and chrominance bandpass filter bypass on/off setting

• Auto Flesh: Flesh tone correction (on/off)

• Overload (on/off) Limits the saturation of the color when the ratio of the burst and color signals is large, i.e. when the color is highly saturated.

• Color phase and saturation controls

• Demodulation angle: 104°

No. 5841-3/39

LA7615

*: Reference values

Mode f0 = Y signal Chroma signal

Trap f0 *Total delay BPF *Total 500 ns delay 0 3.58 MHz 500 ns Asymmetric (peaking type) 515 ns 1 4.2 MHz 510 ns

Symmetric 535 ns

2 5.0 MHz 520 ns 3 10.0 MHz 265 ns Bypass 265 ns

<Deflection Circuits> Dedicated sync separator circuit input pin The horizontal deflection circuit adopts a dual AFC circuit, and the horizontal oscillator uses the 32fH (503 kHz) pulse signal as the horizontal decrement counter clock. The following are the main settings for the horizontal output system that can be controlled over the serial bus interface. These settings support even more efficient end product design.

• AFC gain (first loop gain control)

• APC gain (second loop gain control)

• Horizontal duty cycle

• Horizontal phase *: The vertical deflection circuit adopts a decrement counter system, and provides constantly adjustment-free and stable

vertical synchronization for any type of signal, from TV on air, to weak reception conditions, to VCR signals. Furthermore, this circuit uses an internal capacitor to implement a ramp generator, and allows the corrections described later in this document to be applied to correct image distortion and other problems due to manufacturing variations in the TV tube itself.

• High-stability adjustment-free horizontal oscillator that uses a ceramic oscillator element

• Dual AFC circuit

• Multi-mode control of the AFC gain (first loop gain)

• Horizontal duty and phase controls

• Geometrical distortion correction: East-west DC (horizontal size)

East-west amplitude (horizontal pin-cushion distortion correction) Corner pin

East-west corner 1 East-west corner 2

Tilt adjustment

• Sync killer

• Forcible non-standard mode support (standard mode: 262.5 H)

• Vertical size/linearity and vertical DC (vertical position) adjustments, vertical S-curve correction

• V-comp adjustment (Corrects for changes in the vertical size due to variations in the luminance.)

• Vertical killer

<Power System> PWM circuits have come to be widely used in TV set power supplies in recent years. This IC integrates parts of the power supply circuit (the pulse generator and its control system) and allows the supply voltage (high B) to be adjusted over the serial bus.

No. 5841-4/39

LA7615

No. 5841-5/39

LA7615

Bus Control

General Functions

ON/OFF SW 1 bit Video muting switch 1 bit

VIF/SIF

Video signal switching 1 bit RF AGC delay 6 bits IF AGC SW 1 bit PLL tuning 7 bits APC detector adjustment 6 bits AFT defeat switch 1 bit Noise inverter defeat switch 1 bit Video level 3 bits Sound 4.5 MHz trap 4 bits FM level 4 bits F0 fast (FM detection speed) 1 bit

Luminance/Chrominance Systems

Y/C input selection (one of two inputs) switch 1 bit Luminance (Y) F0 adjustment (filter control) 2 bits Chrominance signal bandpass filter mode switch 1 bit Chrominance signal bandpass filter bypass switch 1 bit Black stretch on/off switch 1 bit Peaking (sharpness) control 5 bits Coring on/off switch 1 bit Auro flesh on/off 1 bit Overload switch 1 bit Contrast control 6 bits Brightness control 6 bits Tint control 7 bits Saturation control 7 bits RGB bias adjustment 6 bits each RGB bias adjustment 7 bits each Sub-brightness control 2 bits each Brightness ABL operating point control 3 bits Brightness ABL mode defeat switch 1 bit each Emergency ABL defeat switch 1 bit

Deflection System

AFC gain (sync killer) 2 bits APC gain 2 bits Horizontal duty adjustment 2 bits Horizontal phase adjustment 4 bits Geometrical distortion correction EAST-WEST DC 5 bits EAST-WEST AMPLITUDE 4 bits East-west corner 1/2 3 bits each Tilt adjustment 4 bits Vertical linearity adjustment 4 bits Vertical S-curve correction 4 bits Vertical size adjustment 7 bits Vertical DC adjustment 6 bits Standard/nonstandard mode switch 1 bit VERTICAL KILL 1 bit V-COMP adjustment 3 bits DAC REF. (+B TRIM) 4 bits

Others: Status Register

POWER ON RESET 1 bit X-ray protection switch 1 bit Horizontal lock detection 1 bit AFT and RF AGC status discrimination 2 bits each

No. 5841-6/39

LA7615

A10048

Wide

Vertical Linearity

Vertical S-Curve Correction

Tilt

East-West Amp

Corner Pin

The distortion correction operation is symmetric left to right.

Narrow

Wide

Narrow

Wide

East-west corner 1

East-west corner 2

A10049

A10050

A10051

A10052

No. 5841-7/39

LA7615

Bus : Control Register Bit Allocation Map

Control Register Bit Allocations

IC address Sub address MSB Data bits LSB

IC Add7 → Add0 ¥ Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1011 1010 0000 0000 1 On/Off Video AFC gain/sync kill

mute (b1) (b0)

0001 1 APC gain B+ trim

(b1) (b0) (b3) (b2) (b1) (b0)

0010 1 Hor duty cycle Horizontal phase

(b1) (b0) (b3) (b2) (b1) (b0)

0011 1 BNI RF AGC delay

defeat (b5) (b4) (b3) (b2) (b1) (b0)

0100 1 IF AGC AFT FM level

defeat defeat (b4) (b3) (b2) (b1) (b0)

0101 1 VCO free running

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

0110 1 4.5 MHz trap

(b3) (b2) (b1) (b0) (b2) (b1) (b0)

0111 1 Video IF APC offset adjust.

switch (b5) (b4) (b3) (b2) (b1) (b0)

1000 1 Vertical Vertical DC

kill (b5) (b4) (b3) (b2) (b1) (b0)

1001 1 Countdown mode East-west DC

(b1) (b0) (b4) (b3) (b2) (b1) (b0)

1010 1 East-west amp

(b3) (b2) (b1) (b0)

1011 1 Vertical comp. East-west tilt

(b2) (b1) (b0) (b3) (b2) (b1) (b0)

1100 1 Vertical size

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

1101 1 Vertical linearity

(b3) (b2) (b1) (b0)

1110 1 FM mode Vertical S-correction

switch (b3) (b2) (b1) (b0)

1111 1 East-west bottom corner East-west top corner

(b2) (b1) (b0) (b2) (b1) (b0)

Bits are transmitted in this order

No. 5841-8/39

LA7615

Bus : Control Register Bit Allocation Map

Control Register Bit Allocations (cont)

IC address Sub address MSB Data bits LSB

IC Add7 → 0 Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1011 1010 0001 0000 1 Red bias

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

0001 1 Green bias

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

0010 1 Blue bias

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

0011 1 Red drive

(b5) (b4) (b3) (b2) (b1) (b0)

0100 1 Green drive

(b5) (b4) (b3) (b2) (b1) (b0)

0101 1 Blue drive

(b5) (b4) (b3) (b2) (b1) (b0)

0110 1 Blue sub bias Red sub bias Green sub bias Y/C

(b1) (b0) (b1) (b0) (b1) (b0) switch

0111 1 Brightness control

(b5) (b4) (b3) (b2) (b1) (b0)

1000 1 Pix control

(b5) (b4) (b3) (b2) (b1) (b0)

1001 1 Coring Peaking control

switch (b4) (b3) (b2) (b1) (b0)

1010 1 F0 select Chroma Auto Chrom Over

(b1) (b0) BPF flesh bypass load

1011 1 Tint control

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

1100 1 Color control

(b6) (b5) (b4) (b3) (b2) (b1) (b0)

1101 1 ABL Mid Stp EMG Bright ABL threshold

defeat defeat defeat (b2) (b1) (b0)

1110 1 Test register 1 Test register 2

(b3) (b2) (b1) (b0) (b2) (b1) (b0)

1111 1 Test regster 3 Black Stretch Blanking Reserved

(b3) (b2) (b1) (b0) defeat defeat

IC address Sub address MSB Data bits LSB

IC Add7 → Add0 Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1011 1010 0001 0000 Pon XRay Horiz On/off AFT status RF AGC status

lock

0001 1 1 1 1 1 1 1 1

Bits are transmitted in this order

Table 8 : Status Register Bit Allocation Map

Status Register Bit Allocations

No. 5841-9/39

LA7615

Bus : Control Register Truth Table

Control Register Truth Table

Register 0 HEX 1 HEX 2 HEX 3 HEX On/off Off On na na Video mute Active Mute na na AFC gain/sync Kill Sync Kill Low gain (auto mode) Mid gain High gain BNI defeat Enable BNI Defeat na na IF AGC defeat Enable AGC Defeat na na AFT defeat Enable AFT Defeat na na Video switch IF video Aux video na na Vertical Kill Vertical active Vertical Killed na na Countdown mode Standard Non-standard 50 Hz 48 Hz FM mode switch Normal Fast na na Y/C switch Y1/C1 IN Y2/C2 IN na na Coring switch Defeat Enable na na F0 select 3.58 Trap 4.20 Trap 5.00 APF 10.0 APF Chrom BPF Symmetrical Peaker na na Autoflesh Off On na na Chroma bypass BPF Bypass na na Over load Off Active na na Bright ABL defeat Enable Defeat na na Bright mid stop defeat Enable Defeat na na Emergency ABL defeat Enable Defeat na na Black Str defeat Enable Defeat na na Blanking defeat Enable Defeat na na

Bus : Status Register Truth Table

Status Register Truth Table

Register 0 HEX 1 HEX 2 HEX 3 HEX POR Inactive Low standby detected na na XRP Inactive XRP fault detected na na Horizontal lock Locked Unlocked na na On/off Off On na na AFT IF frequency in high IF frequency in range na IF frequency is low RF AGC RF AGC voltage is Low. RF AGC voltage is in range. na RF AGC voltage is High.

No. 5841-10/39

LA7615

Initial Condition

Function On/off 1 HEX Video mute 0 HEX AFC gain & sync Kill 1 HEX APC gain 3 HEX B+ trim 8 HEX Horizontal duty 1 HEX Horizontal phase 8 HEX BNI defeat 0 HEX RF AGC delay 20 HEX IF AGC defeat 0 HEX AFT defeat 0 HEX FM level 10 HEX IF VCO free running 40 HEX

4.5 trap 8 HEX Video level 4 HEX Video switch 0 HEX IF APC offset 20 HEX Vertical Kill 0 HEX Vertical DC 20 HEX Countdown mode 0 HEX East/west DC 10 HEX East/west amplitude 8 HEX Vertical comp. 0 HEX East/west tilt 8 HEX Vertical size 40 HEX Vertical linearity 8 HEX FM mode switch 0 HEX Vertical S-correction 8 HEX East/west bottom 0 HEX East/west top corner 0 HEX Red bias 00 HEX Green bias 00 HEX Blue bias 00 HEX Red drive 3F HEX Green drive 3F HEX Blue drive 3F HEX Blue sub bias 2 HEX Red sub bias1 2 HEX Green sub bias 2 HEX Y/C switch 0 HEX Brightness control 20 HEX Pix control 20 HEX Coring switch 0 HEX Peaking control 00 HEX F0 select 1 HEX Chroma BPF 0 HEX Autoflesh 0 HEX Chroma bypass 0 HEX Over load 0 HEX Tint control 40 HEX Color control 40 HEX Bright ABL defeat 0 HEX Bright mid stop 0 HEX Emergency ABL defeat 0 HEX Bright ABL threshold 0 HEX Test registers 1, 2, 3 0 HEX Black strech defeat 1 HEX Blanking defeat 0 HEX

Power Up Sequence <Reference>

No. 5841-11/39

LA7615

6.3VDC

7.3VDC

3.0VDC

time ≥ 2ms

ON/OFF

= 0

ON/OFF

= 1

Mute

= 0

Initialize

TR1 to TR2

Initialize

TR3 to TR31

Standby

Vcc

ON/OFF

BIT

Registers

(TR1-TR2)

XRP BIT

(STATUS)

Pon BIT

(STATUS)

Registers

(TR3-TR31)

Video.Mute

BIT

Run.Vcc

stable

A10053

After Standby Vcc reaches 3.0VDC, the microcontroller has to wait 2ms in order to intitialize the HC Interface in LA7615.

No. 5841-12/39

LA7615

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Circuit Voltages and Currents]

Horizontal supply voltage HV

7.2 7.6 8 V

IF power supplly current (V2) I2 (IFI

) IF AGC : 5 V 28 43 58 mA

Vertical supply current (V17) I17 (DEFI

)101316mA

Video/chrominance supply current (V32) I32 (YCI

) 65 85 105 mA

FM supply current (V60) I60 (FMI

) 5.5 8.5 11.5 mA

[VIF Block]

No signal AFT output voltage V14 With no input signal 2.8 3.8 4.8 Vdc No signal video output voltage V53 With no input signal 4.7 4.9 5.1 Vdc

APC pull-in range (U) f

After APC, PLL, and D/A converter

1 MHz

adjustment

APC pull-in range (L) f

After APC, PLL, and D/A converter

1 MHz

adjustment

Maximum RF AGC voltage V

CW = 91 dBµ, DAC = 0 7.7 8.2 9.0 Vdc

Minimum RF AGC voltage V

CW = 91 dBµ, DAC = 63 0 0.2 0.4 Vdc

RF AGC Delay Pt (@DAC = 0) RF

AGC0

DAC = 0 96 dBµ

RF AGC Delay Pt (@DAC = 63) RF

AGC63

DAC = 63 86 dBµ

Maximum AFT output voltage V

14H

CW = 93 dBµ, frequency change 6.2 6.5 7.6 Vdc

Minimum AFT output voltage V

14L

CW = 93 dBµ, frequency change 0.5 0.9 1.2 Vdc

AFT detection sensitivity Sf CW = 93 dBµ, frequency change 33 25 17 mV/kHz

4.5 MHz attenuation T

RAP

V100 kHz/V4.5 MHz –35 –32 dB

Video output amplitude V

53 93 dBµ, 87.5% Video MOD 1.8 2 2.2 Vp-p

Synchronizing signal tip level V53

TIP

93 dBµ, 87.5% Video MOD 2.4 2.6 2.8 Vdc

Input sensitivity V

Output –3 dB 43 46 dBµ Vide/sync ratio (@100 dBµ) V/S 100 dBµ, 87.5% Video MOD 2.4 2.5 3 Differential gain DG 93 dBµ, 87.5% Video MOD 2 10 % Differential phase DP 93 dBµ, 87.5% Video MOD 2 10 deg Video signal-to-noise ratio S/N CW = 93 dBµ 55 58 dB 920 kHz beat level I920 V3.58 MHz/V920 kHz –57 –50 dB

[SIF Block]

[1st.SIF]

4.5 MHz conversion gain SG

21 26 31 dB

4.5 MHz output level SV

91 96 101 dB

First SIF maximum input SV

–1 0 +1 dB

[SIF Block]

FM detection output voltage S

OADJ

414 424 434 mVrms

FM limiting sensitivity S

50 dBµ

FM detector output bandwidth S

50 100k Hz

FM detector output distortion S

THD

AM rejection ratio S

AMR

40 dB

SIF. Signal-to-noise ratio S

74 dB

[Chrominance Block]

ACC amplitude characteristics 1 ACC

1 Input: +6 dB/0 dB, 0 dB = 40 IRE 0.8 1.0 1.2 times

ACC amplitude characteristics 2 ACC

2 Input: –14 dB/0 dB 0.8 1.0 1.1 times

B-Y/Y amplitude ratio CLR

75 100 120 %

Color control characteristics 1 CLR

Color: max/normal 1.7 2.0 2.3 times Color control characteristics 2 CLR

Color: max/min 33 40 50 dB Color control sensitivity CLR

1 2 4 %/bit

Tint center TIN

CEN

TINT NOM –10 +5 deg Tint control max TIN

MAX

TINT max 30 45 60 deg Tint control min TIN

MIN

TINT min –60 –45 –30 deg Tint control sensitivity TIN

0.7 2.0 deg/bit Demodulated output ratio: B-Y/R-Y BR 1.06 1.19 1.32 Demodulated output ratio: G-Y/R-Y GR 0.34 0.40 0.46

Electrical Characteristics at Ta = 25°C, VCC= V2 = V17 = V32 = V60 = 7.6 V, ICC= I24 = 24 mA

Continued on next page.

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