Sanyo LA6513A Specifications
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CMOS IC
Single-Chip 4-Bit Microcomputer
for Control-Oriented Applications
(Low-Threshold Input, On-Chip FLT Driver)
Ordering number:EN2367B
LC6512A, LC6513A
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
General Description
The LC6512A, 6513A are microcomputers that are dentical
with FLT driver-contained microcomputers LC6502D,
6505D in instruction set but are further enhanced in performance, such as shorter cycle time, more stack levels, increased FLT drive capacity, and are partially changed in
specifications for standby function. Since the LC6512A,
6513A are also pin-compatible with the LC6502D, 6505D,
they can be used as similar replacements for the LC6502D,
6505D. The LC6512A, 6513A can replace the LC6502B/
6502D, 6505B/6505D to enhance performances of equipment in which these microcomputers have been applied so
far.
(3) The standby function is the same as for the LC6514B
and its using method is different from that of the
LC6502D, 6505D, etc.
Package Dimensions
unit:mm
3025B-D42SIC
[LC6512A]
42
22
15.24
13.8
Features
• Low power dissipation CMOS single-chip microcomputer .
• Instruction set with 79 instructions common to the
LC6502C, 6502B, 6502D/LC6505C, 6505B, 6505D.
• 2-source, 2-level interrupt function (external interrupt/
internal timer interrupt)
• 8-level stack
• 4-bit prescaler-contained 8-bit programmable timer
• FLT driver-contained output ports and low-threshold input ports
(1) Digits driving output ports: 10 pins
(2) Segments driving output ports: 8 pins
(3) Normal voltage input ports: 8 pins (4 pins: Low threshold input port)
(4) Normal voltage input/output ports: 8-pins
• ROM, RAM
(1) LC6512A ROM: 2048bytes, RAM: 128 × 4bits
(2) LC6513A ROM: 1024 bytes, RAM: 64 × 4bits
• Cycle time 1.33µs min.
400kHz, 800kHz, 1MHz, 3MHz ceramic resonator OSC.
• Power-down by 2 standby modes
(1) HALT mode: Power dissipation saving by program
standby during normal operation
(2) HOLD mode: Power supply backup during power
failure
1
unit:mm
3052A-QIP48A
3.0
1.5
0.35
20.0
14.0
1.0
1.5
0.25
1.78
21
3.0
1.5
25
24
13
12
4.25
5.1max
3.8
0.51min
1.15
SANYO : DIP42S
0.15
2.15
2.45max
1.7
SANYO : QIP48A
37.9
1
0.48
[LC6513A]
20.0
14.0
1.0
16.6
0.35
0.95
1.5
36
37
48
O1001TN (KT)/7129YT/7227KI/5317KI/N256KI,TS No.2367–1/24
LC6512A, LC6513A
• Differences among LC6512D, 6513D,and LC6512A, 6513A
The LC6512D, 6513D and LC6512A, 6513A are different in the OSC circuit only and are the same in the basic
features. The differences are shown below.
Item
OSC circuit
configuration
OSC mode
OSC waveform
Operating
frequency
1-stage inverter
Ceramic resonator OSC
Sine wave
Ceramic resonator OSC: 500kHz, 800kHz,1MHz, 3MHz
5-stage inverter
Ceramic resonator OSC, CR OSC, application of external clock
Rectangular wave
Ceramic resonator OSC: 400kHz, 800kHz, 1 MHz
CR OSC: 400kHz typ. 800kHz typ
External clock: 222kHz to 1290kHz
LC6512D. 6513DLC6512A, 6513A
Technical Data
The LC6512A, 6513A are members of our LC6500 series of CMOS microcomputers. For their internal functions, refer to
the LC6500 SERIES USFR′S MANUAL. Those which differ from the description in the USER′S MANUAL are described in this catalog. Carefully study features and Appendix 4 Standby Function in this catalog before using the LC6512A,
6513A.
Pin Assignments
Pin Name
OSC1, OSC2
INT
RES
HOLD
PAO-3
PBO-3
PCO-3
PDO-3
PEO-3
PFO-3
PGO-3
PHO-3
PI0, 1
TEST
: Ceramic resonator for OSC
: Interrupt
: Reset
: Hold
: Input port
: Input port
: Input/output common port
: Input/output common port
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Test
A0–3
B0–3
C0–3
D0–3
E0–3
F0–3
G0–3
H0–3
I0, 1
DIP42S
(Note) Nothing must be connected to NC
pins internally or externally.
When mounting the QIP version on the
board, do not dip it in solder.
QIP48A
No.2367–2/24
System Block Diagram
LC6512A, LC6513A
RAM
F
WR
AC
ALU
DP
E
CTL
OSC
TM
Pin Description
Pin Name
INT
Note*:High-voltage port
: Data memory
: Flag
: W orking register
: Accumulator
: Arithmetic and logic unit
: Data pointer
: E register
: Control register
: Oscillation circuit
: Timer
Input/Output
Input
Interrupt request input pin
STS
ROM
PC
INT
IR
I.DEC
CF, CSF
ZF, ZSF
EXTF
TMF
Function
: Status register
: Program memory
: Program counter
: Interrupt control
: lnstruction register
: lnstruction decoder
: Carry flag, carry save flag
: Zero flag, zero save flag
: External interrupt request flag
: Internal interrupt request flag
HOLD
RES
PA
0-3
Input
Input
Input
HOLD mode request input pin (The LC6502, 6505 differ in function.)
Capable of being used as a general-purpose single-bit input port unless the standby mode is used.
Reset input pin
Input port A0 to A3 (Normal voltage, low-threshold input)
Capable of 4-bit input and single-bit decision for branch
Use also for HALT mode release request input
Continued on next page.
No.2367–3/24
Continued from preceding page.
LC6512A, LC6513A
Pin Name
PB
0-3
PC
0-3
PD
0-3
PE
0-3
PF
0-3
PG
0-3
PH
0-3
Pl
0, 1
Input/Output
Input
Input/Output
Input/Output
Output
Output
Output
Output
Output
Input port B0 to B3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch
Input/output common port C0 to C3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
Input/output common port D0 to D3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
Output port E0 to E3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port F0 to F3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port G0 to G3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port H0 to H3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port I0, I1 (Digit driver output)
Capable of 2-bit output and single-bit set/reset
Capable of 2-bit input of output latch contents and single-bit decision of output latch for branch
Function
0SC1
0SC2
V
DD
V
SS
TEST
Input
Output
Input
Input
A ceramic resonator is connected to this pin and pin OSC2 in the internal clock mode.
Pin for externally connecting a resonance circuit for the internal clock mode
Power supply pin
Normally connected to +5V
Connected to 0V power supply
IC test pin
Normally connected to V
SS(0V)
Specifications
Absolute Maximum Ratings at Ta = 25˚C, VSS=0V
retemaraPlobmySsnoitidnoCsgnitaRtinU
egatlovylppusmumixaMV
egatlovtupnIV
egatlovtuptuO
tnerructuptuokaeP
noitapissidrewopelbawollA
erutarepmetgnitarepOrpoT 07+ot03–
erutarepmetegarotSgtsT 521+ot55–
(Note1) For pin OSCl, up to oscillation amplitude generated when internally oscillated under the recommended
oscillation conditions in Fig. 2 is allowable.
[Note] When mounting the QIP package version on the board, do not dip it in solder.
xam 0.7+ot3.0–V
DD
NI
V
)1(TUO
V
)2(TUO
I
)1(O
I
)2(O
I
)3(O
I
)4(O
)1(xamdP07+ot03–=aT° )egakcaptalF(C053Wm
)2(xamdP07+ot03–=aT°)PID(C006Wm
2CSOD,CstroPVot3.0–
I,H,G,F,EstroPV
1CSOnahtrehtosniptupnlVot3.0–
niphcaE:D,CstroP 0.2+ot0.2–Am
niphcaE:I,F,EstroP 0ot51–Am
niphcaE:H,GstroP 0ot01–Am
IotCstropfosnipllA 61+ot09–Am
DD
DD
Vot54–
DD
DD
)1etoN(3.0+V
3.0+V
3.0+V
˚C
˚C
No.2367–4/24
LC6512A, LC6513A
Allowable Operating Conditions at Ta = –30 to +70°C, VDD = 5V±10%, VSS = 0V,
retemaraPlobmySsnoitidnoC
egatlovylppusgnitarepOV
egatlovylppusnwod-rewoPV
egatlovlevel-hgihtupnI
egatlovlevel-woltupnI
CSO
gnimitybdnatS
rotanosercimarecrofecnaticapaclanretxE
tiucricnacsyekniyaledelbawollA
(Note)* tcyc: Cycle time at microcomputer running mode
V
V
V
V
V
V
V
t
t
t
t
)1(DD
)2(DD
)1(HI
)2(HI
)3(HI
)1(LI
)2(LI
)3(LI
)4(LI
1C.2.giFeeS
2C.2.giFeeS
HD
LD
FDDV
RDDV
V=DLOH:edomDLOH
)3(LI
AtroP9.1V
D,C,BstroP
1CSOdnaDLOH,SER,TNl
D,C,BstroPV
1CSO,SER,TNlV
V:TSET,DLOH
DD
AtroPV
V
DD
V
DD
V5.5ot8.1=V
.3xidneppAni4-3,3-3.sgiFeeS
.1.giFeeS,V5.5ot8.1=0sµ
.1.giFeeS,V5.5ot8.1=0sµ
sgnitaR
nimpytxam
5.40.55.5V
8.15.5V
V
DD
V7.0
DD
V8.0
DD
SS
SS
SS
SS
V
DD
V
DD
V3.0
DD
V2.0
DD
V2.0
DD
5.0V
)2-N(
*cyctX
)2-N(
*cyctX
V
V
V
V
V
tinU
sµ
sµ
Fig. 1 Standby mode timing
[Note]
No chattering shall be applied to the HOLD
pin and PA0 to 3 pins during the HALT
instruction execution cycle.
No.2367–5/24
LC6512A, LC6513A
Electrical Characteristics at Ta = –30 to +70°C, VDD = 5.0V±10%, VSS = 0V
retemaraPlobmySsnoitidnoC
tnerruclevel-hgihtupnII
tnerruclevel-woltupnII
egatlovlevel-hgihtuptuO
egatlovlevel-woltuptuO
tnerruckaelFFOtuptuO
CSOrotanoser
niardtnerruC
ecnaticapactupnIC
ecnaticapactuptuOC
egatlovsiseretsyHV
cimarecrofycneuqerfCSOkcolC
ecnaticapactuptuo/tupnIC
HI
LI
V
)1(HO
V
)2(HO
V
)3(HO
V
)4(HO
V
)5(HO
V
)6(HO
V
)7(HO
V
)8(HO
V
)1(LO
V
)2(LO
I
)1(FFO
I
)2(FFO
I
)3(FFO
I
)4(FFO
f
CSOFC
I
)1(DD
I
)2(DD
I
)3(DD
NI
TUO
OI
H
V:niptupnihcaE
NIV=DD
V:niptupnihcaE
NIV=SS
I:D,CstroP
I:D,CstroP
ItrophcaE(
I:H,GstroP
I:2CSO
HO
I:D,CstroP
I:2CSO
LO
V:D,CstroP
V:D,CstroP
Am1–=V
HO
Aµ001–=V
HO
I:I,F,EstroP
I:I,F,EstroP
I:I,F,EstroP
HO
I:H,GstroP
HO
HO
LO
V:edomTLAH
V:edomDLOH
Am01–=V
HO
Am2–=V
HO
Am1–=
HO
Am2–=V
Aµ001–=V
Am1= 4.0V
Aµ001= 4.0V
V=
TUO
DD
V=
TUO
SS
V:I,H,G,F,EstroP
V:I,H,G,F,EstroP
:2.giFnitiucricCSO2932etoN804zHk
DD
DD
DLOH,SER,TNI V1.0
)Am1–nahtsseL=
ItrophcaE(Am1–=
HO
edomDLOH,0.1Aµ
edomDLOH,0.1–Aµ
V=
TUO
DD
V=
TUO
.zHM3=fedomgnitarepO
V04–03–Aµ
DD
zHk0001,008,004=f;CSOrotanosercimareC 0.10.2Am
Vniptupni,neponiptuptuo
V:derusaemgniebtonsniP
V:derusaemgniebtonsniP
V:derusaemgniebtonsniP
NIV=SS
.zHM1=ftaerusaeM:niptupnihcaE
SS
zHM1=ftaerusaeM:l,H,G,F,EstroP
SS
,zHM1=ftaerusaeM..D,CstroP
SS
3.giFnitiucrictseT,%01±V5=01Aµ
sgnitaR
nimpytxam
0.1–Aµ
0.2–V
DD
5.0–V
DD
8.1–V
DD
0.1–V
DD
VDD5.0–V
0.1–V
DD
)Am1–nahtsseL=V
CSOrotanosercimarecrofsnoitidnocdednemmoceR
,CSOrotanosercimarecrofsnoitidnocdednemmoceR
4.giFnitiucrictseT,V5.5ot8.1=01Aµ
5.0–V
DD
5.0–V
DD
4872etoN618zHk
0892etoN0201zHk
04922etoN0603zHk
7.20.4Am
5Fp
01Fp
01Fp
DD
tinU
0.1Aµ
03Aµ
V
No.2367–6/24
LC6512A, LC6513A
Center frequency
3MHz
1MHz
800kHz
400kHz
Ceramic resonator
CSA3.00MG (Murata)
KBR3.0MS (Kyocera) 22±10%
CSB1000K, D (Murata)
KBR1000H (Kyocera)
CSB800K, D (Murata)
KBR800H (Kyocera)
CSB400P (Murata)
KBR400B (Kyocera)
C1 (pF) C2 (pF)
33±10%
180±10%
180±10%
180±10%
180±10%
330±10%
330±10%
Fig. 2 Recommended OSC circuit, constants
for ceramic resonator OSC
CF: Ceramic resonator
CSA3.00MG (Murata)
KBR3.0MS (Kyocera)
CSB1000K, D (Murata)
KBR1000H (Kyocera)
CSB800K, D (Murata)
KBR800H (Kyocera)
CSB400P (Murata)
KBR400B (Kyocera)
Note 2) There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the
nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic
resonator.
The min., max. values of OSC frequency represent the oscillatable frequency range.
Note 3) When using the piggyback microcomputer, evaluation chip for evaluation, connect a feedback resistor (approxi-
mately lMΩ).
Input/output common ports C, D: Output inhibit
HALT instruction is executed to provide HALT mode.
Fig. 3 IDD(2) test circuit Fig. 4 IDD(3) test circuit
Fig. 5 lnitial reset timing
τVDD: Power supply rise time constant
τ
: RES pin rise time constant
RES
Fix C. R so that τVDD τ
t
: OSC stabilized time
OSC
<
, t
=
RES
10ms. is obtained.
OSC
>
=
No.2367–7/24
LC6512A, LC6513A
Appendix 1. Support System
For application development of the LC6512A, 6513A, the support system for the LC6512A, 6513A is used.
1-1. Software support
The support system provides source editor, cross assembler. For cross assembler on CP/M, the "LC6502.COM",
"LC6505.COM" are used, and on MS-DOS, the ''LC6512.COM", ''LC6513.COM" are used.
1-2. Hardware support
(1) Evaluation chip
Evaluation chip LC6597 is used. Level converters, drivers are connected to high-voltage ports (PE0 to 3, PF0 to 3,
PG0 to 3, PH0 to 3, PI0, 1) externally.
(A dedicated adaptor is available.)
External memory for program
Evaluation chip
General-purpose input
General-purpose input/output
FLT driver output
Fig. 1-1 Basic evaluation system using evaluation chip
(2) Simulation chip
Piggyback LC65PG12/13 and adaptor (EVA-97-12D/13D) for the LC6512A, 6513A are used jointly.
LC65PG12/13
EVA-97-12D/13D
A driver shown in fig. 1-3 is contained.
To user’s application aquipment
Fig. 1-2 How to use piggyback
Conversion board TB42S
No.2367–8/24
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