(Product Code : 126 250 02)
(Europe)
(General PAL area)
IDC-1000ZU
(Product Code : 126 250 03)
(U.S.A.)
(Canada)
8. PARTS LIST.............................................................31
ACCESSORIES & PACKING MATERIALS .............31
CABINET & CHASSIS PARTS 1 ............................. 32
CABINET & CHASSIS PARTS 2 ............................. 34
CABINET & CHASSIS PARTS 3 ............................. 35
ELECTRICAL PARTS ..............................................36
CIRCUIT DIAGRAM (Refer to the separate volume)
PRODUCT SAFETY NOTICE
The components designated by a symbol ( ! ) in this schematic diagram designates components whose value are of
special significance to product safety. Should any component designated by a symbol need to be replaced, use only the part
designated in the Parts List. Do not deviate from the resistance, wattage, and voltage ratings shown.
CAUTION
This product utilizes a laser.
The adjustment other than those specified herein may result in hazardous radiation exposure.
CAUTION : Danger of explosion if battery is incorrectly replaced.
Replace only with the same or equivalent type recommended by the manufacturer.
Discard used batteries according to the manufacturer’s instructions.
NOTE : 1. Parts order must contain model number, part number, and description.
Design and specification are subject to change without notice.
SX111/E, EX, U
2. Substitute parts may be supplied as the service parts.
3. N. S. P. : Not available as service parts.
REFERENCE No. SM5310255
Page 2
1. iD PHOTO DISC
1-1. iD PHOTO DISC HIGH-DENSITY TECHNOLOGY
The iD Photo Disc has a diameter of 5 centimeters and yet it
can store up to 730MB of information. A laser pulse magnetic
field modulation recording method and CAD-type ultra-high
magnetic resolution method have been used to record data
at a track pitch of 0.6 µm and an extremely short mark length
of 0.235 µ, which is smaller than the spot diameter of the
laser beam.
1-2. LASER PULSE MAGNETIC FIELD MODULA TION
RECORDING METHOD
The beam which is generated by the laser pickup in the iD
Photo disc drive focuses onto the disc recording medium as
a spot with a diameter of about 1 µm. During recording, a
mark with a diameter of 0.235 µm -- which is smaller than the
diameter of the laser beam spot-- is recorded. A “laser pulse
magnetic field modulation” recording method has been
adopted in order to achieve this. This recording method involves firstly a magnetic head which applies a magnetic field
which is modulated in accordance with the data supplied externally which is to be recorded. In this state, the laser beam
is directed to the reverse side of the disc. The radiated light
within an 0.6 µm-diameter area at the center of the beam
spot is momentarily heated to a temperature of around 200
degrees. The data is then recorded by means of the resulting
change in the magnetic polarity of the recording layer. The
recording mark which is made by this pulse-type laser beam
is accurately formed in the track at a diameter of 0.6 µm. The
rotation of the disc causes each recording mark to overlap
the preceding mark at a point 0.235 µm forward of the preceding mark. As a result, the circles formed according to the
state of the laser beam move along and leaves a continuous
series of minute crescent-shaped marks 0.235 µm across.
These marks are approximately one-quarter the size of the
recording marks which are made on other media such as CDs
and MOs. The iD Photo disc is a magneto-optical disc which
records data uses the principle of applying magnetism and
temperature sumultaneously so that the recording medium
can maintain its magnetic polarity. Because of this, the data
cannnot be erased simply by placing the disc within a magnetic field, and moreover the recording method does not result in any changes to the physical nature of the disc. This
means that stable characteristics can be maintained for respected disc writing operations.
recording laser beam
disc movement direction
1-3. CAD ULTRA-HIGH MAGNETIC RESOLUTION
METHOD
In order to play back the extremely small marks which have
been recorded using laser pulse magnetic field modulation,
the iD Photo disc uses a ultra-high magnetic resolution
method which incorporates CAD (Center Aperture Detection).
Ultra-high magnetic resolution is a form of technology in which
a magnetic signal taken from only the center of the spot is
extracted for playback. The iD Photo disc has a multi-layered structure which comprises a polycarbonate substrate,
upon which is the playback layer with magnetic characteristics, a recording layer which stores the data, and finally a
heat dispersion layer which rapidly allows the spot which has
been heated by the laser beam to cool. When data is played
back from the disc, the laser beam which is generated by the
pickup passes through the polycarbonate substrate to reach
the playback layer, and focuses on a 1-µm spot. This playback layer functions as a screen to shield the recording layer
on which the data is recorded from the laser beam, so that
only a 0.6 µm diameter area at the center of the laser beam
which reaches the playback layer passes through it and is
projected onto the magnetic recording area of the recording
layer by means of an increase in temperature (window). The
recorded data can be picked up and read through this “window”, and the surrounding area is shielded. Moreover, in general the spacing between the tracks is narrow and so signal
interference from tracks which are next to the track being read
can occur. However, CAD-type ultra- high magnetic resolution also solves this interference problem. With CAD-type ultra-high magnetic resolution, only the magnetic signal which
passes throught the window at the center of the beam spot is
read, so that the playback reading area can be restricted to a
very narrow area not only in the tracking direction, but also in
the transverse direction. As a result, signal interference is
suppressed, and the spacing between the tracks can also be
made smaller.
playback laser beam
disc movement direction
MO pit
0.235µm
T
ultra-high magnetic
resolution window
value
temparature
distribution
recording layer
playback layer
Fig. 2
MO pit
0.235µm
recording spot
Fig. 1
– 2 –
Page 3
1-4. PRML SIGNAL PROCESSING
When the data on the iD Photo disc is read, the 0.235 µm
overlapping recording marks which are made during laser
pulse magnetic field modulation recording are read through
an 0.6 µm window by means of a CAD-type ultra-high magnetic resolution reading method. Because this window has a
diameter of 0.6 µm, at least two or three recording marks can
be viewed through this window at any given time. With the iDPhoto disc, PRML signal processing has been adopted as
the signal processing method for this readable area. PRML
signal processing compares the signal wave pattern which is
detected when recording marks with several different pattern
types pass by the window with the signal wave pattern which
is actually obtained by the pickup in order to recreate the
data which has actually been recorded. This technology makes
it possible to accurately reproduce the recording marks which
are smaller than the window being used to read them, and if
a signal pattern which is not valid is read, then it is handled
as an error. In this way, recording and playback of data at
high densities can be couple with high data reliability.
1-5. ZCLV METHOD OF ROTATION CONTROL
A ZCLV (Zoned Constant Linear Velocity) method of rotation
control has been adopted for the iD Photo disc. The ZCLV
method increases the disc rotation speed on a zone basis in
accordance with the progression toward the center of the disc
as the speed of rotation of the disc recording surface with
respect to the pickup becomes progressively slower. The iDPhoto disc is devided into 12 bands from the outside to the
inside of the disc surface, and the rotation speed within each
band is varied within a range of 1900-3100 rpm in order to
maintain the speed of rotation of the recording surface with
respect to the pickup to a level of about 5 meters per second.
1-6. EXTERNAL CLOCK SIGNAL
The iD Photo disc uses an external clock method to gener-
ate the clock pulses which are used to regulate the timing for
reading and writing of data. With conventional methods, the
clock pulse is generated based on changes in the data being
read. However, with this external clock method, an FCM (Fine
Clock Mark) signal is created beforehand and recorded onto
the disc for use as a reference signal in order to generate the
clock pulse. The timing of this FCM signal is monitored during reading of data in order to control the oscillation frequency
of the clock signal generator in accordance with the rotation
of the disc. The Fine Clock Mark is engraved accurately onto
the disc when the disc is manufactured, and it can then be
used as an accurate reference for stable reading and writing.
– 3 –
Page 4
2. OUTLINE OF iD FORMAT DISC DRIVE
CIRCUIT
1. OUTLINE OF DRIVE CIRCUIT BOARD
A drive part is composed of the block diagram of the Fig. 1,
and a drive circuit board is composed of MC1, MC2 and MC3.
During recording, it is the driver circuit board to magnetize
toward the magnetic head.
WD_P
WD_N
EJULK
EJLK
Large current
buffer
Magnetic
head
UP/DOWN
sensor
FET array
Amplitude
limitation circuit
Amplitude
limitation circuit
+ MH+
- MH-
MC1
2-1-1. EXPLANATION OF OPERATION
During recording, the data (WD_P and WD_N) from the MC3
circuit board is used to operate the large current buffer at IC801
in order to turn the FET array on and off. This is turn determines the direction of the magnetic field applied to the magnetic head. Also an upper limit is decided so that a magnetic
field level may not be bigger at the amplitude limitation circuit
by the data.
To the
magnetic
head
To the
magnetic
head
Fig. 2
The ascent and descent condition of the magnetic head is
being watched with the magnetic head up and down sensor.
2-2. SENSOR CIRCUIT BOARD (MC2)
WRPROT
CARTRG
PUINI
SPDLW
SPDLU
SPDLV
SPDLCOM
S8003
Disc write protect detection switch
S8004
Disc setting detection switch
D8003
Pick up location detection sensor
MC2
2-2-1. EXPLANATION OF OPERATION
Sensor circuit board (MC2) is the relay circuit board for the
disc write protection detection, disc setting detection switch,
the pickup location detection sensor and spindle motor control signal.
– 4 –
Fig. 1
To the
spindle
motor
Fig. 3
Page 5
2-3. OUTLINE EXPLANA TION FOR EACH BLOCK OF
DRIVE CIRCUIT BOARD (MC3)
2-3-1. SERVO AMPLIFIER
They are amplifier part for the focus servo and the tracking
servo.
Servo control is carried out by the DSP which is built into the
ASIC (IC402). This controls the focus actuator of the pickup in
order to carry out surface runout tracking control.
Minute
amplitude
inside
Land
Groove
C
B
Land
D
A
Groove
outside
Land
A, B, C, D
Focus
actuator
IC831
SSI33P3721
Gain-Amp
(x1.4)
2.5V
GND
FES Matrix
[Kf(A+C)-(B+D)]
AGC on/off
1. Focus offset adjustment
When the servo and laser are both off, the DSP of the ASIC
(IC402) samples the FE (focusing error) signal and obtains
average values which are used to control the offset cancel
registers of SSI33P3721 (IC402) in order to cancel the electrical offset. The signal level is set to 2.5 V DC.
2. Focus gain adjustment
The DSP of the ASIC (IC402) carries out focus searching to
measure the peak levels (+/–) for the S-shaped characteristics of the FE signal, and sets the ABCD gain (focus gain) for
the SSI (IC831) in accordance with these values. The above
The S-shaped curve amplitude of the focus error signal
(FE signal) is TYP 1.2Vp-p
Focus error singal
observation terminal
(TP810)
IC815
DRIVE ASIC
MACRO
FES
PWM 3/4
FCSF FCSR
4
IN2R
IN2F
H2F
H2R
OUT
OUT
14
DSP
5
12
The OA amplifiers and power supply
of the analog switches are all 5V.
AGC
WG
"0" REC
"1" PLAY
OFFSET
CANCEL
2.5V
Gain-Amp
Read (x1.22)
Write (x0.76)
IC835
(AD8532)
IC833
(ADG702)
FES
BD6603KVT
ABCD gain for the SSI is adjusted by the microprocessor in
order to maintain the VPP for the S-shaped characteristics of
the FE signal to approximately 1.18 V. The ABCD gain for the
SSI can be adjusted within the range of x1.2 to x4.3. During
recording (when the laser is at high power), the signal amplitude is reduced by about half before the FE signal is input to
the DSP of the ASIC (IC402).
3. Focus servo ON
The DSP of the ASIC (IC402) moves the focus actuator up
and down to control the FE signal so that its AC component is
“0”.
Fig. 4
2. TRACKING SERVO (MAIN PP AND PP SUBTRACTION METHOD)
Servo control is carried out by the DSP which is built into the
ASIC (IC402). This controls the tracking actuator and the thread
inside
Land
Groove
HF
C
B
Land
D
A
E
Groove
outside
G
Land
Tracking
actuator
Sread
actuator
A, B, C, D
E, F, G, H
Main Beam PP
[(A+D)-(B+C)]
IC814
(AD8054)
Sub Beam PP
α[(F+G)-(H+E)]
IC814
(AD8054)
IC814
(AD8054)
Gain-Amp
(±6dB)
IC837
(AD8051)
Offset
adjustment
SSI33P3721
2x[(A+D)-(B+C)]α[(F+G)-(H+E)]
actuator of the pickup in order to carry out rotation offset tracking control.
Tracking error signal
observation terminal
(TP811)
LPF
Gain-Amp
(x1~x2.2)
WG
"0" REC
"1" PLAY
TZC
OFFSET
CANCEL
2.5V
TZC
Buf
IC835
(AD8532)
IC834
(ADG702)
TES
IC815
BD6603KVT
TZC
(tracking
zero cross)
FES
PWM 5/6
TRKFTRKR
2
IN1R
IN1F
H1F
OUT
9
3
H1R
OUT
7
MACRO
PWM 1/2
SLDF
36
IN4F
H4F
OUT
40
DSP
SLDR
– 5 –
35
IN4R
H4R
OUT
42
Fig. 5
Page 6
1. Tracking offset adjustment
When the servo and laser are both off, the DSP of the ASIC
(IC402) samples the TE (tracking error) signal in order to control the offset cancel of SSI33P3721 (IC831) in order to cancel the electrical offset.
2. Tracking gain adjustment
When the focus servo is on, the DSP of the ASIC (IC402)
measures the amplitude of the TE signal and uses it to set
the CGA amp gain of the SSI (IC831).
2-3-2. FCM/ADDR AMPLIFIER
1. FCM AMPLIFIER
FCM is an abbreviation for Fine Clock Mark. This is used as
the external clock reference to generate the signal which becomes the syncronizing standard for the drive circuit board.
3. Balance adjustment of main PP and sub PP
This measures the DC offset when shifting to the inside and
to the outside occurs, with respect to the center of the TE
signal when the actuator is shifted 0.83 V to the outside, when
it is shifted 0.83 V to the inside and when it is at the standard
position.
4. Servo ON (disc rotation offset tracking)
The DSP of the ASIC (IC402) moves the tracking actuator to
the left or right to control the TE signal so that its AC component is “0”.
inside
Land
Groove
A, B, C, D
outside
C
D
B
A
Land
Groove
IC814
(AD8054)
TPP Matrix
[(A+B)-(C+D)]
The OA amplifiers, analog switch
and the power supply of the
comparator IC are all 5V.
Land
IC854
(AD8054)
Attenuator
gain fixing
play: x 6.356
rec: x 3.33
FCLKGC
IC855
(ADG701)
Amp
IC857
(AD8534)
LC
Filter
WG
"0" REC
"1" PLAY
PEAK HOLD
circuit
BOTTOM
HOLD
circuit
VCA variable
range (± 4dB)
Ctrl
IC853
(BA7655)
FCLKAMPBTM
LC
Filter
1. Fine clock mark (FCM)
A computation ((A+B)–(C+D)) is carried out on the signals
from the photosensor, after which they pass through the VCA
circuit (IC853) and LPF circuit, and then the FCM signal amplitudes pass through the peak hold and bottom hold circuits
and are input to the DSP of the ASIC (IC402), where A/D
conversion is carried out. At the DSP of the ASIC (IC402), the
D/A value of the signal (FCLKGC) which has had the control
voltage adjusted by the VCA (IC853) is changed so that the
FCM level is set to the level which is necessary for the
FCLKNP and FCLKPP signals to be generated. Furthermore,
DSP of the ASIC (IC402) and the above circuits set the slice
level to 50 % - 70 % of the +/– side FCM marks so that the
comparator (IC852) (FCLKPP and FCLKNP) singals do not
delay the transfer of the address signals. The above circuits
adjust the signals so that the FCM amplitude is at about the
same level when at the default recording and playback power.
Furthermore, a ratio of 60 % or more between the + side and
the – side of the FCM signal is necessary when LAND is on
and when GROOVE is on. The DSP controls the control potential of the VCA (IC853) so that the Vpp of the FCM signal
is about TYP 1.7 Vp-p. Furthermore, the signal interval for
the FCM signals is 532 x 50 ns = 26.6 µs.
FCLKAMPL
Gain-Amp
x2
IC854
(AD8054)
upper slice level
lower slice level
ASIC
D/A
A/D
D/A
A/D
DSP process
FCMK signal
obwervation
LAND
FCM
FCLKPP
FCLKNP
FCLKSLS
FCLKSLSBTM
IC857
(AD8534)
VC25
termanal
(TP808)
IC851
(AD8534)
primary
function
circuit
primary
function
circuit
comparator
input allowable
value (0.8~3.6V)
LAND
FCM
2.5V
GROOVE
Comparator
FCM-PP
IC852
(LT1721)
Comparator
FCM-NP
IC852
(LT1721)
Comparator
FCM-Z
IC852
(LT1721)
26.6[µs]
AS-MO ASIC
160
FCLKPP
161
FCLKNP
162
FCLKZ
2.5V
2.5V
Fig. 6
2. FCLKPP/FCLKNP/FCLKZ
These are generated from the FCM signal by the comparator
(IC852) according to the timing shown in Fig. 7.
1. When LAND is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKPP
signal has been detected and the FCLKZ signal is rising.
2. When GROOVE is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKNP
signal has been detected and the FCLKZ singal is falling.
LAND
FCLKPP
FCLKZ
FCLKNP
GROOVE
Fig. 7
– 6 –
Page 7
3. The principle of rec/play clock generated by the PLL
The clock is reproduced by the PLL with respect to the signal
which has been detected to be the FCM signal by the circuit
(primary function circuit) which generates the slice level from
the FCM signal. The frequency of the reproduced clock is 20
MHz.
4. LC filter
LC filters are located before and after the VCA (IC853). During recording, there is the possibility that the WCLK (20 MHz)
or other high-frequency interference can become mixed in with
2. ADDRESS DETECTION/AMPLIFIER
Mainly the address detection of the disc and signal process in
order to detect are done.
the FCM signal or the address signal. These LC filters remove
almost all of the signal components which are at 20 MHz or
above, leaving just the base frequencies (2-3 MHz) for the
FCM and address signals.
5. Peak hold for FCM signal and bottom hold circuit
These circuits use the amplitude modulation of the FCM signal to hold the peak level and the bottom level of the FCM
signal at the capacity which is connected to the transistor
emitter.
outside
Land
Groove
A, B, C, D
inside
C
D
B
A
Land
Groove
IC814
(AD8054)
Main Matrix
[(A+D)-(B+C)]
Land
ADRSGC
The OA amplifiers, analog switch
and the power supply of the comparator
IC are all 5V.
IC856
IC854
(AD8054)
Attenuator
Gain fixing
Read: x 6.81
Write: x 3.78
(ADG701)
IC857
(AD8534)
Amp
LC
Filter
WG
"0" REC
"1" PLAY
VCA
variable range
(± 4dB(min))
1. Address detection
The main PP signal ((A+D)–(B+D)) at the tracking servo amplifier shown in Fig. 5 passes through the VCA circuit (IC853)
and the LPF circuit, after which the address peak signal is
input to the DSP of the ASIC (IC402) and A/D conversion is
then carried out. As a result, the maximum amplitude of the
address signal is detected and the control potential of the VCA
AS-MO ASIC
189
173
163
A14
A02
ADRSPLS
Filter
Ctrl
IC853
(BA7655)
FCLKWIN
Gain-Amp
LC
IC859
(ADG702)
IC854
(AD8054)
PEAK HOLD
CIRCUIT
Comparator
VC25
comparator
input allowable value
(0.67~3.36V)
ADRSAMPL
ADRSGC
ADRSPLS
IC852
(LT1721)
(IC853) is changed so that the amplitude of the address signal can be changed to the appropriate level. Furthermore, it is
input to the comparator (IC852) to generate the address signal. This address signal is taken up by the DC macro of the
ASIC (IC402) to be used as the frame address and track address during recording and playback.
Fig. 8
2-3-3. RF AMPLIFIER
RF is the data signal that it is to be read by a pickup sensor (I, J).
Gain-Amplifier
x 8.17
I
J
IC838
(AD8062)
I/J is bias by 2.5 V (FREF).
SSI33P3721
Cutoff
AGC
Programmable
AGC on/off
MOAGCHLD
AGCOFFH
Boost
Equalizer
Filter
IC836
(ADG701)
During AGC OFF
Gain is decided.
– 7 –
+5VA
MO-RF
IC832
(AD8051)
2.0V
1.0V
AGCOFFH
TP801
(MO observation)
AS-MO ASIC
136
RF
137
REFTOP
138
REFBTM
221
P06
Fig. 9
Page 8
The signals from the sensors (I/J) are pre-amplified by the
gain amplifier, and then pass through the AGC/equalizer of
the SSI (IC831), and are then input to the RF signal terminal
of the ASIC (IC402). The AGC control signal (AGCOFFH) from
the ASIC (IC402) is modulated to control the on/off status of
the AGC. When the AGC is on, the wave pattern monitored at
TP801 is adjusted to a constant amplitude.
2-3-4. SERVO DRIVER
The driver circuit of spindle motor, sread motor and each actuators are accumulated inside BD6603KVT (IC815). The
spindle motor is used three aspect sensorless motor (DC
motor).
2-3-5. LASER POWER CONTROL
TA6015F (optical disc power control (LPC): IC841) and
TA6012F (optical disc high speed APC) are used in the pairs.
An APC IC appears on the pickup. LPC (IC841) control makes
it possible to set characteristics such as playback power, recording peak power, duty, laser on/off setting and low power
consumption standby mode using the register settings of the
LPC (IC841).
3. BLOCK DIAGRAM OF PLAY/REC AND SIGNAL PROCESS etc.
APC IC (on the pickup)
The APC IC functions to maintain the current detected by the
photosensor attached to the laser to a constant level. This
has the effect of canceling any fluctuations in characteristics
resulting from the semiconductor laser temparature, and any
variances in production lots, so that the laser power can be
maintained at a stable level. The ON/OFF laser high-frequency
currents, power save and laser are output open corrector from
LPC IC, and input to APC IC.
Superimposing high-frequency currents
When a high-output semiconductor laser is used, interference
can be generated from the light which is reflected back from
the disc. Because of this, high-frequency currents of 300-600
MHz are superimposed on the laser drive currnet to reduce
interference.
2-3-6. SDRAM
This is used as a WORK for ECC encoding and decoding, as
a buffer for seamless recording and playback, and as a drive
cache.
Magnetic field strength
MH
Driver
SSI
IC
Gain
G.C
Gain
G.C
DRIVE ASIC
A/D
2T signal
PLL
Slice Level
ADRS
Dec.
SH
APC
IC
LPC
IC
EQ, fc, Boost
MO
FCM
Adrs
WCLK
Duty Pr Pw
Temparature
sensor
1. Playback clock by PLL
The playback clock (20 MHz) which is generated from the
FCLKPP/FCLKNP signals (see Fig. 7) obtained from the FCM
is played back. The spindle motor operation is controlled by
CL V (constant linear velocity) to provide a constant FCM cycle
(26.6 µs). Accodingly, the rotation becomes faster as tracking
moves toward the center of the disc.
3. IC902, IC904, IC908 (H Driver) and IC907 (V Driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC902, IC904 and IC908 are inverter IC which drives the horizontal CCDs (H1 and H2). In addition the XV1-XV3 signals
which are output from IC102 are the vertical transfer clocks,
and the XSG1 and XSG signal which is output from IC102 is
superimposed onto XV2A and XV2B at IC907 in order to generate a ternary pulse. In addition, the XSUB signal which is
output from IC102 is used as the sweep pulse for the electronic shutter, and the RG signal which is output from IC102
is the reset gate clock.
14
CC
1A
1Y
2A
2Y
3A
1
2
3
4
5
V
13
6A
12
6Y
11
5A
10
5Y
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(30) of IC905. There are S/H blocks inside IC905 generated
from the XSHP and XSHD pulses, and it is here that CDS
(correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102 of the CA2 circuit
board. The gain of the AGC amplifier is controlled by serial
data which is output from IC102 of the CA2 circuit board.
PBLK
CCDIN
CLPDM
AUX1IN
AUX2IN
AVDD
CDS
CLP
CLP
4 dB
MUX
AVSS
2~36 dB
2:1
VGA
MUX
10
BUF
2:1
CONTROL
REGISTERS
DIGITAL
INTERFACE
Offset
DAC
8
CLPOB
AD9840
CLP
10-BIT
ADC
BANDGAP
REFERENCE
INTERNAL
BIAS
INTERNAL
TIMING
DRVDD
DRVSS
10
DOUT
VRT
VRB
CML
DVDD
DVSS
4A
3Y
GND
6
7
9
4Y
8
Fig. 1-3. IC902, IC904 and IC908 Block Diagram
DD
V
1
Input
Buffer
XSHT
2
XV3
3
XSG3B
4
XSG3A
5
XV1
6
XSG1B
7
SDATA
SCK
SL
SEN
Fig. 1-5. IC905 Block Diagram
SHT
20
V3B
19
V
L
18
V3A
17
V1B
16
V
H
15
V1A
14
DATA
SHDSHP
CLK
8
9
10
XSG1A
XV4
XV2
Fig. 1-4. IC907 Block Diagram
– 10 –
V4
V2
GND
13
12
11
Page 11
5. Transfer of Electric Charge by the Horizontal CCD
The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-6.
RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the timing
in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the timing in (3),
and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7.
(1)
H1 H2H1 H2 H1 HOGRG
CCD OUT
Floating diffusion
(2)
H1 H2H1 H2 H1 HOGRG
PD
PD
CCD OUT
H1
H2
RG
15.5V
(1) (2) (3)
3.5V
0V
3.5V
0V
12V
(3)
H1 H2H1 H2 H1 HOGRG
Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage
Reset gate pulse
Direction of transfer
H Register
Electric
charge
Floating diffusion gate is
floated at a high impedance.
C is charged
equivalently
12V Pre-charge drain bias(PD)
Voltage output
Fig. 1-7. Theory of Signal Extraction Operation
CCD OUT
CCD OUT
RG pulse peak signal
Signal voltage
6-2. Iris drive
When in the aperture enable (AE SW) state, the target aperture value signal (IRIS PWM) which is output by the ASIC and
the aperture value signal (HALL OUT +/–) which is output by
the lens are compared so that feedback control can be carried
out.
6-3. Focus drive
When the drive signals (FRSTB, FCW, FOEB and FCLK) which
are output from the ASIC, the focus stepping motor is sinewave driven by the micro-step motor driver (IC953). Detection
of the standard focusing positions is carried out by means of
the photointerruptor (FOCUS PI) inside the lens block.
6-4. Zoom drive
When the drive signals (ZRSTB, ZCW, ZOEB and ZCLK) which
are output from the ASIC, the zoom stepping motor is sinewave driven by the micro-step motor driver (IC954). Detection
of the zoom positions is carried out by means of photoreflector
(ZOOM PI) inside the lens block.
Black level
6. Lens drive block
6-1. Shutter drive
The shutter drive signal (SHUTTER) which is output by the
ASIC and the aperture enable signal (AE SW) cause a positive and negative voltage are applied to the aperture drive coil
to open and close the lens aperture.
6-5. ND filter drive
When the drive signals (ND ON, ND OFF) which are output
from the ASIC, ND filter opens and closes.
This circuit uses the function of a 64-Mbit SDRAMs to convert the non-interlaced signal which is output from the CCD
into an interlaced signal for the video monitor.
1-2. Camera signal processor
This comprises circuits such as the digial clamp circuit, white
balance circuit, γcircuit, color signal generation circuit, matrix circuit and horizontal aperture circuit.
1. Digital clamp circuit
The optical black section of the CCD extracts 16-pixel averaged values from the subsequent data to make the black level
of the CCD output data uniform for each line. The 16-pixel
averaged value for each line is taken as the sum of the value
for the previous line multiplied by the coefficient k and the
value for the current line multiplied by the coefficient 1-k.
2. White balance circuit
This circuit controls the white balance by using the A WB judgement value computed by the CPU to control the gain for each
R, G and B pixel based on the CCD data which has been
read.
3. γ circuit
This circuit performs (gamma) correction in order to maintain
a linear relat ionship b etween the light i nput to the camer a
and the light output from the picture screen.
4. Color generation circuit
This circuit converts the CCD da ta int o RGB signal s.
5. Matrix circuit
This circuit generates the Y s ignals , R-Y signals and B-Y signals from the RGB signals.
6. Horizontal aperture circuit
This circuit is used generate the aperture signal.
1-3. SDRAM controller
This circuit outputs address, RAS, CAS and AS data for controlling the SDRAM. It also refr eshes the S DRA M.
1-4. PIO
The expansion parallel port can be used for functions such
as stroboscope control and LCD driver control.
1-5. SIO (Serial control)
This is the interface for the 4-bit mic roprocessor.
1-6. USB control
This is comunicated PC with 12 Mbps.
1-7. TG, SG block
This is the timing generation circuit which generates the clocks
(vertical transfer clock and electronic shutter clock) which drive
the CCD.
1-8. 8-bit D/A circuit (Audio)
This circuit converts the audio signals (analog signals) from
the microphone to 8-bit digital signals.
1-9. 8-bit A/D circuit (Audio)
The audio signals which were converted to digial form by the
8-bit A/D circuit are temporarily to a sound buffer and then
recorded in the SSFDC card. During playback, the 8-bit D/A
circuit converts these signals into analog audio signals.
1-10. Sound buffer
Audio memory
1-11. LCD driver
The Y/C signals which are input to the LCD driver are converted to RGB signals, and the timing signal which is necessary for LCD monitor display and the RGB signals are then
supplied to the LCD monitor.
1-12. LCD monitor
This is the image display device which displays the image
signals supplied from the LCD driver.
1-13. UART
This circuit is used for transmitting serial data to a PC. The
interface is RS-232C-compatible.
1-14. MJPEG compression
Still and continuous frame data is converted to JPEG format,
and movie images are compressed and expanded in MJPEG
format.
2. Outline of Operation
When the shutter opens, the reset signals, TEST0, TEST1
and the serial signals (“take a picture” commands) from the
8-bit microprocessor are input and record operation starts.
When the TG drives the CCD, picture data passes through
the A/D and is then input to the ASIC as 10-bit data. This data
then passes through the DCLP, AWB, shutter and γ circuit,
after which it is input to the SDRAM. The AWB, shutter, γ,
and AGC value are computed from this data, and in case of
1-4 times exposures are made to obtain the optimum picture.
The data which has already been stored in the SDRAM is
read by the CPU and color generation is carried out. Each
pixel is interpolated from the surrounding data as being either R, G or B primary color data to produce R, G and B data.
At this time, correction of the lens distortion which is a characteristic of wide-angle lenses is carried out. Aperture correction is carried out, and in case of still picture the data is
then compressed by the JPEG method and in case of picture
it is compressed by MJPEG method and is transfered to MC3
block. And then it is written to iD photo disc. When the data is
to be output to an external device, it is read JPEG picture
data from the iD photo disc and output to PC via the USB or
IEEE1394.
– 12 –
Page 13
3. LCD Block
During EE, gamma conversion is carried out for the 10-bit
RGB data which is input from the A/D conversion block of the
CCD to the ASIC in order that the γrevised can be displayed
on the video. The YUV of 640 x 480 is then transferred to the
SVRAM.
The data which has accumulated in the SDRAM is after D/A
conversion is carried out by SDRAM control circuit inside the
ASIC, makes Y/C signal, the data is sent to the LCD panel
and displayed.
If the shutter button is pressed in this condition, the 10-bit
data which is output from the A/D conversion block of the
CCD is sent to the SDRAM (DMA transfer), and is displayed
on the LCD as a freeze-frame image.
During playback, the JPEG image data which has accumulated in the iD photo disc is converted to RGB signals. In the
same way as for EE, the data is then sent to the SDRAM,
after which D/A conversion is carried out inside the ASIC,
and then the data is sent to the LCD panel and displayed.
The LCD driver is converted Y/C signals to RGB signals from
ASIC, and these RGB signals and the control signal which is
output by the LCD driver are used to drive the LCD panel.
The RGB signals are 1H transposed so that no DC component is present in the LCD element, and the two horizontal
shift register clocks drive the horizontal shift registers inside
the LCD panel so that the 1H transposed RGB signals are
applied to the LCD panel.
Because the LCD closes more as the difference in potential
between the VCOM (common polar voltage: fixed at DC) and
the R, G and B signals becomes greater, the display becomes
darker; if the difference in potential is smaller, the element
opens and the LCD become brighter. In addition, the brightness and contrast settings for the LCD can be varied by means
of the serial data from the ASIC.
– 13 –
Page 14
3-3. PW1 POWER CIRCUIT DESCRIPTION
1. Outline
This is the PW1 power circuit for camera block. The oscillation frequency is 400 kHz, and it has no voltage adjustment.
1-1. IC501 and IC511
This is necessary for controlling the power supply for a PWMtype switching regulator, and IC501 is provided with four builtin channels step-down circuits. IC511 is provided with transformer control and step-up circuit for backlight. The oscillation frequency is approx. 200 kHz.
1-2. Short-circuit protection circuit
If output is short-circuited for the length of time (approx. 120
ms) determined by the condenser which are connected to
Pin (17) of IC501 and Pin (17) of IC511, all output is turned
off. The control signal (P ON) are recontrolled or reset on the
power to restore output.
1-3. Head 4 V Power Output
IC501 CH1 is output. It is used for head power supply of disc.
Feedback for output voltage is provided to Pin (29) of IC501
so that PWM control can be carried out.
1-4. Digital 3.3 V System Power Output
IC501 CH2 is output. It is used for digital circuit power supply
of camera. Feedback for output voltage is provided to Pin
(26) of IC501 so that PWM control can be carried out.
1-7. CCD Power Output
IC511 CH1 is output. It is output CCD power supply (5.1 V
(A), 15.0 V (A), –8 V (A)) and digital 5.1 V (D) by transformer
T5101. Feedback for 5.1 V (D) is provided to Pin (29) of IC51 1
so that PWM control can be carried out.
1-8. LCD Panel Power Output
IC511 CH2 is output. It is output LCD panel power supply
(5.1 V (L), 12.4 V (L), 15 V (L)) by transformer T5102. Feedback for 5.1 V (L) is provided to Pin (26) of IC511 so that
PWM control can be carried out.
1-9. EVF Back Light Power Output
IC511 CH3 is output. It is output EVF backlight power supply.
The backlight is controlled constant current 15 mA. Output
voltage is approx. 11-14 V by LED VF is scattered.
1-10. LCD Back Light Power Output
IC511 CH4 is output. It is output EVF backlight power supply.
The backlight is controlled constant current 8.3 mA. Output
voltage is approx. 20-24 V by LED VF is scattered.
1-5. Digital 2.4 V System Power Output
IC501 CH3 is output. It is used for core power supply of camera ASIC. Feedback for output voltage is provided to Pin (11)
of IC501 so that PWM control can be carried out.
1-6. Motor 5 V Power Output
IC501 CH4 is output. It is used for lens circuit power supply.
Feedback for output voltage is provided to Pin (7) of IC501
so that PWM control can be carried out.
– 14 –
Page 15
3-4. PW2 POWER CIRCUIT DESCRIPTION
1. Outline
This is the PW2 power circuit for iD disc drive. The oscillation
frequency is 400 kHz, and it has no voltage adjustment.
1-1. IC521
This is necessary for controlling the power supply for a PWMtype switching regulator, and is provided with four built-in channels step-down circuits. The oscillation frequency is approx.
400 kHz.
1-2. Short-circuit protection circuit
If output is short-circuited for the length of time (approx. 120
ms) determined by the condenser which is connected to Pin
(17) of IC501, all output is turned off. The control signal (P
ON) are recontrolled or reset on the power to restore output.
1-3. 4.9 V System Power Output
CH1 is output. It is divided 4.9 V (D) and 4.9 V (A). 4.9 V (A)
is mainly used for laser power supply. Feedback for output
voltage is provided to Pin (29) of IC521 so that PWM control
can be carried out.
1-4. Analog 3.1 V System Power Output
CH2 is output. It is used for disc servo etc. of analog circuit
power supply. Feedback for output voltage is provided to Pin
(26) of IC521 so that PWM control can be carried out.
1-5. Spindle 3.35 V System Power Output
CH3 is output. It is used for spindle motor power supply . Feedback for output voltage is provided to Pin (11) of IC521 so
that PWM control can be carried out.
1-6. Digital 3.15 V System Power Output
CH4 is output. It is used for digital circuit power supply of
disc. Feedback for output voltage is provided to Pin (7) of
IC521 so that PWM control can be carried out.
– 15 –
Page 16
3-5. ST1 STROBE CIRCUIT DESCRIPTION
1. Charging Circuit
When UNREG power is supplied to the charge circuit and the
CHG signal becomes High (3.3 V), the charging circuit starts
operating and the main electorolytic capacitor is charged with
high-voltage direct current.
However, when the CHG signal is Low (0 V), the charging
circuit does not operate.
1-1. Power switch
When the CHG signal switches to Hi, Q5406 turns ON and
the charging circuit starts operating.
1-2. Power supply filter
L5401, C5401 and C5402 constitute the power supply filter.
They smooth out ripples in the current which accompany the
switching of the oscillation transformer.
1-3. Oscillation circuit
This circuit generates an AC voltage (pulse) in order to increase the UNREG power supply voltage when drops in current occur. This circuit generates a drive pulse with a frequency
of approximately 50-100 kHz. Because self-excited light omission is used, the oscillation frequency changes according to
the drive conditions.
2. Light Emission Circuit
When RDY and TRIG signals are input from the ASIC expansion port, the stroboscope emits light.
2-1. Emission control circuit
When the RDY signal is input to the emission control circuit,
Q5409 switches on and preparation is made to let current
flow to the light emitting element. Moreover, when a STOP
signal is input, the stroboscope stops emitting light.
2-2. Trigger circuit
When a TRIG signal is input to the trigger circuit, D5405
switches on, a high-voltage pulse of several kilovolts is generated inside the trigger circuit, and this pulse is then applied
to the light emitting part.
2-3. Light emitting element
When the high-voltage pulse form the trigger circuit is applied to the light emitting part, currnet flows to the light emitting element and light is emitted.
Beware of electric shocks.
1-4. Oscillation transformer
The low-voltage alternating current which is generated by the
oscillation control circuit is converted to a high-voltage alternating current by the oscillation transformer.
1-5. Rectifier circuit
The high-voltage alternating current which is generated at
the secondary side of T5401 is rectified to produce a highvoltage direct current and is accumulated at electrolytic capacitor C5050 on the PW1 circuit board.
1-6. Voltage monitoring circuit
This circuit is used to maintain the voltage accumulated at
C5050 at a constance level.
After the charging voltage is divided and converted to a lower
voltage by R5417 and R5419, it is output to the SY1 circuit
board as the monitoring voltage VMONIT. When this VMONIT
voltage reaches a specified level at the SY1 circuit board, the
CHG signal is switched to Low and charging is interrupted.
– 16 –
Page 17
3-6. SY1 CIRCUIT DESCRIPTION
1. Configuration and Functions
For the overall configuration of the SY1 circuit board, refer to the block diagram. The configuration of the SY1 circuit board
centers around a 8-bit microprocessor (IC301).
The 8-bit microprocessor handles the following functions.
1. Operation key input, 2. Mode LCD display, 3. Clock control, 4. Power ON/OFF, 5. Storobe charge control
Pin
1
2~3
4~7
8AVDD
9
10
11
12
13~19
20
21
22
23~25
26
27
28~30
31
32~51
52~56
57~59
60DC IN
61~63NOT USED
64WAKE UP
65NOT USED--
66MECHA SW
67NOT USED--
68GND-GND
69STROBE SW
70PA ON
71P ON
72MIC JACK
73
74
75
76
77
78
79
80
81
82
83
Signal
CHG VOL
GND
SCAN IN 0~3
AVREF
TARRY LED
GND
VSS
NOT USED
AVREF ON
GND
CHG ON
COM1~COM3
NOT USED
BIAS
VLC0~VLC2
VSS
S1~S20
NOT USED
SCAN IN 4~6
GND
AV JACK
SI
SO
SCK
IC
XOUT
XIN
VDD
XCIN
XCOUT
I/O
I
I
-
I
O
-
-
-
O
O
O
-
-
-
-
O
I
I
ISignal for detection of access condition to discH : Rotation
I
I
ODC/DC converter (analog) ON/OFF signalH : ON
ODC/DC converter ON/OFF signalH : ON
I
-
I
I
O
O
-
O
I
-
I
O
Outline
Strobe charge voltage input (analog input)
GND
Key matrix input
A/D converter analog power terminal
A/D converter standard voltage input terminal
Remote control LEDL : LED light
GND
GND
A/D standard voltage ON/OFF signalL : ON
GND
Flash charge ON/OFF signalH : ON
Mode LCD common signal output
LCD motor voltage supply terminal
LCD motor voltage terminal
GND
Mode LCD segment signal output
-
Key matrix input
DC adaptor insertion detectionL : ON
-
Detection of disc insertion & cover open/close L : Disc insertion and cover close
GND
Video output cable connection detection signalH : Connection
Serial communication data input (←ASIC)
Serial communication data output (→ASIC)
Serial communication clock output (→ASIC)
Connect to VSS
Main clock oscillation terminal (4 MHz)
Main clock oscillation terminal
Power supply terminal
Sub clock oscillation terminal (32.768 kHz)
Sub clock oscillation terminal
See next page →
– 17 –
Page 18
84
85
86
87
88
89
90
91~94
95
96
97
98
99
100
RESET
BAT OFF
IR IN
SREQ
USB
JOG RIJog right rotation
JOG L
SCAN OUT 0~3
LCD ON
ASIC TEST
ASIC RESET
ASIC TEST 1
AVSS
BATTERY
I
I
I
I
I
I
O
O
O
O
O
-
I
Table 4-1. 8-bit Microprocessor Port Specification
Reset input
Battery OFF detection signalL : OFF
Remote control signal input terminal
Serial communication request signalL : Request
USB connector connection detection signalL : Connection
Jog left rotation
Key matrix output
LCD monitor power ON/OFF signalH : ON
ASIC reset control signal
ASIC reset signalL : Reset output
ASIC test signal
A/D converter GND power terminal
Battery voltage input (analog input)
2. Internal Communication Bus
The SY1 circuit board carries out overall control of camera operation by detecting the input from the keyboard and the condition
of the camera circuits. The 8-bit microprocessor reads the signals from each sensor element as input data and outputs this data
to the camera circuits (ASIC) or to the LCD display device as operation mode setting data. Fig. 4-1 shows the internal communication between the 8-bit microprocessor and ASIC RISC CPU circuits.
ASIC TEST 1
ASIC TEST 0
S. REQ
8-bit
microprocessor
Fig. 4-1 Internal Bus Communication System
ASIC SO
ASIC SI
ASIC SCK
RESET
3. Key Operaiton
For details of the key operation, refer to the instruction manual.
SCAN
SCAN
OUT
IN
0
0
LEFT
1
DOWN
23
UP
RIGHT
ASIC RISC CPU
1 CHIP CPU
4
5
f2f1
6
Auto/Manual
1
2
3
1st
STILL IMAGE
SET
2nd
SEQUENTIAL
SHOT
MODE
EXE CUTE
SHOOTING
VIDEO CLIPS
-
Table 4-2. Key Matrix table
AF
OPT
-
– 18 –
AE
COMMUNICA-
TION
ZOOM TELE
AWB
POWER
ZOOM WIDE
CAMERA
-
-
Page 19
4. Power Supply Control
The 8-bit microprocessor controls the power supply for the overall system.
The following is a description of how the power supply is turned on and off. When the battery is attached, a regulated 3.2 V
voltage is normally input to the 8-bit microprocessor (IC301) by IC302, so that clock counting and key scanning is carried out
even when the power switch is turned off, so that the camera can start up again. When the battery is removed, the 8-bit microprocessor operates in sleep mode using the backup battery . At this time, the 8-bit microprocessor only carries out clock counting,
and waits in standby for the battery to be attached again. When a switch is operated, the 4-bit microprocessor supplies power to
the system as required.
The 8-bit microprocessor first sets both the P ON signal at pin (71) and the PA ON signal at pin (70) to high, and then turns on the
DC/DC converter. After this, Low pulse are output from pins (96), (98) and (97) in order so that the ASIC RISC CPU is set to the
active condition. If the LCD monitor is on, the LCD ON signal at pin (95) set to high, and the DC/DC converter for the LCD monitor
is turned on. Once RISC CPU processing is completed, the ASIC RISC CPU return to the reset condition, all DC/DC converters
are turned off and the power supply to the whole system is halted.
Power
ON
Supply voltage
Power OFF
No disc
Play back
Power switch ON-Auto power down
Shutter switch ON
Resolution, Flash,
Self timer switch ON
LCD finder
Table 4-3. Camera Mode (Battery Operation)
Supply voltage
ASIC, RISC
CPU,
CCD
memory
3.3 V, 2.5 V
3.3V(D) 5V(A)
+15 V -8 V
OFFOFF
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON→ OFF
OFF
ONON4MHz
ASIC, RISC
CPU,
CCD
memory
3.3 V
5 V (A)
+15 V -8 V
4bit
CPU
3.2 V
(ALWAYS)
MODE
LCD
3.2 V
(ALWAYS)
LCD (EVF)
MONITOR
5V (L)
+12V etc.
32KHzOFF
4MHzONOFF
4MHzONON/OFF
4MHzONOFF
4MHzONOFF
4MHzONOFF
4bit
CPU
3.2 V
(ALWAYS)
ON
MODE
LCD
3.2 V
(ALWAYS)
ON/OFF
LCD (EVF)
MONITOR
+12V etc.
OFF
5 V (L)
DRIVE
4.9V(D),3.15V(P),
4.9V(A),3.15V(D),
4V(H), 3.1V(A)
OFF
OFF
ON
OFF
ON
OFF
ON
DRIVE
↑
Power OFF
No disc
Power switch ON-Auto power down
Take a picture
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON→ OFF
32 KHzOFFOFF
4 MHzON
4 MHzONOFF
4 MHzONOFF
Power
Erase image
ON
OFF
4 MHzONOFF
ON
Download image
Continuous image
Message from host
ON
ON
ON
OFF
ON
ON
4 MHzONOFF
4 MHzONOFF
4 MHzONOFF
Note) P. SAVE = Power save mode, 4 MHz = Main clock operation, 32 kHz = Sub clock operation
Table 4-4. Host Mode (Battery Operation)
– 19 –
OFF
OFFOFF
OFF
ON
ON
ON
ON
ON
Page 20
4. DISASSEMBLY
4-1. REMOVING THE PROTECTIVE SPACER AND NOTES
If the camera is dropped or subjected to other strong shocks, it may damage the mechanical pickup function. To prevent the
possibility of this happening, attach the protective spacer to the camera when transporting the camera.
1. Push the eject lever in the direction
of the arrow to open the
disk holder.
4-2. REMOVAL OF CABINET ASSEMBLY
1. Three screws 1.7 x 5
2. Screws 1.7 x 4
3. Cabinet top
1
21
15
3
6
17
20
19
18
39
4. FPC
5. Two screws 1.7 x 3.5
6. Four screws 1.7 x 3
7. Cabinet lens L
8. Cabinet VF
9. Six screws 1.7 x 4
10. Screw 1.7 x 2.5
11. Cover bottom
12. Cabinet back
13. Screw 1.7 x 3.5
14. Screw 1.7 x 2.5
15. Screw 1.7 x 5
16. Cabinet front
17. Cabinet lens R
18. Connector
19. FPC
20. Screw 1.7 x 2.5
21. SY2 board
22. Screw 1.7 x 3.5
14
23. Flexible PWB unit
24. Two FPCs
25. Connector
26. Cabinet jog B
27. Two screws 1.7 x 2.5
28. Button AWB
29. Five screws 1.7 x 4
30. SY4 board
31. Two screws 1.7 x 4
32. Holder zoom A
33. Push the button.
34. Three screws 1.7 x 2.5
35. Screw 1.7 x 5
36. Holder flash B
37. Two screws 1.7 x 4
16
36
44
37
45
35
43
13
42
34
1
2
41
2. Gently pull out the
protective spacer.
38. Screw 1.7 x 6
39. Cabinet bottom
40. Open the cover
battery.
8
4
41. Screw 1.7 x 2.5
42. Screw 1.7 x 5
43. Screw 1.7 x 5
5
44. Connector
45. Ring MF
46. Cabinet side L
7
1
12
9
6
A
33
9
11
25
30
C
26
D
B
24
10
29
A
B
C
D
23
27
28
32
31
22
46
38
40
9
– 20 –
Page 21
4-3. REMOVAL OF LCD, SY1 BOARD, SY3 BOARD AND ST1 BOARD
E
G
G
F
F
E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
16
1. Two screws 1.7 x 5
2. Connector
3. FPC
4. Holder LCD VF
5. Two screws 1.7 x 3.5
6. Unit control mode
7. Holder mode
8. Two screws 1.4 x 1.9
9. Connector
10. Holder speaker
11. Screw 1.7 x 3.5
12. FPC
13. Connector
14. Screw 1.7 x 2.5
15. Holder dec LCD
16. FPC
17. Unit flexible PWB
18. FPC
24
25
19. Connector
20. LCD
21. FPC
22. Flexible flat cable
23. SY1 board
26
27
31
30
26
28
24
29
32
H
33
34
35
H
33
37
36
24. Two screws 1.7 x 2.5
25. Holder brind
26. Two screws 1.7 x 3.5
27. Holder SY
28. Screw 1.7 x 2
29. Holder heat sink
30. Screw 1.7 x 3.5
31. SY3 board
32. Screw 1.7 x 3.5
33. Two connectors
34. ST1 board
35. Two screws 1.7 x 3.5
36. Screw 1.7 x 4.0
37. Holder lens MO
– 21 –
Page 22
4-4. REMOVAL OF CA3 BOARD, CA2 BOARD AND MECHANISM
1. Two screws 1.7 X 3.5
2. Connector
3. CA3 board
4. Two screws 1.7 x 3.5
5. Two screws 1.7 x 3.5
6. Two screws 1.7 x 4
7. FPC
8. Three connectors
9. CA2 board
10. Five screws 1.4 x 2.5
11. Cover mecha (protective housings)
12. Two screws 1.7 x 3.5
11
10
13. Holder lens back
14. Two screws 1.7 x 3.5
15. Two screws 1.7 x 2
16. Holder lens mecha
17. Heat sink A
10
12
13
14
15
17
16
4
5
9
5
8
6
7
2
1
1
4
6
3
– 22 –
Page 23
4-5. REMOVAL OF PW1 BOARD, PW2 BOARD, CA1 BOARD, SY5 BOARD AND BOARD LOCATION
10
6
18
8
9
5
7
4
11
15
1
3
12
2
14
13
1. Screw 1.7 x 3.5
2. Screw 1.7 x 4
3. PW1 board
4. Screw 1.7 x 3.5
5. PW2 board
6. Two screws 2.0 x 3.5
7. Holder lens top
8. Screw 1.7 x 2.5
9. Unit flexible PWB
10. Two screws 2.0 x 3.5
11. Holder lens front
12. Shield tape
13. Screw 2 x 2.5
14. Two screws 2 x 6
15. CA1 board
16. Screw 2.0 x 3.5
17. Holder battery C
18. Two screws 1.7 x 3
19. SY5 board
19
16
SY2 board
SY3 board
ST1 board
17
CA2 board
MC3 board
PW2 board
SY1 board
CA3 board
SY4 board
PW1 board
CA1 board
– 23 –
SY5 board
Page 24
5. ELECTRICAL ADJUSTMENT
5-1. Table for Servicing Tools
Ref. No.
J-1
J-2
J-3
J-4
J-5
Note: J-1 color viewer is 100 - 110 VAC only.
Color viewer 5,100 K
Siemens star chart
Calibration software
Chart for color adjustment
Extension cord
Name
Part code
VJ8-0007
VJ8-0178
VJ8-0155
VJ8-0176
6. Lens Adjustment
7. CCD Defect Detect Adjustment
8. LCD Panel Adjustment
8-1. LCD H AFC Adjustment8-2. LCD RGB Offset Adjustment8-3. LCD Gain Adjustment
8-4. LCD Blue Brightness Adjustment
8-5. LCD Red Brightness Adjustment
Note: If the lens, CCD and board in item 5-7, it is necessary
to adjust again. Adjustments should be carried out in
sequence. For 7, carry out adjustment after sufficient
charging has taken place.
J-1J-2
J-3
J-4
J-5
5-4. Setup
1. System requirements
Windows 98 or Me
IBM R -compatible PC with Pentium processor
CD-ROM drive
3.5-inch high-density diskette drive
USB port, 40 MB RAM
Monitor which allows full-color or high-color display
IEEE1394 port (when carrying out IEEE1394 operation compliance checks)
2. Installing calibration software
1. Insert the calibration software installation diskette into your
diskette drive.
2. Open the explorer.
3. Copy the DscCal_162 folder on the floppy disk in the FD
drive to a folder on the hard disk.
3. Installing USB driver
Install the USB drive which are included in the computer connection kit.
4. Installing IEEE1394 driver (when carrying out IEEE1394
operation compliance checks)
Install the B’s CLip which are included in the computer connection kit.
5-2. Equipment
1. Oscilloscope
2. Digital voltmeter
3. PC (IBM R -compatible PC, Pentium processor, Window
98 or Me)
4. AC adaptor
5-3. Adjustment Items and Order
1. IC501 Oscillation Frequency Adjustment
2. 5.1 V (A) Voltage Adjustment
3. 12.4 V (L) Voltage Adjustment
4. Hall Element Adjustment
5. AWB Adjustment
5. Color Viewer
Turn on the switch and wait for 30 minutes for aging to take
place before using Color Pure.
6. Computer screen during adjustment
Calibration
AWB
Focus
UV Matrix
Cal Mode
Cal Data
USB strage
VID
Get
PID
Set
MAC address
Get
OK
OK
Upload
Firmware
Image
Initialize
EVF
LCD Type
LCD
R Bright
RGB Offset
Tint
H AFCTest
Serial
Set
Set
Rev.
B Bright
Gain
Phase
Set
Set
Set
– 24 –
VCOMDC
VCOMPP
Setting
Language
Video Mode
Page 25
5-5. Connecting the camera to the computer
1. Turn on the camera and PC.
2. Insert the camera-side connector of the USB cable into the USB port of the camera.
3. Insert the PC-side connector of the USB cable into the USB port of the PC.
CAUTION
This product utilizes a laser.
The adjustment other than those specified herein may result
in hazardous radiation exposure.
Q5109 collector or CL540
Frequency counter
VR511
200 ±1 kHz
Q5109
CL525
Side A
CL540
VR513
CL529
VR512
Adjustment method:
1. Adjust with VR511 to 200 ±1 kHz.
2. 5.1 V (A) Voltage Adjustment
Measuring Point
Measuring Equipment
ADJ. Location
ADJ. Value
Adjustment method:
1. Adjust with VR512 to 5.15 ±0.05 V.
CL529
Digital voltmeter
VR512
5.15 ±0.05 V
3. 12.4 V (L) A Voltage Adjustment
Measuring Point
Measuring Equipment
ADJ. Location
ADJ. Value
Adjustment method:
1.Adjust with VR513 to 12.40 ±0.10 V
CL525
Digital voltmeter
VR513
12.40 ±0.10 V
4. Hall Element Adjustment
[CA2 board (Side A and B)]
VR511
Side B
Note:
1. Voltage adjustment is necessary to repair in the PW1 board
and replace the parts.
Storobe discharge:
1. Remove the solders of JW541 (pink, 330 V) and JW542
(blue, GND) on the ST1 board.
Preparation:
1. Do not activate the ST1 board when adjusting the voltage.
(If activating the circuits on the ST1 board, be sure to connect a stroboscope main condenser beween JW541 and
JW542 first.)
2. Connect CN107 on the CA2 board and CN501 on the PW1
board with extension cord.
3. Connect the LCD panel and EVF panel.
4. Set the iD disc.
3. Set the power on with still mode, and set the through im-
age. (S1703 open condition.)
VR972
VR971
Side A
TP971
TP973
TP974
TP972
Side B
Adjustment condition:
1. After adjustment, the readjustment is necessary to replace
the lens and the CA2 board.
Adjustment method:
1. Set the power on at the REC mode, and turn on the LCD.
2. Connect TP974 and TP972. The iris will close and get dark.
3. Adjust VR972 so that the voltage of TP971 is 1.0 ± 0.03 V.
4. Disconnect TP974 and TP972, and then connect TP973
and TP972. The iris will open, and display the monitor.
5. Adjust VR971 so that the voltage of TP971 is 3.0 ±0.03 V.
– 26 –
Page 27
5. AWB Adjustment
Cable
2. Double-click on the DscCalDi126a.
3. Click the Focus, and click the Yes.
4. Lens adjustment value will appear on the screen.
5. Click the OK.
7. CCD Defect Detect Adjustment
Preparation:
POWER switch: ON (Set the camera mode.)
Adjustment method:
1. Double-click on the DscCalDi126a.
2. Select “CCD Defect” on the LCD “Test”, and click the “Yes”.
3. After the adjustment is completed, OK will display.
4. Click the OK.
Camera
0 - 18 cm
All white pattern
Color viewer (5,100K)
Preparation:
POWER switch: ON
Adjusting method:
1. When setting the camera in place, set it to an angle so that
nothing appears in any part of the color viewer except the
white section. (Do not enter any light.)
2. Double-click on the DscCalDi126a.
3. Click the AWB, and click the Yes.
4. AWB adjustment value will appear on the screen.
5. Click the OK.
6. Lens Adjustment
Cable
8. LCD Panel Adjustment
[CA3 board (Side A)]
CL415
CL414
CL416
VR171
8-1. LCD H AFC Adjustment
Preparation:
POWER switch: ON
Adjusting method:
1. Double-click on the DscCalDi126a.
2. Select 0 on the LCD “H AFC”.
3. While watching the LCD monitor, adjust VR171 so that the
edge of the LCD adjustment frame are the same distance
from the left and right edge of the LCD screen. (A = B)
Camera
Approx.
100 cm ± 3 cm
Siemens
star chart
Preparation:
POWER switch: ON
Adjustment condition:
More than A3 size siemens star chart
Fluorescent light illumination with no flicker
Illumination above the subject should be 400 lux±10 %.
Adjustment method:
1. Set the siemens star chart 100 cm ± 3 cm so that it becomes center of the screen.
LCD
LCD screen
A
adjustment
B
frame
FPC
8-2. LCD RGB Offset Adjustment
Adjusting method:
1. Adjust LCD “RGB offset” so that the amplitude of the CL416
waveform is 7.3 V ± 0.3 Vp-p.
– 27 –
Page 28
7.3 V
± 0.3 Vp-p
VG
CL416 waveform
8-3. LCD Gain Adjustment
Adjusting method:
1. Adjust LCD “Gain” so that the amplitude of the CL416 waveform is 4.0 V ± 0.1 Vp-p.
Note:
8-2. LCD RGB Offset adjustment should always be carried
out first.
4.0 V
± 0.1Vp-p
CL416 waveform
8-4. LCD Blue Brightness Adjustment
Adjusting method:
1. Adjust LCD “B Bright” so that the amplitude of the CL414
waveform is VG + 0.2 ± 0.05 Vp-p with respect to the CL416
(VG) waveform.
Note:
8-2. LCD RGB Offset adjustment and 8-3. LCD Gain adjustment should always be carried out first.
CL416 waveform
VG + 0.2
± 0.05 Vp-p
CL414 waveform
8-5. LCD Red Brightness Adjustment
Adjusting method:
1. Adjust LCD “R Bright” so that the amplitude of the CL415
waveform is VG – 0.1 ± 0.05 Vp-p with respect to the CL416
(VG) waveform.
Note:
8-2. LCD RGB Offset adjustment and 8-3. LCD Gain adjustment should always be carried out first.
VG
– 28 –
CL416 waveform
VG – 0.1
± 0.05 Vp-p
CL415 waveform
Page 29
6. MAC ADDRESS
1. SETTING MAC ADDRESS
MAC addresses consist of 64-bit numbers (hexadecimal format) which are unique for each separate device which is compatible with IEEE1394. As a result, if these numbers are incorrect, it will cause problems with device identification if using this device while connected to a network which is being
used by a large number of other IEEE1394-compliant devices,
and this can result in inconvenience to the customer. Therefore, MAC addresses are assigned separately for each device and are written to the device’s memory during the manufacturing process. The first seven characters of the MAC address for this device (08007B5) are fixed (as indicated by the
manufacturer), and all subsequent characters are unique for
each separate device.
2. CHECKING AND WRITING THE MAC ADDRESS
1. Check the MAC address when rewriting the firmware. Before rewriting the firmware, click Get in the MAC Address
window of the adjustment screen, and write down the MAC
address.
2. After the CA2 board has been replaced, you need to write
the MAC address to the memory.
3. WRITING THE MAC ADDRESS TO THE MEMORY
1. Turn on the power for the computer and the camera. The
camera will be ready for use 30 seconds after the power
for the camera is turned on.
2. Set the camera to communication mode (“PC--U” will appear).
3. Connect the camera to the computer by the extension cord.
4. Start up the calibration software on the computer.
5-1. If the firmware has been rewritten
1. After rewriting the firmware, click Get in the MAC Address window of the adjustment screen, and check that
the MAC address is unchanged from what it was before
the firmware was rewritten.
2. If the MAC address is different from what it was before
the firmware was written, enter the MAC address code
before the firmware was written, and then click Set.
3. Click Get and check that the correct MAC address was
written correctly.
5-2. If the CA2 circuit has been replaced
1. Enter the MAC address code which was provided with
the sub-board in the MAC Address window of the adjustment screen, and then click Set.
6. Close the calibration software on the computer.
VR511645 019 5150VR,SEMI,10K S
VR512645 028 2201VR,SEMI,2.2K S
VR513645 028 2201VR,SEMI,2.2K S
(INDUCTORS)
L5001645 031 3622INDUCTOR,47U M
L5002645 037 0632INDUCTOR,47U M
L5003645 037 0632INDUCTOR,47U M
L5004645 037 0632INDUCTOR,47U M
L5006645 030 9854INDUCTOR,600 OHM
L5007645 021 5315INDUCTOR,110 OHM
L5101645 037 1530INDUCTOR,47U K
L5102645 037 1530INDUCTOR,47U K
L5103645 037 1530INDUCTOR,47U K
L5104645 037 1523INDUCTOR,10U K
L5105645 037 1530INDUCTOR,47U K
L5106645 037 1530INDUCTOR,47U K
L5107645 037 1523INDUCTOR,10U K
L5108645 037 0632INDUCTOR,47U M
L5109645 037 0632INDUCTOR,47U M
L5201645 038 2000INDUCTOR,33U M
L5202645 031 3622INDUCTOR,47U M
L5203645 038 2000INDUCTOR,33U M
L5204645 031 3622INDUCTOR,47U M
L5205645 037 0625INDUCTOR,4.7U M
(CAPACITORS)
C5201403 341 4803CERAMIC 10U K 10V
C5203403 215 1006CERAMIC 470P J 50V
C5204403 337 9508CERAMIC 0.15U K 10V
C5205403 113 4109CERAMIC 2200P K 50V
C5206403 337 9508CERAMIC 0.15U K 10V
C5207403 113 4109CERAMIC 2200P K 50V
C5208403 157 4202CERAMIC 220P J 50V
C5209403 338 2904CERAMIC 0.47U K 10V
C5210403 311 1801CERAMIC 1U K 10V
C5211403 311 1801CERAMIC 1U K 10V
C5212403 337 9508CERAMIC 0.15U K 10V
C5213403 113 4109CERAMIC 2200P K 50V
C5214403 113 4109CERAMIC 2200P K 50V
C5215403 337 9508CERAMIC 0.15U K 10V
42
Page 43
LOCATION PARTS NO.DESCRIPTIONLOCATION PARTS NO.DESCRIPTION
C5216403 157 3106CERAMIC 56P J 50V
C5217403 215 1006CERAMIC 470P J 50V
C5218403 311 1801CERAMIC 1U K 10V
C5219403 157 3106CERAMIC 56P J 50V
C5220403 215 1006CERAMIC 470P J 50V
C5221403 157 3106CERAMIC 56P J 50V
C5222403 215 1006CERAMIC 470P J 50V
C5223403 311 1801CERAMIC 1U K 10V
C5224403 157 3106CERAMIC 56P J 50V
C5230403 311 1801CERAMIC 1U K 10V
C5231403 325 0807POS-SOLID 150U M 6.3V
C5232403 155 2309CERAMIC 4700P K 50V
C5234403 334 3806CERAMIC 10U K 6.3V
C5235403 311 1801CERAMIC 1U K 10V
C5236403 351 0406POS-SOLID 220U M 4V
C5237403 155 2309CERAMIC 4700P K 50V
C5238403 334 3806CERAMIC 10U K 6.3V
C5239403 311 1801CERAMIC 1U K 10V
C5240403 351 0406POS-SOLID 220U M 4V
C5241403 155 2309CERAMIC 4700P K 50V
C5243403 334 3806CERAMIC 10U K 6.3V
C5244403 311 1801CERAMIC 1U K 10V
C5245403 351 0406POS-SOLID 220U M 4V
C5246403 155 2309CERAMIC 4700P K 50V
C5247403 334 3806CERAMIC 10U K 6.3V
(RESISTORS)
R5201401 105 4007MT-GLAZE 330 JA 1/16W
R5202401 250 6208MT-GLAZE 270K DC 1/16W
R5203401 250 5003MT-GLAZE 100K DC 1/16W
R5204401 105 8005MT-GLAZE 1M JA 1/16W
R5205401 250 6208MT-GLAZE 270K DC 1/16W
R5206401 250 5003MT-GLAZE 100K DC 1/16W
R5207401 105 8005MT-GLAZE 1M JA 1/16W
R5209401 105 0504MT-GLAZE 1K JA 1/16W
R5210401 241 5807MT-GLAZE 22K DC 1/16W
R5211401 241 2400MT-GLAZE 2.2K DC 1/16W
R5212401 105 0504MT-GLAZE 1K JA 1/16W
R5213401 250 6208MT-GLAZE 270K DC 1/16W
R5214401 250 5003MT-GLAZE 100K DC 1/16W
R5215401 105 8005MT-GLAZE 1M JA 1/16W
R5216401 105 8005MT-GLAZE 1M JA 1/16W
R5217401 250 5003MT-GLAZE 100K DC 1/16W
R5219401 105 6001MT-GLAZE 5.6K JA 1/16W
R5220401 105 4007MT-GLAZE 330 JA 1/16W
R5221401 105 6001MT-GLAZE 5.6K JA 1/16W
R5222401 105 4007MT-GLAZE 330 JA 1/16W
R5223401 105 6001MT-GLAZE 5.6K JA 1/16W
R5224401 105 4007MT-GLAZE 330 JA 1/16W
R5225401 105 6001MT-GLAZE 5.6K JA 1/16W
R5227401 105 0603MT-GLAZE 10K JA 1/16W
R5228401 105 0603MT-GLAZE 10K JA 1/16W
R5229401 105 5905MT-GLAZE 560 JA 1/16W
R5230401 105 2102MT-GLAZE 18K JA 1/16W
R5231401 105 1105MT-GLAZE 12K JA 1/16W
R5232401 105 0504MT-GLAZE 1K JA 1/16W
R5233401 241 5708MT-GLAZE 18K DC 1/16W
R5234401 241 5005MT-GLAZE 7.5K DC 1/16W
R5235401 241 0802MT-GLAZE 220 DC 1/16W
R5236401 241 0802MT-GLAZE 220 DC 1/16W
R5237401 105 0504MT-GLAZE 1K JA 1/16W
R5238401 105 0504MT-GLAZE 1K JA 1/16W
R5239401 241 5401MT-GLAZE 12K DC 1/16W
R5240401 241 5302MT-GLAZE 10K DC 1/16W
R5241401 241 2004MT-GLAZE 1.2K DC 1/16W
R5242401 105 7909MT-GLAZE 0.000 ZA 1/16W
R5243401 105 0504MT-GLAZE 1K JA 1/16W
R5244401 105 0504MT-GLAZE 1K JA 1/16W
R5245401 241 5401MT-GLAZE 12K DC 1/16W
R5246401 241 5104MT-GLAZE 8.2K DC 1/16W
R5247401 241 2004MT-GLAZE 1.2K DC 1/16W
R5248401 241 1007MT-GLAZE 330 DC 1/16W
R5249401 105 0504MT-GLAZE 1K JA 1/16W
R5250401 105 0504MT-GLAZE 1K JA 1/16W
R5251401 241 5401MT-GLAZE 12K DC 1/16W
R5252401 241 5104MT-GLAZE 8.2K DC 1/16W
R5253401 241 2608MT-GLAZE 2.7K DC 1/16W
R5254401 105 7909MT-GLAZE 0.000 ZA 1/16W