SANYO IDC-1000ZE, IDC-1000ZEX, IDC-1000ZU SERVICE MANUAL
SERVICE MANUAL
FILE NO.
Digital Disc Camera
Contents
1. iD PHOTO DISC ........................................................2
2. OUTLINE OF iD FORMAT DISC DRIVE CIRCUIT....4
3. OUTLINE OF CIRCUIT DESCRIPTION .................... 9
4. DISASSEMBLY........................................................20
5. ELECTRICAL ADJUSTMENT..................................24
6. MAC ADDRESS.......................................................29
7. TROUBLESHOOTING GUIDE.................................30
IDC-1000ZE
(Product Code : 126 250 01)
(U.K.)
IDC-1000ZEX
(Product Code : 126 250 02)
(Europe)
(General PAL area)
IDC-1000ZU
(Product Code : 126 250 03)
(U.S.A.)
(Canada)
8. PARTS LIST.............................................................31
ACCESSORIES & PACKING MATERIALS .............31
CABINET & CHASSIS PARTS 1 ............................. 32
CABINET & CHASSIS PARTS 2 ............................. 34
CABINET & CHASSIS PARTS 3 ............................. 35
ELECTRICAL PARTS ..............................................36
CIRCUIT DIAGRAM (Refer to the separate volume)
PRODUCT SAFETY NOTICE
The components designated by a symbol ( ! ) in this schematic diagram designates components whose value are of
special significance to product safety. Should any component designated by a symbol need to be replaced, use only the part
designated in the Parts List. Do not deviate from the resistance, wattage, and voltage ratings shown.
CAUTION
This product utilizes a laser.
The adjustment other than those specified herein may result in hazardous radiation exposure.
CAUTION : Danger of explosion if battery is incorrectly replaced.
Replace only with the same or equivalent type recommended by the manufacturer.
Discard used batteries according to the manufacturer’s instructions.
NOTE : 1. Parts order must contain model number, part number, and description.
Design and specification are subject to change without notice.
SX111/E, EX, U
2. Substitute parts may be supplied as the service parts.
3. N. S. P. : Not available as service parts.
REFERENCE No. SM5310255
1. iD PHOTO DISC
1-1. iD PHOTO DISC HIGH-DENSITY TECHNOLOGY
The iD Photo Disc has a diameter of 5 centimeters and yet it
can store up to 730MB of information. A laser pulse magnetic
field modulation recording method and CAD-type ultra-high
magnetic resolution method have been used to record data
at a track pitch of 0.6 µm and an extremely short mark length
of 0.235 µ, which is smaller than the spot diameter of the
laser beam.
1-2. LASER PULSE MAGNETIC FIELD MODULA TION
RECORDING METHOD
The beam which is generated by the laser pickup in the iD
Photo disc drive focuses onto the disc recording medium as
a spot with a diameter of about 1 µm. During recording, a
mark with a diameter of 0.235 µm -- which is smaller than the
diameter of the laser beam spot-- is recorded. A “laser pulse
magnetic field modulation” recording method has been
adopted in order to achieve this. This recording method involves firstly a magnetic head which applies a magnetic field
which is modulated in accordance with the data supplied externally which is to be recorded. In this state, the laser beam
is directed to the reverse side of the disc. The radiated light
within an 0.6 µm-diameter area at the center of the beam
spot is momentarily heated to a temperature of around 200
degrees. The data is then recorded by means of the resulting
change in the magnetic polarity of the recording layer. The
recording mark which is made by this pulse-type laser beam
is accurately formed in the track at a diameter of 0.6 µm. The
rotation of the disc causes each recording mark to overlap
the preceding mark at a point 0.235 µm forward of the preceding mark. As a result, the circles formed according to the
state of the laser beam move along and leaves a continuous
series of minute crescent-shaped marks 0.235 µm across.
These marks are approximately one-quarter the size of the
recording marks which are made on other media such as CDs
and MOs. The iD Photo disc is a magneto-optical disc which
records data uses the principle of applying magnetism and
temperature sumultaneously so that the recording medium
can maintain its magnetic polarity. Because of this, the data
cannnot be erased simply by placing the disc within a magnetic field, and moreover the recording method does not result in any changes to the physical nature of the disc. This
means that stable characteristics can be maintained for respected disc writing operations.
recording laser beam
disc movement direction
1-3. CAD ULTRA-HIGH MAGNETIC RESOLUTION
METHOD
In order to play back the extremely small marks which have
been recorded using laser pulse magnetic field modulation,
the iD Photo disc uses a ultra-high magnetic resolution
method which incorporates CAD (Center Aperture Detection).
Ultra-high magnetic resolution is a form of technology in which
a magnetic signal taken from only the center of the spot is
extracted for playback. The iD Photo disc has a multi-layered structure which comprises a polycarbonate substrate,
upon which is the playback layer with magnetic characteristics, a recording layer which stores the data, and finally a
heat dispersion layer which rapidly allows the spot which has
been heated by the laser beam to cool. When data is played
back from the disc, the laser beam which is generated by the
pickup passes through the polycarbonate substrate to reach
the playback layer, and focuses on a 1-µm spot. This playback layer functions as a screen to shield the recording layer
on which the data is recorded from the laser beam, so that
only a 0.6 µm diameter area at the center of the laser beam
which reaches the playback layer passes through it and is
projected onto the magnetic recording area of the recording
layer by means of an increase in temperature (window). The
recorded data can be picked up and read through this “window”, and the surrounding area is shielded. Moreover, in general the spacing between the tracks is narrow and so signal
interference from tracks which are next to the track being read
can occur. However, CAD-type ultra- high magnetic resolution also solves this interference problem. With CAD-type ultra-high magnetic resolution, only the magnetic signal which
passes throught the window at the center of the beam spot is
read, so that the playback reading area can be restricted to a
very narrow area not only in the tracking direction, but also in
the transverse direction. As a result, signal interference is
suppressed, and the spacing between the tracks can also be
made smaller.
playback laser beam
disc movement direction
MO pit
0.235µm
T
ultra-high magnetic
resolution window
value
temparature
distribution
recording layer
playback layer
Fig. 2
MO pit
0.235µm
recording spot
Fig. 1
– 2 –
1-4. PRML SIGNAL PROCESSING
When the data on the iD Photo disc is read, the 0.235 µm
overlapping recording marks which are made during laser
pulse magnetic field modulation recording are read through
an 0.6 µm window by means of a CAD-type ultra-high magnetic resolution reading method. Because this window has a
diameter of 0.6 µm, at least two or three recording marks can
be viewed through this window at any given time. With the iD
Photo disc, PRML signal processing has been adopted as
the signal processing method for this readable area. PRML
signal processing compares the signal wave pattern which is
detected when recording marks with several different pattern
types pass by the window with the signal wave pattern which
is actually obtained by the pickup in order to recreate the
data which has actually been recorded. This technology makes
it possible to accurately reproduce the recording marks which
are smaller than the window being used to read them, and if
a signal pattern which is not valid is read, then it is handled
as an error. In this way, recording and playback of data at
high densities can be couple with high data reliability.
1-5. ZCLV METHOD OF ROTATION CONTROL
A ZCLV (Zoned Constant Linear Velocity) method of rotation
control has been adopted for the iD Photo disc. The ZCLV
method increases the disc rotation speed on a zone basis in
accordance with the progression toward the center of the disc
as the speed of rotation of the disc recording surface with
respect to the pickup becomes progressively slower. The iD
Photo disc is devided into 12 bands from the outside to the
inside of the disc surface, and the rotation speed within each
band is varied within a range of 1900-3100 rpm in order to
maintain the speed of rotation of the recording surface with
respect to the pickup to a level of about 5 meters per second.
1-6. EXTERNAL CLOCK SIGNAL
The iD Photo disc uses an external clock method to gener-
ate the clock pulses which are used to regulate the timing for
reading and writing of data. With conventional methods, the
clock pulse is generated based on changes in the data being
read. However, with this external clock method, an FCM (Fine
Clock Mark) signal is created beforehand and recorded onto
the disc for use as a reference signal in order to generate the
clock pulse. The timing of this FCM signal is monitored during reading of data in order to control the oscillation frequency
of the clock signal generator in accordance with the rotation
of the disc. The Fine Clock Mark is engraved accurately onto
the disc when the disc is manufactured, and it can then be
used as an accurate reference for stable reading and writing.
– 3 –
2. OUTLINE OF iD FORMAT DISC DRIVE
CIRCUIT
1. OUTLINE OF DRIVE CIRCUIT BOARD
A drive part is composed of the block diagram of the Fig. 1,
and a drive circuit board is composed of MC1, MC2 and MC3.
CAMERA
CAMERA
ASIC
CA2
CPU
Processor
BUS
ATA BUS
(IDE)
50øAS-MO DRIVE CIRCUIT BOARD (MC3)
WDTX(reverse of WDT)
(A/D) THERMO
MO signal (play signal)
(A/D) FCLKAMPL
(A/D) ADRSAMPL
DRIVE
ASIC
(PWM output) FCSR
(PWM output) FCSF
(PWM output) TRKR
(PWM output) TRKF
(PWM output) SLDR
(PWM output) SLDF
SDRAM
(64Mbit)
FCLKNP
FCLKPP
FCLKZ
ADRSPLS
(A/D) FES
(A/D) TES
(A/D) SUM
SPREF
16bit
WDT
WCLK
WG
SDCLK
96
168
167
186
136
190
161
160
162
163
189
193
192
191
209
208
212
211
207
206
205
165
171
"0" Rec
"1" Play
RF Amplifier
FCM/ADDR
Amplifier
Servo
Amplifier
Servo
Driver
(BD6603KVT)
Lazer POWER
Control
(TA6015F)
MAGNETIC HEAD
DRIVER CIRCUIT
THERMO
I
J
Photo
A
sensor
B
output
C
D
A
Temparature
B
sensor
C
D
E
F
Tracking
G
H
actuator
T+
T-
SLED+
SENSOR
SLED-
BOARD
(MC2)
F+
F-
U/V/W/COM
Iout
LD-ON/Off
RF-On/Off
(oscillation circuit
On/Off)
PS-On/Off(Power
saveOn/Off)
ST(abnormal
detection)
BOARD (MC1)
Magnetic
head
Pick Up
Focus
actuator
Sread
motor
Laser
APC IC
(included
PICK UP)
DRIVE MECHA and
MECHA CIRCUIT
BOARD
iD disc(50ø)
Spindle
VCC
motor
LD
PD
2. OUTLINE EXPLANATION OF DRIVE CIRCUIT
BOARD
2-1. MAGNETIC HEAD DRIVER CIRCUIT BOARD (MC1)
During recording, it is the driver circuit board to magnetize
toward the magnetic head.
WD_P
WD_N
EJULK
EJLK
Large current
buffer
Magnetic
head
UP/DOWN
sensor
FET array
Amplitude
limitation circuit
Amplitude
limitation circuit
+ MH+
- MH-
MC1
2-1-1. EXPLANATION OF OPERATION
During recording, the data (WD_P and WD_N) from the MC3
circuit board is used to operate the large current buffer at IC801
in order to turn the FET array on and off. This is turn determines the direction of the magnetic field applied to the magnetic head. Also an upper limit is decided so that a magnetic
field level may not be bigger at the amplitude limitation circuit
by the data.
To the
magnetic
head
To the
magnetic
head
Fig. 2
The ascent and descent condition of the magnetic head is
being watched with the magnetic head up and down sensor.
2-2. SENSOR CIRCUIT BOARD (MC2)
WRPROT
CARTRG
PUINI
SPDLW
SPDLU
SPDLV
SPDLCOM
S8003
Disc write protect detection switch
S8004
Disc setting detection switch
D8003
Pick up location detection sensor
MC2
2-2-1. EXPLANATION OF OPERATION
Sensor circuit board (MC2) is the relay circuit board for the
disc write protection detection, disc setting detection switch,
the pickup location detection sensor and spindle motor control signal.
– 4 –
Fig. 1
To the
spindle
motor
Fig. 3
2-3. OUTLINE EXPLANA TION FOR EACH BLOCK OF
DRIVE CIRCUIT BOARD (MC3)
2-3-1. SERVO AMPLIFIER
They are amplifier part for the focus servo and the tracking
servo.
1. FOCUS SERVO (DISC SURF ACE RUNOUT TRACKING CONTROL)
Servo control is carried out by the DSP which is built into the
ASIC (IC402). This controls the focus actuator of the pickup in
order to carry out surface runout tracking control.
Minute
amplitude
inside
Land
Groove
C
B
Land
D
A
Groove
outside
Land
A, B, C, D
Focus
actuator
IC831
SSI33P3721
Gain-Amp
(x1.4)
2.5V
GND
FES Matrix
[Kf(A+C)-(B+D)]
AGC on/off
1. Focus offset adjustment
When the servo and laser are both off, the DSP of the ASIC
(IC402) samples the FE (focusing error) signal and obtains
average values which are used to control the offset cancel
registers of SSI33P3721 (IC402) in order to cancel the electrical offset. The signal level is set to 2.5 V DC.
2. Focus gain adjustment
The DSP of the ASIC (IC402) carries out focus searching to
measure the peak levels (+/–) for the S-shaped characteristics of the FE signal, and sets the ABCD gain (focus gain) for
the SSI (IC831) in accordance with these values. The above
The S-shaped curve amplitude of the focus error signal
(FE signal) is TYP 1.2Vp-p
Focus error singal
observation terminal
(TP810)
IC815
DRIVE ASIC
MACRO
FES
PWM 3/4
FCSF FCSR
4
IN2R
IN2F
H2F
H2R
OUT
OUT
14
DSP
5
12
The OA amplifiers and power supply
of the analog switches are all 5V.
AGC
WG
"0" REC
"1" PLAY
OFFSET
CANCEL
2.5V
Gain-Amp
Read (x1.22)
Write (x0.76)
IC835
(AD8532)
IC833
(ADG702)
FES
BD6603KVT
ABCD gain for the SSI is adjusted by the microprocessor in
order to maintain the VPP for the S-shaped characteristics of
the FE signal to approximately 1.18 V. The ABCD gain for the
SSI can be adjusted within the range of x1.2 to x4.3. During
recording (when the laser is at high power), the signal amplitude is reduced by about half before the FE signal is input to
the DSP of the ASIC (IC402).
3. Focus servo ON
The DSP of the ASIC (IC402) moves the focus actuator up
and down to control the FE signal so that its AC component is
“0”.
Fig. 4
2. TRACKING SERVO (MAIN PP AND PP SUBTRACTION METHOD)
Servo control is carried out by the DSP which is built into the
ASIC (IC402). This controls the tracking actuator and the thread
inside
Land
Groove
HF
C
B
Land
D
A
E
Groove
outside
G
Land
Tracking
actuator
Sread
actuator
A, B, C, D
E, F, G, H
Main Beam PP
[(A+D)-(B+C)]
IC814
(AD8054)
Sub Beam PP
α[(F+G)-(H+E)]
IC814
(AD8054)
IC814
(AD8054)
Gain-Amp
(±6dB)
IC837
(AD8051)
Offset
adjustment
SSI33P3721
2x[(A+D)-(B+C)]α[(F+G)-(H+E)]
actuator of the pickup in order to carry out rotation offset tracking control.
Tracking error signal
observation terminal
(TP811)
LPF
Gain-Amp
(x1~x2.2)
WG
"0" REC
"1" PLAY
TZC
OFFSET
CANCEL
2.5V
TZC
Buf
IC835
(AD8532)
IC834
(ADG702)
TES
IC815
BD6603KVT
TZC
(tracking
zero cross)
FES
PWM 5/6
TRKFTRKR
2
IN1R
IN1F
H1F
OUT
9
3
H1R
OUT
7
MACRO
PWM 1/2
SLDF
36
IN4F
H4F
OUT
40
DSP
SLDR
– 5 –
35
IN4R
H4R
OUT
42
Fig. 5
1. Tracking offset adjustment
When the servo and laser are both off, the DSP of the ASIC
(IC402) samples the TE (tracking error) signal in order to control the offset cancel of SSI33P3721 (IC831) in order to cancel the electrical offset.
2. Tracking gain adjustment
When the focus servo is on, the DSP of the ASIC (IC402)
measures the amplitude of the TE signal and uses it to set
the CGA amp gain of the SSI (IC831).
2-3-2. FCM/ADDR AMPLIFIER
1. FCM AMPLIFIER
FCM is an abbreviation for Fine Clock Mark. This is used as
the external clock reference to generate the signal which becomes the syncronizing standard for the drive circuit board.
3. Balance adjustment of main PP and sub PP
This measures the DC offset when shifting to the inside and
to the outside occurs, with respect to the center of the TE
signal when the actuator is shifted 0.83 V to the outside, when
it is shifted 0.83 V to the inside and when it is at the standard
position.
4. Servo ON (disc rotation offset tracking)
The DSP of the ASIC (IC402) moves the tracking actuator to
the left or right to control the TE signal so that its AC component is “0”.
inside
Land
Groove
A, B, C, D
outside
C
D
B
A
Land
Groove
IC814
(AD8054)
TPP Matrix
[(A+B)-(C+D)]
The OA amplifiers, analog switch
and the power supply of the
comparator IC are all 5V.
Land
IC854
(AD8054)
Attenuator
gain fixing
play: x 6.356
rec: x 3.33
FCLKGC
IC855
(ADG701)
Amp
IC857
(AD8534)
LC
Filter
WG
"0" REC
"1" PLAY
PEAK HOLD
circuit
BOTTOM
HOLD
circuit
VCA variable
range (± 4dB)
Ctrl
IC853
(BA7655)
FCLKAMPBTM
LC
Filter
1. Fine clock mark (FCM)
A computation ((A+B)–(C+D)) is carried out on the signals
from the photosensor, after which they pass through the VCA
circuit (IC853) and LPF circuit, and then the FCM signal amplitudes pass through the peak hold and bottom hold circuits
and are input to the DSP of the ASIC (IC402), where A/D
conversion is carried out. At the DSP of the ASIC (IC402), the
D/A value of the signal (FCLKGC) which has had the control
voltage adjusted by the VCA (IC853) is changed so that the
FCM level is set to the level which is necessary for the
FCLKNP and FCLKPP signals to be generated. Furthermore,
DSP of the ASIC (IC402) and the above circuits set the slice
level to 50 % - 70 % of the +/– side FCM marks so that the
comparator (IC852) (FCLKPP and FCLKNP) singals do not
delay the transfer of the address signals. The above circuits
adjust the signals so that the FCM amplitude is at about the
same level when at the default recording and playback power.
Furthermore, a ratio of 60 % or more between the + side and
the – side of the FCM signal is necessary when LAND is on
and when GROOVE is on. The DSP controls the control potential of the VCA (IC853) so that the Vpp of the FCM signal
is about TYP 1.7 Vp-p. Furthermore, the signal interval for
the FCM signals is 532 x 50 ns = 26.6 µs.
FCLKAMPL
Gain-Amp
x2
IC854
(AD8054)
upper slice level
lower slice level
ASIC
D/A
A/D
D/A
A/D
DSP process
FCMK signal
obwervation
LAND
FCM
FCLKPP
FCLKNP
FCLKSLS
FCLKSLSBTM
IC857
(AD8534)
VC25
termanal
(TP808)
IC851
(AD8534)
primary
function
circuit
primary
function
circuit
comparator
input allowable
value (0.8~3.6V)
LAND
FCM
2.5V
GROOVE
Comparator
FCM-PP
IC852
(LT1721)
Comparator
FCM-NP
IC852
(LT1721)
Comparator
FCM-Z
IC852
(LT1721)
26.6[µs]
AS-MO ASIC
160
FCLKPP
161
FCLKNP
162
FCLKZ
2.5V
2.5V
Fig. 6
2. FCLKPP/FCLKNP/FCLKZ
These are generated from the FCM signal by the comparator
(IC852) according to the timing shown in Fig. 7.
1. When LAND is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKPP
signal has been detected and the FCLKZ signal is rising.
2. When GROOVE is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKNP
signal has been detected and the FCLKZ singal is falling.
LAND
FCLKPP
FCLKZ
FCLKNP
GROOVE
Fig. 7
– 6 –
3. The principle of rec/play clock generated by the PLL
The clock is reproduced by the PLL with respect to the signal
which has been detected to be the FCM signal by the circuit
(primary function circuit) which generates the slice level from
the FCM signal. The frequency of the reproduced clock is 20
MHz.
4. LC filter
LC filters are located before and after the VCA (IC853). During recording, there is the possibility that the WCLK (20 MHz)
or other high-frequency interference can become mixed in with
2. ADDRESS DETECTION/AMPLIFIER
Mainly the address detection of the disc and signal process in
order to detect are done.
the FCM signal or the address signal. These LC filters remove
almost all of the signal components which are at 20 MHz or
above, leaving just the base frequencies (2-3 MHz) for the
FCM and address signals.
5. Peak hold for FCM signal and bottom hold circuit
These circuits use the amplitude modulation of the FCM signal to hold the peak level and the bottom level of the FCM
signal at the capacity which is connected to the transistor
emitter.
outside
Land
Groove
A, B, C, D
inside
C
D
B
A
Land
Groove
IC814
(AD8054)
Main Matrix
[(A+D)-(B+C)]
Land
ADRSGC
The OA amplifiers, analog switch
and the power supply of the comparator
IC are all 5V.
IC856
IC854
(AD8054)
Attenuator
Gain fixing
Read: x 6.81
Write: x 3.78
(ADG701)
IC857
(AD8534)
Amp
LC
Filter
WG
"0" REC
"1" PLAY
VCA
variable range
(± 4dB(min))
1. Address detection
The main PP signal ((A+D)–(B+D)) at the tracking servo amplifier shown in Fig. 5 passes through the VCA circuit (IC853)
and the LPF circuit, after which the address peak signal is
input to the DSP of the ASIC (IC402) and A/D conversion is
then carried out. As a result, the maximum amplitude of the
address signal is detected and the control potential of the VCA
AS-MO ASIC
189
173
163
A14
A02
ADRSPLS
Filter
Ctrl
IC853
(BA7655)
FCLKWIN
Gain-Amp
LC
IC859
(ADG702)
IC854
(AD8054)
PEAK HOLD
CIRCUIT
Comparator
VC25
comparator
input allowable value
(0.67~3.36V)
ADRSAMPL
ADRSGC
ADRSPLS
IC852
(LT1721)
(IC853) is changed so that the amplitude of the address signal can be changed to the appropriate level. Furthermore, it is
input to the comparator (IC852) to generate the address signal. This address signal is taken up by the DC macro of the
ASIC (IC402) to be used as the frame address and track address during recording and playback.
Fig. 8
2-3-3. RF AMPLIFIER
RF is the data signal that it is to be read by a pickup sensor (I, J).
Gain-Amplifier
x 8.17
I
J
IC838
(AD8062)
I/J is bias by 2.5 V (FREF).
SSI33P3721
Cutoff
AGC
Programmable
AGC on/off
MOAGCHLD
AGCOFFH
Boost
Equalizer
Filter
IC836
(ADG701)
During AGC OFF
Gain is decided.
– 7 –
+5VA
MO-RF
IC832
(AD8051)
2.0V
1.0V
AGCOFFH
TP801
(MO observation)
AS-MO ASIC
136
RF
137
REFTOP
138
REFBTM
221
P06
Fig. 9
The signals from the sensors (I/J) are pre-amplified by the
gain amplifier, and then pass through the AGC/equalizer of
the SSI (IC831), and are then input to the RF signal terminal
of the ASIC (IC402). The AGC control signal (AGCOFFH) from
the ASIC (IC402) is modulated to control the on/off status of
the AGC. When the AGC is on, the wave pattern monitored at
TP801 is adjusted to a constant amplitude.
2-3-4. SERVO DRIVER
The driver circuit of spindle motor, sread motor and each actuators are accumulated inside BD6603KVT (IC815). The
spindle motor is used three aspect sensorless motor (DC
motor).
2-3-5. LASER POWER CONTROL
TA6015F (optical disc power control (LPC): IC841) and
TA6012F (optical disc high speed APC) are used in the pairs.
An APC IC appears on the pickup. LPC (IC841) control makes
it possible to set characteristics such as playback power, recording peak power, duty, laser on/off setting and low power
consumption standby mode using the register settings of the
LPC (IC841).
3. BLOCK DIAGRAM OF PLAY/REC AND SIGNAL PROCESS etc.
APC IC (on the pickup)
The APC IC functions to maintain the current detected by the
photosensor attached to the laser to a constant level. This
has the effect of canceling any fluctuations in characteristics
resulting from the semiconductor laser temparature, and any
variances in production lots, so that the laser power can be
maintained at a stable level. The ON/OFF laser high-frequency
currents, power save and laser are output open corrector from
LPC IC, and input to APC IC.
Superimposing high-frequency currents
When a high-output semiconductor laser is used, interference
can be generated from the light which is reflected back from
the disc. Because of this, high-frequency currents of 300-600
MHz are superimposed on the laser drive currnet to reduce
interference.
2-3-6. SDRAM
This is used as a WORK for ECC encoding and decoding, as
a buffer for seamless recording and playback, and as a drive
cache.
Magnetic field strength
MH
Driver
SSI
IC
Gain
G.C
Gain
G.C
DRIVE ASIC
A/D
2T signal
PLL
Slice Level
ADRS
Dec.
SH
APC
IC
LPC
IC
EQ, fc, Boost
MO
FCM
Adrs
WCLK
Duty Pr Pw
Temparature
sensor
1. Playback clock by PLL
The playback clock (20 MHz) which is generated from the
FCLKPP/FCLKNP signals (see Fig. 7) obtained from the FCM
is played back. The spindle motor operation is controlled by
CL V (constant linear velocity) to provide a constant FCM cycle
(26.6 µs). Accodingly, the rotation becomes faster as tracking
moves toward the center of the disc.
RCLK
Tap coefficient
Digital
EQI
Delay
Off Track
Tilt Mark
CPU
Delay
quantity
Expectation
value
PRML
PR(1, 1)
2T/8T
amplitude
ratio
ECC
Fig. 10
– 8 –
3. OUTLINE OF CIRCUIT DESCRIPTION
10
9 6 5 4 3 2 1
13
14 15 16 17
18
19
20
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
Vertical register
Horizontal register
Note
Note: Photo sensor
VOUT
GND
NC
NC
V
ø3
øSUB
NC
C
SUB
NC
V
L
øRG
12
GND
11
VDD
7
GND
8
NC
V
ø2B
Vø2A
Vø1
Hø1
Hø2
3-1. CA1 CIRCUIT DESCRIPTION
Around CCD block
1. IC Configuration
IC903 (ICX267) CCD imager
IC902, IC904, IC908 (74ACT04MTC) H driver
IC907 (CXD3400N) V driver
IC905 (AD9803) CDS, AGC, A/D converter
2. IC903 (CCD)
[Structure]
Interline type CCD image sensor
Optical size 1/2 type
Effective pixels 1392 (H) ×1040 (V)
Pixels in total 1434 (H) ×1050 (V)
Actual pixels 1360 (H) × 1024 (V)
Optical black
Horizontal (H) direction: Front 2 pixels, Rear 40 pixels
Vertical (V) direction: Front 8 pixels, Rear 2 pixels
Dummy bit number Horizontal : 20 Vertical : 3
Pin 1
2
V
2
Pin 11
Fig. 1-1.Optical Black Location (Top View)
Pin No.
1
2, 3
4
5, 6, 8,
14, 16
7, 9, 12
10
11
13
15
Symbol
Vφ
φSUB
V φ
1
2A, Vφ2B
V φ3
NC
GND
VOUT
VDD
CSUB
8
H
40
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
Circuit power
Substrate clock
Substrate bias
Waveform
GND
DC
DC
Fig. 1-2. CCD Block Diagram
Voltage
-8.0 V, 0 V
-8.0 V, 0 V, 15 V
-8.0 V, 0 V
0 V
Aprox. 7 V
15 V
Different from every CCD
Different from every CCD
17
18
19
20
VL
φRG
H φ
H φ
Protection transistor bias
1
2
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
DC
Table 1-1. CCD Pin Description
– 9 –
-8 V
12 V, 17 V
0 V, 5 V
0 V, 5 V
When sensor read-out
3. IC902, IC904, IC908 (H Driver) and IC907 (V Driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC902, IC904 and IC908 are inverter IC which drives the horizontal CCDs (H1 and H2). In addition the XV1-XV3 signals
which are output from IC102 are the vertical transfer clocks,
and the XSG1 and XSG signal which is output from IC102 is
superimposed onto XV2A and XV2B at IC907 in order to generate a ternary pulse. In addition, the XSUB signal which is
output from IC102 is used as the sweep pulse for the electronic shutter, and the RG signal which is output from IC102
is the reset gate clock.
14
CC
1A
1Y
2A
2Y
3A
1
2
3
4
5
V
13
6A
12
6Y
11
5A
10
5Y
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(30) of IC905. There are S/H blocks inside IC905 generated
from the XSHP and XSHD pulses, and it is here that CDS
(correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102 of the CA2 circuit
board. The gain of the AGC amplifier is controlled by serial
data which is output from IC102 of the CA2 circuit board.
PBLK
CCDIN
CLPDM
AUX1IN
AUX2IN
AVDD
CDS
CLP
CLP
4 dB
MUX
AVSS
2~36 dB
2:1
VGA
MUX
10
BUF
2:1
CONTROL
REGISTERS
DIGITAL
INTERFACE
Offset
DAC
8
CLPOB
AD9840
CLP
10-BIT
ADC
BANDGAP
REFERENCE
INTERNAL
BIAS
INTERNAL
TIMING
DRVDD
DRVSS
10
DOUT
VRT
VRB
CML
DVDD
DVSS
4A
3Y
GND
6
7
9
4Y
8
Fig. 1-3. IC902, IC904 and IC908 Block Diagram
DD
V
1
Input
Buffer
XSHT
2
XV3
3
XSG3B
4
XSG3A
5
XV1
6
XSG1B
7
SDATA
SCK
SL
SEN
Fig. 1-5. IC905 Block Diagram
SHT
20
V3B
19
V
L
18
V3A
17
V1B
16
V
H
15
V1A
14
DATA
SHDSHP
CLK
8
9
10
XSG1A
XV4
XV2
Fig. 1-4. IC907 Block Diagram
– 10 –
V4
V2
GND
13
12
11
5. Transfer of Electric Charge by the Horizontal CCD
The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-6.
RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the timing
in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the timing in (3),
and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7.
(1)
H1 H2 H1 H2 H1 HOG RG
CCD OUT
Floating diffusion
(2)
H1 H2 H1 H2 H1 HOG RG
PD
PD
CCD OUT
H1
H2
RG
15.5V
(1) (2) (3)
3.5V
0V
3.5V
0V
12V
(3)
H1 H2 H1 H2 H1 HOG RG
Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage
Reset gate pulse
Direction of transfer
H Register
Electric
charge
Floating diffusion gate is
floated at a high impedance.
C is charged
equivalently
12V Pre-charge drain bias（PD）
Voltage output
Fig. 1-7. Theory of Signal Extraction Operation
CCD OUT
CCD OUT
RG pulse peak signal
Signal voltage
6-2. Iris drive
When in the aperture enable (AE SW) state, the target aperture value signal (IRIS PWM) which is output by the ASIC and
the aperture value signal (HALL OUT +/–) which is output by
the lens are compared so that feedback control can be carried
out.
6-3. Focus drive
When the drive signals (FRSTB, FCW, FOEB and FCLK) which
are output from the ASIC, the focus stepping motor is sinewave driven by the micro-step motor driver (IC953). Detection
of the standard focusing positions is carried out by means of
the photointerruptor (FOCUS PI) inside the lens block.
6-4. Zoom drive
When the drive signals (ZRSTB, ZCW, ZOEB and ZCLK) which
are output from the ASIC, the zoom stepping motor is sinewave driven by the micro-step motor driver (IC954). Detection
of the zoom positions is carried out by means of photoreflector
(ZOOM PI) inside the lens block.
Black level
6. Lens drive block
6-1. Shutter drive
The shutter drive signal (SHUTTER) which is output by the
ASIC and the aperture enable signal (AE SW) cause a positive and negative voltage are applied to the aperture drive coil
to open and close the lens aperture.
6-5. ND filter drive
When the drive signals (ND ON, ND OFF) which are output
from the ASIC, ND filter opens and closes.
– 11 –
3-2. CA2 CIRCUIT DESCRIPTION
1. Circuit Description
1-1. Scannning converter (Interlace converter)
This circuit uses the function of a 64-Mbit SDRAMs to convert the non-interlaced signal which is output from the CCD
into an interlaced signal for the video monitor.
1-2. Camera signal processor
This comprises circuits such as the digial clamp circuit, white
balance circuit, γcircuit, color signal generation circuit, matrix circuit and horizontal aperture circuit.
1. Digital clamp circuit
The optical black section of the CCD extracts 16-pixel averaged values from the subsequent data to make the black level
of the CCD output data uniform for each line. The 16-pixel
averaged value for each line is taken as the sum of the value
for the previous line multiplied by the coefficient k and the
value for the current line multiplied by the coefficient 1-k.
2. White balance circuit
This circuit controls the white balance by using the A WB judgement value computed by the CPU to control the gain for each
R, G and B pixel based on the CCD data which has been
read.
3. γ circuit
This circuit performs (gamma) correction in order to maintain
a linear relat ionship b etween the light i nput to the camer a
and the light output from the picture screen.
4. Color generation circuit
This circuit converts the CCD da ta int o RGB signal s.
5. Matrix circuit
This circuit generates the Y s ignals , R-Y signals and B-Y signals from the RGB signals.
6. Horizontal aperture circuit
This circuit is used generate the aperture signal.
1-3. SDRAM controller
This circuit outputs address, RAS, CAS and AS data for controlling the SDRAM. It also refr eshes the S DRA M.
1-4. PIO
The expansion parallel port can be used for functions such
as stroboscope control and LCD driver control.
1-5. SIO (Serial control)
This is the interface for the 4-bit mic roprocessor.
1-6. USB control
This is comunicated PC with 12 Mbps.
1-7. TG, SG block
This is the timing generation circuit which generates the clocks
(vertical transfer clock and electronic shutter clock) which drive
the CCD.
1-8. 8-bit D/A circuit (Audio)
This circuit converts the audio signals (analog signals) from
the microphone to 8-bit digital signals.
1-9. 8-bit A/D circuit (Audio)
The audio signals which were converted to digial form by the
8-bit A/D circuit are temporarily to a sound buffer and then
recorded in the SSFDC card. During playback, the 8-bit D/A
circuit converts these signals into analog audio signals.
1-10. Sound buffer
Audio memory
1-11. LCD driver
The Y/C signals which are input to the LCD driver are converted to RGB signals, and the timing signal which is necessary for LCD monitor display and the RGB signals are then
supplied to the LCD monitor.
1-12. LCD monitor
This is the image display device which displays the image
signals supplied from the LCD driver.
1-13. UART
This circuit is used for transmitting serial data to a PC. The
interface is RS-232C-compatible.
1-14. MJPEG compression
Still and continuous frame data is converted to JPEG format,
and movie images are compressed and expanded in MJPEG
format.
2. Outline of Operation
When the shutter opens, the reset signals, TEST0, TEST1
and the serial signals (“take a picture” commands) from the
8-bit microprocessor are input and record operation starts.
When the TG drives the CCD, picture data passes through
the A/D and is then input to the ASIC as 10-bit data. This data
then passes through the DCLP, AWB, shutter and γ circuit,
after which it is input to the SDRAM. The AWB, shutter, γ,
and AGC value are computed from this data, and in case of
1-4 times exposures are made to obtain the optimum picture.
The data which has already been stored in the SDRAM is
read by the CPU and color generation is carried out. Each
pixel is interpolated from the surrounding data as being either R, G or B primary color data to produce R, G and B data.
At this time, correction of the lens distortion which is a characteristic of wide-angle lenses is carried out. Aperture correction is carried out, and in case of still picture the data is
then compressed by the JPEG method and in case of picture
it is compressed by MJPEG method and is transfered to MC3
block. And then it is written to iD photo disc. When the data is
to be output to an external device, it is read JPEG picture
data from the iD photo disc and output to PC via the USB or
IEEE1394.
– 12 –
3. LCD Block
During EE, gamma conversion is carried out for the 10-bit
RGB data which is input from the A/D conversion block of the
CCD to the ASIC in order that the γrevised can be displayed
on the video. The YUV of 640 x 480 is then transferred to the
SVRAM.
The data which has accumulated in the SDRAM is after D/A
conversion is carried out by SDRAM control circuit inside the
ASIC, makes Y/C signal, the data is sent to the LCD panel
and displayed.
If the shutter button is pressed in this condition, the 10-bit
data which is output from the A/D conversion block of the
CCD is sent to the SDRAM (DMA transfer), and is displayed
on the LCD as a freeze-frame image.
During playback, the JPEG image data which has accumulated in the iD photo disc is converted to RGB signals. In the
same way as for EE, the data is then sent to the SDRAM,
after which D/A conversion is carried out inside the ASIC,
and then the data is sent to the LCD panel and displayed.
The LCD driver is converted Y/C signals to RGB signals from
ASIC, and these RGB signals and the control signal which is
output by the LCD driver are used to drive the LCD panel.
The RGB signals are 1H transposed so that no DC component is present in the LCD element, and the two horizontal
shift register clocks drive the horizontal shift registers inside
the LCD panel so that the 1H transposed RGB signals are
applied to the LCD panel.
Because the LCD closes more as the difference in potential
between the VCOM (common polar voltage: fixed at DC) and
the R, G and B signals becomes greater, the display becomes
darker; if the difference in potential is smaller, the element
opens and the LCD become brighter. In addition, the brightness and contrast settings for the LCD can be varied by means
of the serial data from the ASIC.
– 13 –
3-3. PW1 POWER CIRCUIT DESCRIPTION
1. Outline
This is the PW1 power circuit for camera block. The oscillation frequency is 400 kHz, and it has no voltage adjustment.
1-1. IC501 and IC511
This is necessary for controlling the power supply for a PWMtype switching regulator, and IC501 is provided with four builtin channels step-down circuits. IC511 is provided with transformer control and step-up circuit for backlight. The oscillation frequency is approx. 200 kHz.
1-2. Short-circuit protection circuit
If output is short-circuited for the length of time (approx. 120
ms) determined by the condenser which are connected to
Pin (17) of IC501 and Pin (17) of IC511, all output is turned
off. The control signal (P ON) are recontrolled or reset on the
power to restore output.
1-3. Head 4 V Power Output
IC501 CH1 is output. It is used for head power supply of disc.
Feedback for output voltage is provided to Pin (29) of IC501
so that PWM control can be carried out.
1-4. Digital 3.3 V System Power Output
IC501 CH2 is output. It is used for digital circuit power supply
of camera. Feedback for output voltage is provided to Pin
(26) of IC501 so that PWM control can be carried out.
1-7. CCD Power Output
IC511 CH1 is output. It is output CCD power supply (5.1 V
(A), 15.0 V (A), –8 V (A)) and digital 5.1 V (D) by transformer
T5101. Feedback for 5.1 V (D) is provided to Pin (29) of IC51 1
so that PWM control can be carried out.
1-8. LCD Panel Power Output
IC511 CH2 is output. It is output LCD panel power supply
(5.1 V (L), 12.4 V (L), 15 V (L)) by transformer T5102. Feedback for 5.1 V (L) is provided to Pin (26) of IC511 so that
PWM control can be carried out.
1-9. EVF Back Light Power Output
IC511 CH3 is output. It is output EVF backlight power supply.
The backlight is controlled constant current 15 mA. Output
voltage is approx. 11-14 V by LED VF is scattered.
1-10. LCD Back Light Power Output
IC511 CH4 is output. It is output EVF backlight power supply.
The backlight is controlled constant current 8.3 mA. Output
voltage is approx. 20-24 V by LED VF is scattered.
1-5. Digital 2.4 V System Power Output
IC501 CH3 is output. It is used for core power supply of camera ASIC. Feedback for output voltage is provided to Pin (11)
of IC501 so that PWM control can be carried out.
1-6. Motor 5 V Power Output
IC501 CH4 is output. It is used for lens circuit power supply.
Feedback for output voltage is provided to Pin (7) of IC501
so that PWM control can be carried out.
– 14 –
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